thread_context.hh revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53    class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU.  It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state.  Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72  public:
73    typedef typename Impl::O3CPU O3CPU;
74
75   /** Pointer to the CPU. */
76    O3CPU *cpu;
77
78    /** Pointer to the thread state that this TC corrseponds to. */
79    O3ThreadState<Impl> *thread;
80
81    /** Returns a pointer to the ITB. */
82    TheISA::TLB *getITBPtr() { return cpu->itb; }
83
84    /** Returns a pointer to the DTB. */
85    TheISA::TLB *getDTBPtr() { return cpu->dtb; }
86
87    CheckerCPU *getCheckerCpuPtr() { return NULL; }
88
89    TheISA::Decoder *
90    getDecoderPtr()
91    {
92        return cpu->fetch.decoder[thread->threadId()];
93    }
94
95    /** Returns a pointer to this CPU. */
96    virtual BaseCPU *getCpuPtr() { return cpu; }
97
98    /** Reads this CPU's ID. */
99    virtual int cpuId() const { return cpu->cpuId(); }
100
101    /** Reads this CPU's Socket ID. */
102    virtual uint32_t socketId() const { return cpu->socketId(); }
103
104    virtual int contextId() const { return thread->contextId(); }
105
106    virtual void setContextId(int id) { thread->setContextId(id); }
107
108    /** Returns this thread's ID number. */
109    virtual int threadId() const { return thread->threadId(); }
110    virtual void setThreadId(int id) { return thread->setThreadId(id); }
111
112    /** Returns a pointer to the system. */
113    virtual System *getSystemPtr() { return cpu->system; }
114
115    /** Returns a pointer to this thread's kernel statistics. */
116    virtual TheISA::Kernel::Statistics *getKernelStats()
117    { return thread->kernelStats; }
118
119    /** Returns a pointer to this thread's process. */
120    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
121
122    virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
123
124    virtual FSTranslatingPortProxy &getVirtProxy();
125
126    virtual void initMemProxies(ThreadContext *tc)
127    { thread->initMemProxies(tc); }
128
129    virtual SETranslatingPortProxy &getMemProxy()
130    { return thread->getMemProxy(); }
131
132    /** Returns this thread's status. */
133    virtual Status status() const { return thread->status(); }
134
135    /** Sets this thread's status. */
136    virtual void setStatus(Status new_status)
137    { thread->setStatus(new_status); }
138
139    /** Set the status to Active. */
140    virtual void activate();
141
142    /** Set the status to Suspended. */
143    virtual void suspend();
144
145    /** Set the status to Halted. */
146    virtual void halt();
147
148    /** Dumps the function profiling information.
149     * @todo: Implement.
150     */
151    virtual void dumpFuncProfile();
152
153    /** Takes over execution of a thread from another CPU. */
154    virtual void takeOverFrom(ThreadContext *old_context);
155
156    /** Registers statistics associated with this TC. */
157    virtual void regStats(const std::string &name);
158
159    /** Reads the last tick that this thread was activated on. */
160    virtual Tick readLastActivate();
161    /** Reads the last tick that this thread was suspended on. */
162    virtual Tick readLastSuspend();
163
164    /** Clears the function profiling information. */
165    virtual void profileClear();
166    /** Samples the function profiling information. */
167    virtual void profileSample();
168
169    /** Copies the architectural registers from another TC into this TC. */
170    virtual void copyArchRegs(ThreadContext *tc);
171
172    /** Resets all architectural registers to 0. */
173    virtual void clearArchRegs();
174
175    /** Reads an integer register. */
176    virtual uint64_t readIntReg(int reg_idx) {
177        return readIntRegFlat(flattenIntIndex(reg_idx));
178    }
179
180    virtual FloatReg readFloatReg(int reg_idx) {
181        return readFloatRegFlat(flattenFloatIndex(reg_idx));
182    }
183
184    virtual FloatRegBits readFloatRegBits(int reg_idx) {
185        return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
186    }
187
188    virtual CCReg readCCReg(int reg_idx) {
189        return readCCRegFlat(flattenCCIndex(reg_idx));
190    }
191
192    virtual const VectorReg &readVectorReg(int reg_idx) {
193        return readVectorRegFlat(flattenVectorIndex(reg_idx));
194    }
195
196    /** Sets an integer register to a value. */
197    virtual void setIntReg(int reg_idx, uint64_t val) {
198        setIntRegFlat(flattenIntIndex(reg_idx), val);
199    }
200
201    virtual void setFloatReg(int reg_idx, FloatReg val) {
202        setFloatRegFlat(flattenFloatIndex(reg_idx), val);
203    }
204
205    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
206        setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
207    }
208
209    virtual void setCCReg(int reg_idx, CCReg val) {
210        setCCRegFlat(flattenCCIndex(reg_idx), val);
211    }
212
213    virtual void setVectorReg(int reg_idx, const VectorReg &val) {
214        setVectorRegFlat(flattenVectorIndex(reg_idx), val);
215    }
216
217    /** Reads this thread's PC state. */
218    virtual TheISA::PCState pcState()
219    { return cpu->pcState(thread->threadId()); }
220
221    /** Sets this thread's PC state. */
222    virtual void pcState(const TheISA::PCState &val);
223
224    virtual void pcStateNoRecord(const TheISA::PCState &val);
225
226    /** Reads this thread's PC. */
227    virtual Addr instAddr()
228    { return cpu->instAddr(thread->threadId()); }
229
230    /** Reads this thread's next PC. */
231    virtual Addr nextInstAddr()
232    { return cpu->nextInstAddr(thread->threadId()); }
233
234    /** Reads this thread's next PC. */
235    virtual MicroPC microPC()
236    { return cpu->microPC(thread->threadId()); }
237
238    /** Reads a miscellaneous register. */
239    virtual MiscReg readMiscRegNoEffect(int misc_reg) const
240    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
241
242    /** Reads a misc. register, including any side-effects the
243     * read might have as defined by the architecture. */
244    virtual MiscReg readMiscReg(int misc_reg)
245    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
246
247    /** Sets a misc. register. */
248    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
249
250    /** Sets a misc. register, including any side-effects the
251     * write might have as defined by the architecture. */
252    virtual void setMiscReg(int misc_reg, const MiscReg &val);
253
254    virtual int flattenIntIndex(int reg);
255    virtual int flattenFloatIndex(int reg);
256    virtual int flattenCCIndex(int reg);
257    virtual int flattenVectorIndex(int reg);
258    virtual int flattenMiscIndex(int reg);
259
260    /** Returns the number of consecutive store conditional failures. */
261    // @todo: Figure out where these store cond failures should go.
262    virtual unsigned readStCondFailures()
263    { return thread->storeCondFailures; }
264
265    /** Sets the number of consecutive store conditional failures. */
266    virtual void setStCondFailures(unsigned sc_failures)
267    { thread->storeCondFailures = sc_failures; }
268
269    /** Executes a syscall in SE mode. */
270    virtual void syscall(int64_t callnum)
271    { return cpu->syscall(callnum, thread->threadId()); }
272
273    /** Reads the funcExeInst counter. */
274    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
275
276    /** Returns pointer to the quiesce event. */
277    virtual EndQuiesceEvent *getQuiesceEvent()
278    {
279        return this->thread->quiesceEvent;
280    }
281    /** check if the cpu is currently in state update mode and squash if not.
282     * This function will return true if a trap is pending or if a fault or
283     * similar is currently writing to the thread context and doesn't want
284     * reset all the state (see noSquashFromTC).
285     */
286    inline void conditionalSquash()
287    {
288        if (!thread->trapPending && !thread->noSquashFromTC)
289            cpu->squashFromTC(thread->threadId());
290    }
291
292    virtual uint64_t readIntRegFlat(int idx);
293    virtual void setIntRegFlat(int idx, uint64_t val);
294
295    virtual FloatReg readFloatRegFlat(int idx);
296    virtual void setFloatRegFlat(int idx, FloatReg val);
297
298    virtual FloatRegBits readFloatRegBitsFlat(int idx);
299    virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
300
301    virtual CCReg readCCRegFlat(int idx);
302    virtual void setCCRegFlat(int idx, CCReg val);
303
304    virtual const VectorReg &readVectorRegFlat(int idx);
305    virtual void setVectorRegFlat(int idx, const VectorReg &val);
306};
307
308#endif
309