thread_context.hh revision 10698:829adc48e175
14483Sgblack@eecs.umich.edu/* 24483Sgblack@eecs.umich.edu * Copyright (c) 2011-2012 ARM Limited 34483Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 44483Sgblack@eecs.umich.edu * All rights reserved 54483Sgblack@eecs.umich.edu * 64483Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 74483Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 84483Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 94483Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 104483Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 114483Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 124483Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 134483Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 144483Sgblack@eecs.umich.edu * 154483Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 164483Sgblack@eecs.umich.edu * All rights reserved. 174483Sgblack@eecs.umich.edu * 184483Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 194483Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 204483Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 214483Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 224483Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 234483Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 244483Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 254483Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 264483Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 274483Sgblack@eecs.umich.edu * this software without specific prior written permission. 284483Sgblack@eecs.umich.edu * 294483Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304483Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314483Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324483Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334483Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344483Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354483Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364483Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374483Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384483Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394483Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404483Sgblack@eecs.umich.edu * 414483Sgblack@eecs.umich.edu * Authors: Kevin Lim 424483Sgblack@eecs.umich.edu */ 434483Sgblack@eecs.umich.edu 444483Sgblack@eecs.umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 454483Sgblack@eecs.umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 464483Sgblack@eecs.umich.edu 474483Sgblack@eecs.umich.edu#include "config/the_isa.hh" 484483Sgblack@eecs.umich.edu#include "cpu/o3/isa_specific.hh" 494483Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 504483Sgblack@eecs.umich.edu 514483Sgblack@eecs.umich.educlass EndQuiesceEvent; 524483Sgblack@eecs.umich.edunamespace Kernel { 534483Sgblack@eecs.umich.edu class Statistics; 544483Sgblack@eecs.umich.edu} 554483Sgblack@eecs.umich.edu 564483Sgblack@eecs.umich.edu/** 574483Sgblack@eecs.umich.edu * Derived ThreadContext class for use with the O3CPU. It 584483Sgblack@eecs.umich.edu * provides the interface for any external objects to access a 594483Sgblack@eecs.umich.edu * single thread's state and some general CPU state. Any time 604483Sgblack@eecs.umich.edu * external objects try to update state through this interface, 614483Sgblack@eecs.umich.edu * the CPU will create an event to squash all in-flight 624483Sgblack@eecs.umich.edu * instructions in order to ensure state is maintained correctly. 634483Sgblack@eecs.umich.edu * It must be defined specifically for the O3CPU because 644483Sgblack@eecs.umich.edu * not all architectural state is located within the O3ThreadState 654483Sgblack@eecs.umich.edu * (such as the commit PC, and registers), and specific actions 664483Sgblack@eecs.umich.edu * must be taken when using this interface (such as squashing all 674507Sgblack@eecs.umich.edu * in-flight instructions when doing a write to this interface). 684483Sgblack@eecs.umich.edu */ 694483Sgblack@eecs.umich.edutemplate <class Impl> 704507Sgblack@eecs.umich.educlass O3ThreadContext : public ThreadContext 714507Sgblack@eecs.umich.edu{ 724507Sgblack@eecs.umich.edu public: 734507Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 744507Sgblack@eecs.umich.edu 754508Sgblack@eecs.umich.edu /** Pointer to the CPU. */ 764508Sgblack@eecs.umich.edu O3CPU *cpu; 774508Sgblack@eecs.umich.edu 784483Sgblack@eecs.umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 794483Sgblack@eecs.umich.edu O3ThreadState<Impl> *thread; 804483Sgblack@eecs.umich.edu 814483Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 824483Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return cpu->itb; } 834483Sgblack@eecs.umich.edu 844483Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 854483Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return cpu->dtb; } 864483Sgblack@eecs.umich.edu 874483Sgblack@eecs.umich.edu CheckerCPU *getCheckerCpuPtr() { return NULL; } 884483Sgblack@eecs.umich.edu 894483Sgblack@eecs.umich.edu TheISA::Decoder * 904483Sgblack@eecs.umich.edu getDecoderPtr() 914483Sgblack@eecs.umich.edu { 924483Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 934483Sgblack@eecs.umich.edu } 944483Sgblack@eecs.umich.edu 954483Sgblack@eecs.umich.edu /** Returns a pointer to this CPU. */ 964483Sgblack@eecs.umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 974483Sgblack@eecs.umich.edu 984483Sgblack@eecs.umich.edu /** Reads this CPU's ID. */ 994483Sgblack@eecs.umich.edu virtual int cpuId() const { return cpu->cpuId(); } 1004483Sgblack@eecs.umich.edu 1014483Sgblack@eecs.umich.edu /** Reads this CPU's Socket ID. */ 1024503Sgblack@eecs.umich.edu virtual uint32_t socketId() const { return cpu->socketId(); } 1034483Sgblack@eecs.umich.edu 1044483Sgblack@eecs.umich.edu virtual int contextId() const { return thread->contextId(); } 1054483Sgblack@eecs.umich.edu 1064483Sgblack@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 1074483Sgblack@eecs.umich.edu 1084483Sgblack@eecs.umich.edu /** Returns this thread's ID number. */ 1094483Sgblack@eecs.umich.edu virtual int threadId() const { return thread->threadId(); } 1104483Sgblack@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 1114483Sgblack@eecs.umich.edu 1124483Sgblack@eecs.umich.edu /** Returns a pointer to the system. */ 1134483Sgblack@eecs.umich.edu virtual System *getSystemPtr() { return cpu->system; } 1144483Sgblack@eecs.umich.edu 1154483Sgblack@eecs.umich.edu /** Returns a pointer to this thread's kernel statistics. */ 1164483Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 1174483Sgblack@eecs.umich.edu { return thread->kernelStats; } 1184483Sgblack@eecs.umich.edu 1194483Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1204483Sgblack@eecs.umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1214483Sgblack@eecs.umich.edu 1224483Sgblack@eecs.umich.edu virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 1234483Sgblack@eecs.umich.edu 1244483Sgblack@eecs.umich.edu virtual FSTranslatingPortProxy &getVirtProxy(); 1254483Sgblack@eecs.umich.edu 1264483Sgblack@eecs.umich.edu virtual void initMemProxies(ThreadContext *tc) 1274483Sgblack@eecs.umich.edu { thread->initMemProxies(tc); } 1284483Sgblack@eecs.umich.edu 1294483Sgblack@eecs.umich.edu virtual SETranslatingPortProxy &getMemProxy() 1304483Sgblack@eecs.umich.edu { return thread->getMemProxy(); } 1314483Sgblack@eecs.umich.edu 1324483Sgblack@eecs.umich.edu /** Returns this thread's status. */ 1334483Sgblack@eecs.umich.edu virtual Status status() const { return thread->status(); } 1344483Sgblack@eecs.umich.edu 1354483Sgblack@eecs.umich.edu /** Sets this thread's status. */ 1364483Sgblack@eecs.umich.edu virtual void setStatus(Status new_status) 1374483Sgblack@eecs.umich.edu { thread->setStatus(new_status); } 1384483Sgblack@eecs.umich.edu 1394483Sgblack@eecs.umich.edu /** Set the status to Active. */ 1404483Sgblack@eecs.umich.edu virtual void activate(); 1414483Sgblack@eecs.umich.edu 1424483Sgblack@eecs.umich.edu /** Set the status to Suspended. */ 1434483Sgblack@eecs.umich.edu virtual void suspend(); 1444483Sgblack@eecs.umich.edu 1454483Sgblack@eecs.umich.edu /** Set the status to Halted. */ 1464483Sgblack@eecs.umich.edu virtual void halt(); 1474503Sgblack@eecs.umich.edu 1484483Sgblack@eecs.umich.edu /** Dumps the function profiling information. 1494483Sgblack@eecs.umich.edu * @todo: Implement. 1504483Sgblack@eecs.umich.edu */ 1514483Sgblack@eecs.umich.edu virtual void dumpFuncProfile(); 1524483Sgblack@eecs.umich.edu 1534483Sgblack@eecs.umich.edu /** Takes over execution of a thread from another CPU. */ 1544483Sgblack@eecs.umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1554483Sgblack@eecs.umich.edu 1564483Sgblack@eecs.umich.edu /** Registers statistics associated with this TC. */ 1574483Sgblack@eecs.umich.edu virtual void regStats(const std::string &name); 1584483Sgblack@eecs.umich.edu 1594483Sgblack@eecs.umich.edu /** Reads the last tick that this thread was activated on. */ 1604483Sgblack@eecs.umich.edu virtual Tick readLastActivate(); 1614483Sgblack@eecs.umich.edu /** Reads the last tick that this thread was suspended on. */ 1624483Sgblack@eecs.umich.edu virtual Tick readLastSuspend(); 1634483Sgblack@eecs.umich.edu 1644483Sgblack@eecs.umich.edu /** Clears the function profiling information. */ 1654483Sgblack@eecs.umich.edu virtual void profileClear(); 1664483Sgblack@eecs.umich.edu /** Samples the function profiling information. */ 1674483Sgblack@eecs.umich.edu virtual void profileSample(); 1684483Sgblack@eecs.umich.edu 1694483Sgblack@eecs.umich.edu /** Copies the architectural registers from another TC into this TC. */ 1704483Sgblack@eecs.umich.edu virtual void copyArchRegs(ThreadContext *tc); 1714483Sgblack@eecs.umich.edu 1724483Sgblack@eecs.umich.edu /** Resets all architectural registers to 0. */ 1734483Sgblack@eecs.umich.edu virtual void clearArchRegs(); 1744483Sgblack@eecs.umich.edu 1754483Sgblack@eecs.umich.edu /** Reads an integer register. */ 1764483Sgblack@eecs.umich.edu virtual uint64_t readIntReg(int reg_idx) { 1774483Sgblack@eecs.umich.edu return readIntRegFlat(flattenIntIndex(reg_idx)); 1784483Sgblack@eecs.umich.edu } 1794483Sgblack@eecs.umich.edu 1804483Sgblack@eecs.umich.edu virtual FloatReg readFloatReg(int reg_idx) { 1814483Sgblack@eecs.umich.edu return readFloatRegFlat(flattenFloatIndex(reg_idx)); 1824483Sgblack@eecs.umich.edu } 1834483Sgblack@eecs.umich.edu 1844483Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx) { 1854483Sgblack@eecs.umich.edu return readFloatRegBitsFlat(flattenFloatIndex(reg_idx)); 1864483Sgblack@eecs.umich.edu } 1874483Sgblack@eecs.umich.edu 1884483Sgblack@eecs.umich.edu virtual CCReg readCCReg(int reg_idx) { 1894483Sgblack@eecs.umich.edu return readCCRegFlat(flattenCCIndex(reg_idx)); 1904483Sgblack@eecs.umich.edu } 1914483Sgblack@eecs.umich.edu 1924483Sgblack@eecs.umich.edu /** Sets an integer register to a value. */ 1934483Sgblack@eecs.umich.edu virtual void setIntReg(int reg_idx, uint64_t val) { 1944483Sgblack@eecs.umich.edu setIntRegFlat(flattenIntIndex(reg_idx), val); 1954483Sgblack@eecs.umich.edu } 1964483Sgblack@eecs.umich.edu 1974483Sgblack@eecs.umich.edu virtual void setFloatReg(int reg_idx, FloatReg val) { 1984483Sgblack@eecs.umich.edu setFloatRegFlat(flattenFloatIndex(reg_idx), val); 1994483Sgblack@eecs.umich.edu } 2004512Sgblack@eecs.umich.edu 2014502Sgblack@eecs.umich.edu virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { 2024502Sgblack@eecs.umich.edu setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val); 2034502Sgblack@eecs.umich.edu } 2044502Sgblack@eecs.umich.edu 2054502Sgblack@eecs.umich.edu virtual void setCCReg(int reg_idx, CCReg val) { 2064502Sgblack@eecs.umich.edu setCCRegFlat(flattenCCIndex(reg_idx), val); 2074512Sgblack@eecs.umich.edu } 2084512Sgblack@eecs.umich.edu 2094512Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 2104483Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() 2114483Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 2124483Sgblack@eecs.umich.edu 2134483Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 2144483Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val); 2154512Sgblack@eecs.umich.edu 2164512Sgblack@eecs.umich.edu virtual void pcStateNoRecord(const TheISA::PCState &val); 2174512Sgblack@eecs.umich.edu 2184512Sgblack@eecs.umich.edu /** Reads this thread's PC. */ 2194483Sgblack@eecs.umich.edu virtual Addr instAddr() 2204483Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 2214483Sgblack@eecs.umich.edu 2224483Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 2234483Sgblack@eecs.umich.edu virtual Addr nextInstAddr() 2244483Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 2254512Sgblack@eecs.umich.edu 2264512Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 2274483Sgblack@eecs.umich.edu virtual MicroPC microPC() 2284483Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 2294483Sgblack@eecs.umich.edu 2304483Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 2314483Sgblack@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) const 2324512Sgblack@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 2334512Sgblack@eecs.umich.edu 2344483Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the 2354566Sgblack@eecs.umich.edu * read might have as defined by the architecture. */ 2364483Sgblack@eecs.umich.edu virtual MiscReg readMiscReg(int misc_reg) 2374566Sgblack@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 2384566Sgblack@eecs.umich.edu 2394566Sgblack@eecs.umich.edu /** Sets a misc. register. */ 2404566Sgblack@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2414566Sgblack@eecs.umich.edu 2424566Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the 2434566Sgblack@eecs.umich.edu * write might have as defined by the architecture. */ 2444483Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val); 2454483Sgblack@eecs.umich.edu 2464483Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg); 2474512Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg); 2484483Sgblack@eecs.umich.edu virtual int flattenCCIndex(int reg); 2494483Sgblack@eecs.umich.edu virtual int flattenMiscIndex(int reg); 2504483Sgblack@eecs.umich.edu 2514483Sgblack@eecs.umich.edu /** Returns the number of consecutive store conditional failures. */ 2524483Sgblack@eecs.umich.edu // @todo: Figure out where these store cond failures should go. 2534483Sgblack@eecs.umich.edu virtual unsigned readStCondFailures() 2544483Sgblack@eecs.umich.edu { return thread->storeCondFailures; } 2554483Sgblack@eecs.umich.edu 2564483Sgblack@eecs.umich.edu /** Sets the number of consecutive store conditional failures. */ 2574483Sgblack@eecs.umich.edu virtual void setStCondFailures(unsigned sc_failures) 2584512Sgblack@eecs.umich.edu { thread->storeCondFailures = sc_failures; } 2594483Sgblack@eecs.umich.edu 2604483Sgblack@eecs.umich.edu /** Executes a syscall in SE mode. */ 2614483Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) 2624483Sgblack@eecs.umich.edu { return cpu->syscall(callnum, thread->threadId()); } 2634512Sgblack@eecs.umich.edu 2644512Sgblack@eecs.umich.edu /** Reads the funcExeInst counter. */ 2654483Sgblack@eecs.umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 2664483Sgblack@eecs.umich.edu 2674483Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 2684483Sgblack@eecs.umich.edu virtual EndQuiesceEvent *getQuiesceEvent() 2694483Sgblack@eecs.umich.edu { 2704512Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 2714512Sgblack@eecs.umich.edu } 2724483Sgblack@eecs.umich.edu /** check if the cpu is currently in state update mode and squash if not. 2734483Sgblack@eecs.umich.edu * This function will return true if a trap is pending or if a fault or 2744483Sgblack@eecs.umich.edu * similar is currently writing to the thread context and doesn't want 2754483Sgblack@eecs.umich.edu * reset all the state (see noSquashFromTC). 2764483Sgblack@eecs.umich.edu */ 2774483Sgblack@eecs.umich.edu inline void conditionalSquash() 2784483Sgblack@eecs.umich.edu { 2794483Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->noSquashFromTC) 2804483Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2814483Sgblack@eecs.umich.edu } 2824483Sgblack@eecs.umich.edu 2834483Sgblack@eecs.umich.edu virtual uint64_t readIntRegFlat(int idx); 2844483Sgblack@eecs.umich.edu virtual void setIntRegFlat(int idx, uint64_t val); 2854483Sgblack@eecs.umich.edu 2864483Sgblack@eecs.umich.edu virtual FloatReg readFloatRegFlat(int idx); 2874483Sgblack@eecs.umich.edu virtual void setFloatRegFlat(int idx, FloatReg val); 2884483Sgblack@eecs.umich.edu 2894483Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBitsFlat(int idx); 2904483Sgblack@eecs.umich.edu virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); 2914483Sgblack@eecs.umich.edu 2924483Sgblack@eecs.umich.edu virtual CCReg readCCRegFlat(int idx); 2934483Sgblack@eecs.umich.edu virtual void setCCRegFlat(int idx, CCReg val); 2944483Sgblack@eecs.umich.edu}; 2954483Sgblack@eecs.umich.edu 2964483Sgblack@eecs.umich.edu#endif 2974483Sgblack@eecs.umich.edu