thread_context.hh revision 9180
112SN/A/* 21762SN/A * Copyright (c) 2011 ARM Limited 312SN/A * All rights reserved 412SN/A * 512SN/A * The license below extends only to copyright in the software and shall 612SN/A * not be construed as granting a license to any other intellectual 712SN/A * property including but not limited to intellectual property relating 812SN/A * to a hardware implementation of the functionality of the software 912SN/A * licensed hereunder. You may use the software subject to the license 1012SN/A * terms below provided that you ensure that this notice is replicated 1112SN/A * unmodified and in its entirety in all distributions of the software, 1212SN/A * modified or unmodified, in source code or in binary form. 1312SN/A * 1412SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 1512SN/A * All rights reserved. 1612SN/A * 1712SN/A * Redistribution and use in source and binary forms, with or without 1812SN/A * modification, are permitted provided that the following conditions are 1912SN/A * met: redistributions of source code must retain the above copyright 2012SN/A * notice, this list of conditions and the following disclaimer; 2112SN/A * redistributions in binary form must reproduce the above copyright 2212SN/A * notice, this list of conditions and the following disclaimer in the 2312SN/A * documentation and/or other materials provided with the distribution; 2412SN/A * neither the name of the copyright holders nor the names of its 2512SN/A * contributors may be used to endorse or promote products derived from 2612SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342634Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35468SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3656SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374484Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382439SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3956SN/A * 402423SN/A * Authors: Kevin Lim 412423SN/A */ 4212SN/A 4312SN/A#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 4412SN/A#define __CPU_O3_THREAD_CONTEXT_HH__ 4512SN/A 4612SN/A#include "config/the_isa.hh" 47443SN/A#include "cpu/o3/isa_specific.hh" 48443SN/A#include "cpu/thread_context.hh" 492207SN/A 502207SN/Aclass EndQuiesceEvent; 51443SN/Anamespace Kernel { 52468SN/A class Statistics; 531708SN/A} 541708SN/A 55443SN/A/** 56468SN/A * Derived ThreadContext class for use with the O3CPU. It 57443SN/A * provides the interface for any external objects to access a 58468SN/A * single thread's state and some general CPU state. Any time 59443SN/A * external objects try to update state through this interface, 60443SN/A * the CPU will create an event to squash all in-flight 61468SN/A * instructions in order to ensure state is maintained correctly. 62468SN/A * It must be defined specifically for the O3CPU because 63443SN/A * not all architectural state is located within the O3ThreadState 64443SN/A * (such as the commit PC, and registers), and specific actions 65443SN/A * must be taken when using this interface (such as squashing all 662476SN/A * in-flight instructions when doing a write to this interface). 672207SN/A */ 682207SN/Atemplate <class Impl> 692207SN/Aclass O3ThreadContext : public ThreadContext 702207SN/A{ 712207SN/A public: 724111Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 734111Sgblack@eecs.umich.edu 742620SN/A /** Pointer to the CPU. */ 754111Sgblack@eecs.umich.edu O3CPU *cpu; 764111Sgblack@eecs.umich.edu 774111Sgblack@eecs.umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 784111Sgblack@eecs.umich.edu O3ThreadState<Impl> *thread; 794111Sgblack@eecs.umich.edu 802207SN/A /** Returns a pointer to the ITB. */ 812207SN/A TheISA::TLB *getITBPtr() { return cpu->itb; } 822472SN/A 834166Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 844166Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return cpu->dtb; } 854166Sgblack@eecs.umich.edu 864166Sgblack@eecs.umich.edu CheckerCPU *getCheckerCpuPtr() { return NULL; } 874166Sgblack@eecs.umich.edu 884166Sgblack@eecs.umich.edu TheISA::Decoder * 892207SN/A getDecoderPtr() 902207SN/A { 912207SN/A return cpu->fetch.decoder[thread->threadId()]; 922600SN/A } 932207SN/A 942207SN/A /** Returns a pointer to this CPU. */ 952207SN/A virtual BaseCPU *getCpuPtr() { return cpu; } 962207SN/A 972207SN/A /** Reads this CPU's ID. */ 982207SN/A virtual int cpuId() { return cpu->cpuId(); } 992238SN/A 1002207SN/A virtual int contextId() { return thread->contextId(); } 1012207SN/A 1022207SN/A virtual void setContextId(int id) { thread->setContextId(id); } 1032207SN/A 1042207SN/A /** Returns this thread's ID number. */ 1052238SN/A virtual int threadId() { return thread->threadId(); } 1062207SN/A virtual void setThreadId(int id) { return thread->setThreadId(id); } 1072207SN/A 1082238SN/A /** Returns a pointer to the system. */ 1092207SN/A virtual System *getSystemPtr() { return cpu->system; } 1102207SN/A 1112207SN/A /** Returns a pointer to this thread's kernel statistics. */ 1122207SN/A virtual TheISA::Kernel::Statistics *getKernelStats() 1132238SN/A { return thread->kernelStats; } 1142238SN/A 1152600SN/A /** Returns a pointer to this thread's process. */ 1162238SN/A virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1172238SN/A 1182238SN/A virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 1192238SN/A 1202238SN/A virtual FSTranslatingPortProxy &getVirtProxy(); 1212238SN/A 1222238SN/A virtual void initMemProxies(ThreadContext *tc) 1232238SN/A { thread->initMemProxies(tc); } 1242238SN/A 1252238SN/A virtual SETranslatingPortProxy &getMemProxy() 1262600SN/A { return thread->getMemProxy(); } 1272238SN/A 1282238SN/A /** Returns this thread's status. */ 1292238SN/A virtual Status status() const { return thread->status(); } 1302238SN/A 1312238SN/A /** Sets this thread's status. */ 1322238SN/A virtual void setStatus(Status new_status) 1332238SN/A { thread->setStatus(new_status); } 1342238SN/A 1352238SN/A /** Set the status to Active. Optional delay indicates number of 1362238SN/A * cycles to wait before beginning execution. */ 1372238SN/A virtual void activate(Cycles delay = Cycles(1)); 1382238SN/A 1392238SN/A /** Set the status to Suspended. */ 1402238SN/A virtual void suspend(Cycles delay = Cycles(0)); 1412238SN/A 1422238SN/A /** Set the status to Halted. */ 1432238SN/A virtual void halt(Cycles delay = Cycles(0)); 1442238SN/A 1452238SN/A /** Dumps the function profiling information. 1462238SN/A * @todo: Implement. 1472238SN/A */ 1482238SN/A virtual void dumpFuncProfile(); 1492600SN/A 1502600SN/A /** Takes over execution of a thread from another CPU. */ 1512600SN/A virtual void takeOverFrom(ThreadContext *old_context); 1522600SN/A 1532600SN/A /** Registers statistics associated with this TC. */ 1542238SN/A virtual void regStats(const std::string &name); 1552238SN/A 1562238SN/A /** Serializes state. */ 1572472SN/A virtual void serialize(std::ostream &os); 1582976Sgblack@eecs.umich.edu /** Unserializes state. */ 1592976Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1602976Sgblack@eecs.umich.edu 1612976Sgblack@eecs.umich.edu /** Reads the last tick that this thread was activated on. */ 1622976Sgblack@eecs.umich.edu virtual Tick readLastActivate(); 1632976Sgblack@eecs.umich.edu /** Reads the last tick that this thread was suspended on. */ 1642976Sgblack@eecs.umich.edu virtual Tick readLastSuspend(); 1652976Sgblack@eecs.umich.edu 1662976Sgblack@eecs.umich.edu /** Clears the function profiling information. */ 1672976Sgblack@eecs.umich.edu virtual void profileClear(); 1682976Sgblack@eecs.umich.edu /** Samples the function profiling information. */ 1692976Sgblack@eecs.umich.edu virtual void profileSample(); 1702976Sgblack@eecs.umich.edu 1712976Sgblack@eecs.umich.edu /** Copies the architectural registers from another TC into this TC. */ 1722976Sgblack@eecs.umich.edu virtual void copyArchRegs(ThreadContext *tc); 1732976Sgblack@eecs.umich.edu 1742976Sgblack@eecs.umich.edu /** Resets all architectural registers to 0. */ 1752976Sgblack@eecs.umich.edu virtual void clearArchRegs(); 1762976Sgblack@eecs.umich.edu 1772976Sgblack@eecs.umich.edu /** Reads an integer register. */ 1782976Sgblack@eecs.umich.edu virtual uint64_t readIntReg(int reg_idx); 1792976Sgblack@eecs.umich.edu 1802976Sgblack@eecs.umich.edu virtual FloatReg readFloatReg(int reg_idx); 1812976Sgblack@eecs.umich.edu 1822976Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx); 1832976Sgblack@eecs.umich.edu 1842976Sgblack@eecs.umich.edu /** Sets an integer register to a value. */ 1852976Sgblack@eecs.umich.edu virtual void setIntReg(int reg_idx, uint64_t val); 1862976Sgblack@eecs.umich.edu 1872976Sgblack@eecs.umich.edu virtual void setFloatReg(int reg_idx, FloatReg val); 1882238SN/A 1892976Sgblack@eecs.umich.edu virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 19012SN/A 19112SN/A /** Reads this thread's PC state. */ 19212SN/A virtual TheISA::PCState pcState() 19312SN/A { return cpu->pcState(thread->threadId()); } 19412SN/A 195360SN/A /** Sets this thread's PC state. */ 196360SN/A virtual void pcState(const TheISA::PCState &val); 197360SN/A 198443SN/A virtual void pcStateNoRecord(const TheISA::PCState &val); 19912SN/A 200443SN/A /** Reads this thread's PC. */ 201443SN/A virtual Addr instAddr() 20212SN/A { return cpu->instAddr(thread->threadId()); } 203468SN/A 2041708SN/A /** Reads this thread's next PC. */ 2051708SN/A virtual Addr nextInstAddr() 20612SN/A { return cpu->nextInstAddr(thread->threadId()); } 207468SN/A 208443SN/A /** Reads this thread's next PC. */ 209468SN/A virtual MicroPC microPC() 210443SN/A { return cpu->microPC(thread->threadId()); } 21112SN/A 212468SN/A /** Reads a miscellaneous register. */ 213468SN/A virtual MiscReg readMiscRegNoEffect(int misc_reg) 214443SN/A { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 21512SN/A 21612SN/A /** Reads a misc. register, including any side-effects the 217468SN/A * read might have as defined by the architecture. */ 21812SN/A virtual MiscReg readMiscReg(int misc_reg) 2192472SN/A { return cpu->readMiscReg(misc_reg, thread->threadId()); } 220468SN/A 221468SN/A /** Sets a misc. register. */ 222468SN/A virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 223468SN/A 224468SN/A /** Sets a misc. register, including any side-effects the 225468SN/A * write might have as defined by the architecture. */ 226468SN/A virtual void setMiscReg(int misc_reg, const MiscReg &val); 227468SN/A 228468SN/A virtual int flattenIntIndex(int reg); 229468SN/A virtual int flattenFloatIndex(int reg); 230468SN/A 231468SN/A /** Returns the number of consecutive store conditional failures. */ 232468SN/A // @todo: Figure out where these store cond failures should go. 233468SN/A virtual unsigned readStCondFailures() 234468SN/A { return thread->storeCondFailures; } 235468SN/A 236468SN/A /** Sets the number of consecutive store conditional failures. */ 237468SN/A virtual void setStCondFailures(unsigned sc_failures) 2382420SN/A { thread->storeCondFailures = sc_failures; } 239468SN/A 240468SN/A // Only really makes sense for old CPU model. Lots of code 241468SN/A // outside the CPU still checks this function, so it will 242468SN/A // always return false to keep everything working. 243468SN/A /** Checks if the thread is misspeculating. Because it is 244468SN/A * very difficult to determine if the thread is 2452420SN/A * misspeculating, this is set as false. */ 2462476SN/A virtual bool misspeculating() { return false; } 247468SN/A 248468SN/A /** Executes a syscall in SE mode. */ 2492420SN/A virtual void syscall(int64_t callnum) 250468SN/A { return cpu->syscall(callnum, thread->threadId()); } 251468SN/A 252468SN/A /** Reads the funcExeInst counter. */ 253468SN/A virtual Counter readFuncExeInst() { return thread->funcExeInst; } 254468SN/A 255468SN/A /** Returns pointer to the quiesce event. */ 256468SN/A virtual EndQuiesceEvent *getQuiesceEvent() 257468SN/A { 2582420SN/A return this->thread->quiesceEvent; 2592476SN/A } 2602476SN/A 2612476SN/A}; 2622476SN/A 263468SN/A#endif 264468SN/A