thread_context.hh revision 8799
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu */ 302817Sksewell@umich.edu 312817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 322817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 332817Sksewell@umich.edu 346658Snate@binkert.org#include "config/the_isa.hh" 358229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 362935Sksewell@umich.edu#include "cpu/thread_context.hh" 372817Sksewell@umich.edu 382834Sksewell@umich.educlass EndQuiesceEvent; 392834Sksewell@umich.edunamespace Kernel { 402834Sksewell@umich.edu class Statistics; 412834Sksewell@umich.edu}; 422834Sksewell@umich.edu 432834Sksewell@umich.educlass TranslatingPort; 442834Sksewell@umich.edu 452817Sksewell@umich.edu/** 462817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 472817Sksewell@umich.edu * provides the interface for any external objects to access a 482817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 492817Sksewell@umich.edu * external objects try to update state through this interface, 502817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 512817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 522817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 532817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 542817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 552817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 562817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 572817Sksewell@umich.edu */ 582817Sksewell@umich.edutemplate <class Impl> 592817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 602817Sksewell@umich.edu{ 612817Sksewell@umich.edu public: 622817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 632817Sksewell@umich.edu 642817Sksewell@umich.edu /** Pointer to the CPU. */ 652817Sksewell@umich.edu O3CPU *cpu; 662817Sksewell@umich.edu 672817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 682817Sksewell@umich.edu O3ThreadState<Impl> *thread; 692817Sksewell@umich.edu 703784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 716022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return cpu->itb; } 723784Sgblack@eecs.umich.edu 733784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 746022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return cpu->dtb; } 753784Sgblack@eecs.umich.edu 768541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return &cpu->fetch.decoder; } 778541Sgblack@eecs.umich.edu 782817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 792817Sksewell@umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 802817Sksewell@umich.edu 812817Sksewell@umich.edu /** Reads this CPU's ID. */ 825712Shsul@eecs.umich.edu virtual int cpuId() { return cpu->cpuId(); } 832817Sksewell@umich.edu 845714Shsul@eecs.umich.edu virtual int contextId() { return thread->contextId(); } 855714Shsul@eecs.umich.edu 865714Shsul@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 875714Shsul@eecs.umich.edu 885715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 895715Shsul@eecs.umich.edu virtual int threadId() { return thread->threadId(); } 905715Shsul@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 915715Shsul@eecs.umich.edu 922817Sksewell@umich.edu /** Returns a pointer to the system. */ 932817Sksewell@umich.edu virtual System *getSystemPtr() { return cpu->system; } 942817Sksewell@umich.edu 952817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 963548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 972817Sksewell@umich.edu { return thread->kernelStats; } 982817Sksewell@umich.edu 998541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1008541Sgblack@eecs.umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1018754Sgblack@eecs.umich.edu 1028706Sandreas.hansson@arm.com virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); } 1032817Sksewell@umich.edu 1048706Sandreas.hansson@arm.com virtual FSTranslatingPortProxy* getVirtProxy(); 1053675Sktlim@umich.edu 1068706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) 1078706Sandreas.hansson@arm.com { thread->initMemProxies(tc); } 1088799Sgblack@eecs.umich.edu 1098706Sandreas.hansson@arm.com virtual SETranslatingPortProxy* getMemProxy() 1108706Sandreas.hansson@arm.com { return thread->getMemProxy(); } 1112817Sksewell@umich.edu 1122817Sksewell@umich.edu /** Returns this thread's status. */ 1132817Sksewell@umich.edu virtual Status status() const { return thread->status(); } 1142817Sksewell@umich.edu 1152817Sksewell@umich.edu /** Sets this thread's status. */ 1162817Sksewell@umich.edu virtual void setStatus(Status new_status) 1172817Sksewell@umich.edu { thread->setStatus(new_status); } 1182817Sksewell@umich.edu 1192817Sksewell@umich.edu /** Set the status to Active. Optional delay indicates number of 1202817Sksewell@umich.edu * cycles to wait before beginning execution. */ 1212817Sksewell@umich.edu virtual void activate(int delay = 1); 1222817Sksewell@umich.edu 1232817Sksewell@umich.edu /** Set the status to Suspended. */ 1245250Sksewell@umich.edu virtual void suspend(int delay = 0); 1252817Sksewell@umich.edu 1262817Sksewell@umich.edu /** Set the status to Halted. */ 1275250Sksewell@umich.edu virtual void halt(int delay = 0); 1282817Sksewell@umich.edu 1292817Sksewell@umich.edu /** Dumps the function profiling information. 1302817Sksewell@umich.edu * @todo: Implement. 1312817Sksewell@umich.edu */ 1322817Sksewell@umich.edu virtual void dumpFuncProfile(); 1338777Sgblack@eecs.umich.edu 1342817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 1352817Sksewell@umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1362817Sksewell@umich.edu 1372817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 1382817Sksewell@umich.edu virtual void regStats(const std::string &name); 1392817Sksewell@umich.edu 1402817Sksewell@umich.edu /** Serializes state. */ 1412817Sksewell@umich.edu virtual void serialize(std::ostream &os); 1422817Sksewell@umich.edu /** Unserializes state. */ 1432817Sksewell@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1442817Sksewell@umich.edu 1452817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 1462817Sksewell@umich.edu virtual Tick readLastActivate(); 1472817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 1482817Sksewell@umich.edu virtual Tick readLastSuspend(); 1492817Sksewell@umich.edu 1502817Sksewell@umich.edu /** Clears the function profiling information. */ 1512817Sksewell@umich.edu virtual void profileClear(); 1522817Sksewell@umich.edu /** Samples the function profiling information. */ 1532817Sksewell@umich.edu virtual void profileSample(); 1542817Sksewell@umich.edu 1552817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 1562817Sksewell@umich.edu virtual void copyArchRegs(ThreadContext *tc); 1572817Sksewell@umich.edu 1582817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 1592817Sksewell@umich.edu virtual void clearArchRegs(); 1602817Sksewell@umich.edu 1612817Sksewell@umich.edu /** Reads an integer register. */ 1622817Sksewell@umich.edu virtual uint64_t readIntReg(int reg_idx); 1632817Sksewell@umich.edu 1642817Sksewell@umich.edu virtual FloatReg readFloatReg(int reg_idx); 1652817Sksewell@umich.edu 1662817Sksewell@umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx); 1672817Sksewell@umich.edu 1682817Sksewell@umich.edu /** Sets an integer register to a value. */ 1692817Sksewell@umich.edu virtual void setIntReg(int reg_idx, uint64_t val); 1702817Sksewell@umich.edu 1712817Sksewell@umich.edu virtual void setFloatReg(int reg_idx, FloatReg val); 1722817Sksewell@umich.edu 1732817Sksewell@umich.edu virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 1742817Sksewell@umich.edu 1757720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 1767720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() 1777720Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 1787720Sgblack@eecs.umich.edu 1797720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 1807720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val); 1817720Sgblack@eecs.umich.edu 1822817Sksewell@umich.edu /** Reads this thread's PC. */ 1837720Sgblack@eecs.umich.edu virtual Addr instAddr() 1847720Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 1852817Sksewell@umich.edu 1862817Sksewell@umich.edu /** Reads this thread's next PC. */ 1877720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() 1887720Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 1892817Sksewell@umich.edu 1907720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 1917720Sgblack@eecs.umich.edu virtual MicroPC microPC() 1927720Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 1935259Sksewell@umich.edu 1942817Sksewell@umich.edu /** Reads a miscellaneous register. */ 1954172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) 1965715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 1974172Ssaidi@eecs.umich.edu 1984172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 1994172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 2002817Sksewell@umich.edu virtual MiscReg readMiscReg(int misc_reg) 2015715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 2022817Sksewell@umich.edu 2032817Sksewell@umich.edu /** Sets a misc. register. */ 2044172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2052817Sksewell@umich.edu 2062817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 2072817Sksewell@umich.edu * write might have as defined by the architecture. */ 2084172Ssaidi@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val); 2092817Sksewell@umich.edu 2106313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg); 2116313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg); 2126313Sgblack@eecs.umich.edu 2132817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 2142817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 2152817Sksewell@umich.edu virtual unsigned readStCondFailures() 2162817Sksewell@umich.edu { return thread->storeCondFailures; } 2172817Sksewell@umich.edu 2182817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 2192817Sksewell@umich.edu virtual void setStCondFailures(unsigned sc_failures) 2202817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 2212817Sksewell@umich.edu 2222817Sksewell@umich.edu // Only really makes sense for old CPU model. Lots of code 2232817Sksewell@umich.edu // outside the CPU still checks this function, so it will 2242817Sksewell@umich.edu // always return false to keep everything working. 2252817Sksewell@umich.edu /** Checks if the thread is misspeculating. Because it is 2262817Sksewell@umich.edu * very difficult to determine if the thread is 2272817Sksewell@umich.edu * misspeculating, this is set as false. */ 2282817Sksewell@umich.edu virtual bool misspeculating() { return false; } 2292817Sksewell@umich.edu 2302817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 2312817Sksewell@umich.edu virtual void syscall(int64_t callnum) 2325715Shsul@eecs.umich.edu { return cpu->syscall(callnum, thread->threadId()); } 2332817Sksewell@umich.edu 2342817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 2352817Sksewell@umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 2368777Sgblack@eecs.umich.edu 2375595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 2385595Sgblack@eecs.umich.edu virtual EndQuiesceEvent *getQuiesceEvent() 2395595Sgblack@eecs.umich.edu { 2405595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 2415595Sgblack@eecs.umich.edu } 2425595Sgblack@eecs.umich.edu 2432817Sksewell@umich.edu}; 2442817Sksewell@umich.edu 2452817Sksewell@umich.edu#endif 246