thread_context.hh revision 3789
111570SCurtis.Dunham@arm.com/* 211570SCurtis.Dunham@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 38347SN/A * All rights reserved. 48347SN/A * 56112SN/A * Redistribution and use in source and binary forms, with or without 611960Sgabeblack@google.com * modification, are permitted provided that the following conditions are 711960Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 811960Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 911956Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1010798Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 116112SN/A * documentation and/or other materials provided with the distribution; 126112SN/A * neither the name of the copyright holders nor the names of its 1310798Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 1410798Ssteve.reinhardt@amd.com * this software without specific prior written permission. 1511956Sgabeblack@google.com * 1611956Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711731Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811956Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196112SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011731Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111731Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211103Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311731Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411680SCurtis.Dunham@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511731Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266112SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710900Snilay@cs.wisc.edu * 2811956Sgabeblack@google.com * Authors: Kevin Lim 2911731Sjason@lowepower.com */ 3011731Sjason@lowepower.com 3111956Sgabeblack@google.com#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 3211956Sgabeblack@google.com#define __CPU_O3_THREAD_CONTEXT_HH__ 336112SN/A 3411956Sgabeblack@google.com#include "cpu/thread_context.hh" 3511956Sgabeblack@google.com#include "cpu/o3/isa_specific.hh" 3611731Sjason@lowepower.com 3711956Sgabeblack@google.comclass EndQuiesceEvent; 3811680SCurtis.Dunham@arm.comnamespace Kernel { 3911731Sjason@lowepower.com class Statistics; 406112SN/A}; 4111731Sjason@lowepower.com 4211731Sjason@lowepower.comclass TranslatingPort; 4311680SCurtis.Dunham@arm.com 4411731Sjason@lowepower.com/** 4511570SCurtis.Dunham@arm.com * Derived ThreadContext class for use with the O3CPU. It 4611731Sjason@lowepower.com * provides the interface for any external objects to access a 476112SN/A * single thread's state and some general CPU state. Any time 4811680SCurtis.Dunham@arm.com * external objects try to update state through this interface, 4911680SCurtis.Dunham@arm.com * the CPU will create an event to squash all in-flight 5011956Sgabeblack@google.com * instructions in order to ensure state is maintained correctly. 5111956Sgabeblack@google.com * It must be defined specifically for the O3CPU because 5211680SCurtis.Dunham@arm.com * not all architectural state is located within the O3ThreadState 5311956Sgabeblack@google.com * (such as the commit PC, and registers), and specific actions 546112SN/A * must be taken when using this interface (such as squashing all 5511956Sgabeblack@google.com * in-flight instructions when doing a write to this interface). 5611956Sgabeblack@google.com */ 5711731Sjason@lowepower.comtemplate <class Impl> 5811956Sgabeblack@google.comclass O3ThreadContext : public ThreadContext 5911680SCurtis.Dunham@arm.com{ 6011731Sjason@lowepower.com public: 616112SN/A typedef typename Impl::O3CPU O3CPU; 6211570SCurtis.Dunham@arm.com 6311731Sjason@lowepower.com /** Pointer to the CPU. */ 6411103Snilay@cs.wisc.edu O3CPU *cpu; 6511680SCurtis.Dunham@arm.com 6611731Sjason@lowepower.com /** Pointer to the thread state that this TC corrseponds to. */ 6711731Sjason@lowepower.com O3ThreadState<Impl> *thread; 686112SN/A 6911731Sjason@lowepower.com#if FULL_SYSTEM 7011731Sjason@lowepower.com /** Returns a pointer to the ITB. */ 7111956Sgabeblack@google.com TheISA::ITB *getITBPtr() { return cpu->itb; } 7211956Sgabeblack@google.com 7311731Sjason@lowepower.com /** Returns a pointer to the DTB. */ 7411956Sgabeblack@google.com TheISA::DTB *getDTBPtr() { return cpu->dtb; } 756112SN/A#endif 7611956Sgabeblack@google.com 7711956Sgabeblack@google.com /** Returns a pointer to this CPU. */ 7811731Sjason@lowepower.com virtual BaseCPU *getCpuPtr() { return cpu; } 7911956Sgabeblack@google.com 8011680SCurtis.Dunham@arm.com /** Sets this CPU's ID. */ 8111956Sgabeblack@google.com virtual void setCpuId(int id) { cpu->setCpuId(id); } 826112SN/A 836112SN/A /** Reads this CPU's ID. */ 8411960Sgabeblack@google.com virtual int readCpuId() { return cpu->readCpuId(); } 85 86#if FULL_SYSTEM 87 /** Returns a pointer to the system. */ 88 virtual System *getSystemPtr() { return cpu->system; } 89 90 /** Returns a pointer to physical memory. */ 91 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } 92 93 /** Returns a pointer to this thread's kernel statistics. */ 94 virtual TheISA::Kernel::Statistics *getKernelStats() 95 { return thread->kernelStats; } 96 97 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 98 99 virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL); 100 101 void delVirtPort(VirtualPort *vp); 102 103 virtual void connectMemPorts() { thread->connectMemPorts(); } 104#else 105 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 106 107 /** Returns a pointer to this thread's process. */ 108 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 109#endif 110 /** Returns this thread's status. */ 111 virtual Status status() const { return thread->status(); } 112 113 /** Sets this thread's status. */ 114 virtual void setStatus(Status new_status) 115 { thread->setStatus(new_status); } 116 117 /** Set the status to Active. Optional delay indicates number of 118 * cycles to wait before beginning execution. */ 119 virtual void activate(int delay = 1); 120 121 /** Set the status to Suspended. */ 122 virtual void suspend(); 123 124 /** Set the status to Unallocated. */ 125 virtual void deallocate(int delay = 0); 126 127 /** Set the status to Halted. */ 128 virtual void halt(); 129 130#if FULL_SYSTEM 131 /** Dumps the function profiling information. 132 * @todo: Implement. 133 */ 134 virtual void dumpFuncProfile(); 135#endif 136 /** Takes over execution of a thread from another CPU. */ 137 virtual void takeOverFrom(ThreadContext *old_context); 138 139 /** Registers statistics associated with this TC. */ 140 virtual void regStats(const std::string &name); 141 142 /** Serializes state. */ 143 virtual void serialize(std::ostream &os); 144 /** Unserializes state. */ 145 virtual void unserialize(Checkpoint *cp, const std::string §ion); 146 147#if FULL_SYSTEM 148 /** Reads the last tick that this thread was activated on. */ 149 virtual Tick readLastActivate(); 150 /** Reads the last tick that this thread was suspended on. */ 151 virtual Tick readLastSuspend(); 152 153 /** Clears the function profiling information. */ 154 virtual void profileClear(); 155 /** Samples the function profiling information. */ 156 virtual void profileSample(); 157#endif 158 /** Returns this thread's ID number. */ 159 virtual int getThreadNum() { return thread->readTid(); } 160 161 /** Returns the instruction this thread is currently committing. 162 * Only used when an instruction faults. 163 */ 164 virtual TheISA::MachInst getInst(); 165 166 /** Copies the architectural registers from another TC into this TC. */ 167 virtual void copyArchRegs(ThreadContext *tc); 168 169 /** Resets all architectural registers to 0. */ 170 virtual void clearArchRegs(); 171 172 /** Reads an integer register. */ 173 virtual uint64_t readIntReg(int reg_idx); 174 175 virtual FloatReg readFloatReg(int reg_idx, int width); 176 177 virtual FloatReg readFloatReg(int reg_idx); 178 179 virtual FloatRegBits readFloatRegBits(int reg_idx, int width); 180 181 virtual FloatRegBits readFloatRegBits(int reg_idx); 182 183 /** Sets an integer register to a value. */ 184 virtual void setIntReg(int reg_idx, uint64_t val); 185 186 virtual void setFloatReg(int reg_idx, FloatReg val, int width); 187 188 virtual void setFloatReg(int reg_idx, FloatReg val); 189 190 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 191 192 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 193 194 /** Reads this thread's PC. */ 195 virtual uint64_t readPC() 196 { return cpu->readPC(thread->readTid()); } 197 198 /** Sets this thread's PC. */ 199 virtual void setPC(uint64_t val); 200 201 /** Reads this thread's next PC. */ 202 virtual uint64_t readNextPC() 203 { return cpu->readNextPC(thread->readTid()); } 204 205 /** Sets this thread's next PC. */ 206 virtual void setNextPC(uint64_t val); 207 208 /** Reads a miscellaneous register. */ 209 virtual MiscReg readMiscReg(int misc_reg) 210 { return cpu->readMiscReg(misc_reg, thread->readTid()); } 211 212 /** Reads a misc. register, including any side-effects the 213 * read might have as defined by the architecture. */ 214 virtual MiscReg readMiscRegWithEffect(int misc_reg) 215 { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); } 216 217 /** Sets a misc. register. */ 218 virtual void setMiscReg(int misc_reg, const MiscReg &val); 219 220 /** Sets a misc. register, including any side-effects the 221 * write might have as defined by the architecture. */ 222 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val); 223 224 /** Returns the number of consecutive store conditional failures. */ 225 // @todo: Figure out where these store cond failures should go. 226 virtual unsigned readStCondFailures() 227 { return thread->storeCondFailures; } 228 229 /** Sets the number of consecutive store conditional failures. */ 230 virtual void setStCondFailures(unsigned sc_failures) 231 { thread->storeCondFailures = sc_failures; } 232 233 // Only really makes sense for old CPU model. Lots of code 234 // outside the CPU still checks this function, so it will 235 // always return false to keep everything working. 236 /** Checks if the thread is misspeculating. Because it is 237 * very difficult to determine if the thread is 238 * misspeculating, this is set as false. */ 239 virtual bool misspeculating() { return false; } 240 241#if !FULL_SYSTEM 242 /** Gets a syscall argument by index. */ 243 virtual IntReg getSyscallArg(int i); 244 245 /** Sets a syscall argument. */ 246 virtual void setSyscallArg(int i, IntReg val); 247 248 /** Sets the syscall return value. */ 249 virtual void setSyscallReturn(SyscallReturn return_value); 250 251 /** Executes a syscall in SE mode. */ 252 virtual void syscall(int64_t callnum) 253 { return cpu->syscall(callnum, thread->readTid()); } 254 255 /** Reads the funcExeInst counter. */ 256 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 257#endif 258}; 259 260#endif 261