thread_context.hh revision 2935
1360SN/A/* 21458SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 3360SN/A * All rights reserved. 4360SN/A * 5360SN/A * Redistribution and use in source and binary forms, with or without 6360SN/A * modification, are permitted provided that the following conditions are 7360SN/A * met: redistributions of source code must retain the above copyright 8360SN/A * notice, this list of conditions and the following disclaimer; 9360SN/A * redistributions in binary form must reproduce the above copyright 10360SN/A * notice, this list of conditions and the following disclaimer in the 11360SN/A * documentation and/or other materials provided with the distribution; 12360SN/A * neither the name of the copyright holders nor the names of its 13360SN/A * contributors may be used to endorse or promote products derived from 14360SN/A * this software without specific prior written permission. 15360SN/A * 16360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22360SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23360SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26360SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu */ 30360SN/A 31360SN/A#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 322093SN/A#define __CPU_O3_THREAD_CONTEXT_HH__ 33360SN/A 34360SN/A#include "cpu/thread_context.hh" 35360SN/A#include "cpu/o3/isa_specific.hh" 36360SN/A 37360SN/Aclass EndQuiesceEvent; 38360SN/Anamespace Kernel { 392474SN/A class Statistics; 40360SN/A}; 412680Sktlim@umich.edu 421717SN/Aclass TranslatingPort; 432474SN/A 44360SN/A/** 456029Ssteve.reinhardt@amd.com * Derived ThreadContext class for use with the O3CPU. It 46360SN/A * provides the interface for any external objects to access a 472667Sstever@eecs.umich.edu * single thread's state and some general CPU state. Any time 48360SN/A * external objects try to update state through this interface, 49360SN/A * the CPU will create an event to squash all in-flight 502107SN/A * instructions in order to ensure state is maintained correctly. 51360SN/A * It must be defined specifically for the O3CPU because 52360SN/A * not all architectural state is located within the O3ThreadState 533114Sgblack@eecs.umich.edu * (such as the commit PC, and registers), and specific actions 54360SN/A * must be taken when using this interface (such as squashing all 552495SN/A * in-flight instructions when doing a write to this interface). 562680Sktlim@umich.edu */ 575958Sgblack@eecs.umich.edutemplate <class Impl> 585958Sgblack@eecs.umich.educlass O3ThreadContext : public ThreadContext 59360SN/A{ 602680Sktlim@umich.edu public: 61360SN/A typedef typename Impl::O3CPU O3CPU; 622495SN/A 632680Sktlim@umich.edu /** Pointer to the CPU. */ 64360SN/A O3CPU *cpu; 651450SN/A 665958Sgblack@eecs.umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 67360SN/A O3ThreadState<Impl> *thread; 68360SN/A 69360SN/A /** Returns a pointer to this CPU. */ 701450SN/A virtual BaseCPU *getCpuPtr() { return cpu; } 713114Sgblack@eecs.umich.edu 722680Sktlim@umich.edu /** Sets this CPU's ID. */ 73360SN/A virtual void setCpuId(int id) { cpu->setCpuId(id); } 741969SN/A 752484SN/A /** Reads this CPU's ID. */ 762484SN/A virtual int readCpuId() { return cpu->readCpuId(); } 77360SN/A 78360SN/A#if FULL_SYSTEM 79360SN/A /** Returns a pointer to the system. */ 801450SN/A virtual System *getSystemPtr() { return cpu->system; } 813114Sgblack@eecs.umich.edu 822680Sktlim@umich.edu /** Returns a pointer to physical memory. */ 83360SN/A virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } 841969SN/A 855958Sgblack@eecs.umich.edu /** Returns a pointer to this thread's kernel statistics. */ 86360SN/A virtual Kernel::Statistics *getKernelStats() 871458SN/A { return thread->kernelStats; } 88360SN/A 89360SN/A virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 90360SN/A 911450SN/A virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL); 923114Sgblack@eecs.umich.edu 932680Sktlim@umich.edu void delVirtPort(VirtualPort *vp); 94360SN/A#else 956029Ssteve.reinhardt@amd.com virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 966029Ssteve.reinhardt@amd.com 975958Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 986029Ssteve.reinhardt@amd.com virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 996029Ssteve.reinhardt@amd.com#endif 1006029Ssteve.reinhardt@amd.com /** Returns this thread's status. */ 1016029Ssteve.reinhardt@amd.com virtual Status status() const { return thread->status(); } 1022834Sksewell@umich.edu 103360SN/A /** Sets this thread's status. */ 1041458SN/A virtual void setStatus(Status new_status) 105360SN/A { thread->setStatus(new_status); } 106360SN/A 107360SN/A /** Set the status to Active. Optional delay indicates number of 1081450SN/A * cycles to wait before beginning execution. */ 1093114Sgblack@eecs.umich.edu virtual void activate(int delay = 1); 110360SN/A 1112107SN/A /** Set the status to Suspended. */ 112360SN/A virtual void suspend(); 113360SN/A 114360SN/A /** Set the status to Unallocated. */ 1151450SN/A virtual void deallocate(int delay = 0); 1165748SSteve.Reinhardt@amd.com 117360SN/A /** Set the status to Halted. */ 118360SN/A virtual void halt(); 1195958Sgblack@eecs.umich.edu 1205748SSteve.Reinhardt@amd.com#if FULL_SYSTEM 1215748SSteve.Reinhardt@amd.com /** Dumps the function profiling information. 1225748SSteve.Reinhardt@amd.com * @todo: Implement. 1235748SSteve.Reinhardt@amd.com */ 1245748SSteve.Reinhardt@amd.com virtual void dumpFuncProfile(); 1255748SSteve.Reinhardt@amd.com#endif 1265748SSteve.Reinhardt@amd.com /** Takes over execution of a thread from another CPU. */ 1275748SSteve.Reinhardt@amd.com virtual void takeOverFrom(ThreadContext *old_context); 1282474SN/A 1292474SN/A /** Registers statistics associated with this TC. */ 1305748SSteve.Reinhardt@amd.com virtual void regStats(const std::string &name); 1312474SN/A 1322474SN/A /** Serializes state. */ 1332474SN/A virtual void serialize(std::ostream &os); 1341450SN/A /** Unserializes state. */ 1355748SSteve.Reinhardt@amd.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 1365748SSteve.Reinhardt@amd.com 1371458SN/A#if FULL_SYSTEM 1381458SN/A /** Reads the last tick that this thread was activated on. */ 139360SN/A virtual Tick readLastActivate(); 140360SN/A /** Reads the last tick that this thread was suspended on. */ 141360SN/A virtual Tick readLastSuspend(); 1421450SN/A 1433114Sgblack@eecs.umich.edu /** Clears the function profiling information. */ 144360SN/A virtual void profileClear(); 1455958Sgblack@eecs.umich.edu /** Samples the function profiling information. */ 1461970SN/A virtual void profileSample(); 1471970SN/A#endif 1481970SN/A /** Returns this thread's ID number. */ 1491970SN/A virtual int getThreadNum() { return thread->readTid(); } 150360SN/A 151360SN/A /** Returns the instruction this thread is currently committing. 152360SN/A * Only used when an instruction faults. 1531450SN/A */ 1543114Sgblack@eecs.umich.edu virtual TheISA::MachInst getInst(); 155360SN/A 1565958Sgblack@eecs.umich.edu /** Copies the architectural registers from another TC into this TC. */ 1575958Sgblack@eecs.umich.edu virtual void copyArchRegs(ThreadContext *tc); 1585958Sgblack@eecs.umich.edu 159360SN/A /** Resets all architectural registers to 0. */ 160360SN/A virtual void clearArchRegs(); 161360SN/A 162360SN/A /** Reads an integer register. */ 1632680Sktlim@umich.edu virtual uint64_t readIntReg(int reg_idx); 164360SN/A 1651458SN/A virtual FloatReg readFloatReg(int reg_idx, int width); 166360SN/A 167360SN/A virtual FloatReg readFloatReg(int reg_idx); 1681450SN/A 1693114Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx, int width); 170360SN/A 1715958Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx); 1725958Sgblack@eecs.umich.edu 1735958Sgblack@eecs.umich.edu /** Sets an integer register to a value. */ 174360SN/A virtual void setIntReg(int reg_idx, uint64_t val); 1752680Sktlim@umich.edu 176360SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width); 177360SN/A 178360SN/A virtual void setFloatReg(int reg_idx, FloatReg val); 179360SN/A 180360SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 1811458SN/A 182360SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 183360SN/A 184360SN/A /** Reads this thread's PC. */ 1851450SN/A virtual uint64_t readPC() 1863114Sgblack@eecs.umich.edu { return cpu->readPC(thread->readTid()); } 187360SN/A 1885958Sgblack@eecs.umich.edu /** Sets this thread's PC. */ 1895958Sgblack@eecs.umich.edu virtual void setPC(uint64_t val); 1905958Sgblack@eecs.umich.edu 191360SN/A /** Reads this thread's next PC. */ 192360SN/A virtual uint64_t readNextPC() 193360SN/A { return cpu->readNextPC(thread->readTid()); } 1941458SN/A 195360SN/A /** Sets this thread's next PC. */ 196360SN/A virtual void setNextPC(uint64_t val); 197360SN/A 1981450SN/A /** Reads a miscellaneous register. */ 1994118Sgblack@eecs.umich.edu virtual MiscReg readMiscReg(int misc_reg) 2004118Sgblack@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->readTid()); } 2015958Sgblack@eecs.umich.edu 2025958Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the 2035958Sgblack@eecs.umich.edu * read might have as defined by the architecture. */ 2045958Sgblack@eecs.umich.edu virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 2055958Sgblack@eecs.umich.edu { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); } 2064118Sgblack@eecs.umich.edu 2074118Sgblack@eecs.umich.edu /** Sets a misc. register. */ 2084118Sgblack@eecs.umich.edu virtual Fault setMiscReg(int misc_reg, const MiscReg &val); 2094118Sgblack@eecs.umich.edu 2104118Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the 2114118Sgblack@eecs.umich.edu * write might have as defined by the architecture. */ 2124118Sgblack@eecs.umich.edu virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); 2134118Sgblack@eecs.umich.edu 2144118Sgblack@eecs.umich.edu /** Returns the number of consecutive store conditional failures. */ 2154118Sgblack@eecs.umich.edu // @todo: Figure out where these store cond failures should go. 2164118Sgblack@eecs.umich.edu virtual unsigned readStCondFailures() 2174118Sgblack@eecs.umich.edu { return thread->storeCondFailures; } 2184118Sgblack@eecs.umich.edu 2194118Sgblack@eecs.umich.edu /** Sets the number of consecutive store conditional failures. */ 2204118Sgblack@eecs.umich.edu virtual void setStCondFailures(unsigned sc_failures) 2214118Sgblack@eecs.umich.edu { thread->storeCondFailures = sc_failures; } 2224118Sgblack@eecs.umich.edu 2234118Sgblack@eecs.umich.edu // Only really makes sense for old CPU model. Lots of code 2244118Sgblack@eecs.umich.edu // outside the CPU still checks this function, so it will 2254118Sgblack@eecs.umich.edu // always return false to keep everything working. 2264118Sgblack@eecs.umich.edu /** Checks if the thread is misspeculating. Because it is 2274118Sgblack@eecs.umich.edu * very difficult to determine if the thread is 2284118Sgblack@eecs.umich.edu * misspeculating, this is set as false. */ 2294118Sgblack@eecs.umich.edu virtual bool misspeculating() { return false; } 2304118Sgblack@eecs.umich.edu 2314118Sgblack@eecs.umich.edu#if !FULL_SYSTEM 2323114Sgblack@eecs.umich.edu /** Gets a syscall argument by index. */ 233360SN/A virtual IntReg getSyscallArg(int i); 234360SN/A 2351458SN/A /** Sets a syscall argument. */ 236360SN/A virtual void setSyscallArg(int i, IntReg val); 237360SN/A 238360SN/A /** Sets the syscall return value. */ 239360SN/A virtual void setSyscallReturn(SyscallReturn return_value); 240360SN/A 2411450SN/A /** Executes a syscall in SE mode. */ 2423114Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) 243360SN/A { return cpu->syscall(callnum, thread->readTid()); } 2445958Sgblack@eecs.umich.edu 2455958Sgblack@eecs.umich.edu /** Reads the funcExeInst counter. */ 246360SN/A virtual Counter readFuncExeInst() { return thread->funcExeInst; } 247360SN/A#endif 248360SN/A}; 2492680Sktlim@umich.edu 250360SN/A#endif 2511458SN/A