thread_context.hh revision 13693
12817Sksewell@umich.edu/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 442817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 452817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 462817Sksewell@umich.edu 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 492935Sksewell@umich.edu#include "cpu/thread_context.hh" 502817Sksewell@umich.edu 512834Sksewell@umich.educlass EndQuiesceEvent; 522834Sksewell@umich.edunamespace Kernel { 532834Sksewell@umich.edu class Statistics; 548902Sandreas.hansson@arm.com} 552834Sksewell@umich.edu 562817Sksewell@umich.edu/** 572817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 582817Sksewell@umich.edu * provides the interface for any external objects to access a 592817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 602817Sksewell@umich.edu * external objects try to update state through this interface, 612817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 622817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 632817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 642817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 652817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 662817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 672817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 682817Sksewell@umich.edu */ 692817Sksewell@umich.edutemplate <class Impl> 702817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 712817Sksewell@umich.edu{ 722817Sksewell@umich.edu public: 732817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 742817Sksewell@umich.edu 752817Sksewell@umich.edu /** Pointer to the CPU. */ 762817Sksewell@umich.edu O3CPU *cpu; 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 792817Sksewell@umich.edu O3ThreadState<Impl> *thread; 802817Sksewell@umich.edu 813784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 8213628SAndrea.Mondelli@ucf.edu BaseTLB *getITBPtr() override { return cpu->itb; } 833784Sgblack@eecs.umich.edu 843784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 8513628SAndrea.Mondelli@ucf.edu BaseTLB *getDTBPtr() override { return cpu->dtb; } 863784Sgblack@eecs.umich.edu 8713628SAndrea.Mondelli@ucf.edu CheckerCPU *getCheckerCpuPtr() override { return NULL; } 888733Sgeoffrey.blake@arm.com 8913693Sgiacomo.gabrielli@arm.com TheISA::ISA * 9013693Sgiacomo.gabrielli@arm.com getIsaPtr() override 9113693Sgiacomo.gabrielli@arm.com { 9213693Sgiacomo.gabrielli@arm.com return cpu->isa[thread->threadId()]; 9313693Sgiacomo.gabrielli@arm.com } 9413693Sgiacomo.gabrielli@arm.com 959023Sgblack@eecs.umich.edu TheISA::Decoder * 9613628SAndrea.Mondelli@ucf.edu getDecoderPtr() override 979023Sgblack@eecs.umich.edu { 989023Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 999023Sgblack@eecs.umich.edu } 1008541Sgblack@eecs.umich.edu 1012817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 10213628SAndrea.Mondelli@ucf.edu virtual BaseCPU *getCpuPtr() override { return cpu; } 1032817Sksewell@umich.edu 1042817Sksewell@umich.edu /** Reads this CPU's ID. */ 10513628SAndrea.Mondelli@ucf.edu virtual int cpuId() const override { return cpu->cpuId(); } 1062817Sksewell@umich.edu 10710190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 10813628SAndrea.Mondelli@ucf.edu virtual uint32_t socketId() const override { return cpu->socketId(); } 10910190Sakash.bagdia@arm.com 11013628SAndrea.Mondelli@ucf.edu virtual ContextID 11113628SAndrea.Mondelli@ucf.edu contextId() const override { return thread->contextId(); } 1125714Shsul@eecs.umich.edu 11313628SAndrea.Mondelli@ucf.edu virtual void setContextId(int id) override { thread->setContextId(id); } 1145714Shsul@eecs.umich.edu 1155715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 11613628SAndrea.Mondelli@ucf.edu virtual int threadId() const override 11713628SAndrea.Mondelli@ucf.edu { return thread->threadId(); } 11813628SAndrea.Mondelli@ucf.edu virtual void setThreadId(int id) override 11913628SAndrea.Mondelli@ucf.edu { return thread->setThreadId(id); } 1205715Shsul@eecs.umich.edu 1212817Sksewell@umich.edu /** Returns a pointer to the system. */ 12213628SAndrea.Mondelli@ucf.edu virtual System *getSystemPtr() override { return cpu->system; } 1232817Sksewell@umich.edu 1242817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 12513628SAndrea.Mondelli@ucf.edu virtual TheISA::Kernel::Statistics *getKernelStats() override 1262817Sksewell@umich.edu { return thread->kernelStats; } 1272817Sksewell@umich.edu 1288541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 12913628SAndrea.Mondelli@ucf.edu virtual Process *getProcessPtr() override 13013628SAndrea.Mondelli@ucf.edu { return thread->getProcessPtr(); } 1318754Sgblack@eecs.umich.edu 13213628SAndrea.Mondelli@ucf.edu virtual void setProcessPtr(Process *p) override 13313628SAndrea.Mondelli@ucf.edu { thread->setProcessPtr(p); } 13411886Sbrandon.potter@amd.com 13513628SAndrea.Mondelli@ucf.edu virtual PortProxy &getPhysProxy() override 13613628SAndrea.Mondelli@ucf.edu { return thread->getPhysProxy(); } 1372817Sksewell@umich.edu 13813628SAndrea.Mondelli@ucf.edu virtual FSTranslatingPortProxy &getVirtProxy() override; 1393675Sktlim@umich.edu 14013628SAndrea.Mondelli@ucf.edu virtual void initMemProxies(ThreadContext *tc) override 1418706Sandreas.hansson@arm.com { thread->initMemProxies(tc); } 1428799Sgblack@eecs.umich.edu 14313628SAndrea.Mondelli@ucf.edu virtual SETranslatingPortProxy &getMemProxy() override 1448706Sandreas.hansson@arm.com { return thread->getMemProxy(); } 1452817Sksewell@umich.edu 1462817Sksewell@umich.edu /** Returns this thread's status. */ 14713628SAndrea.Mondelli@ucf.edu virtual Status status() const override { return thread->status(); } 1482817Sksewell@umich.edu 1492817Sksewell@umich.edu /** Sets this thread's status. */ 15013628SAndrea.Mondelli@ucf.edu virtual void setStatus(Status new_status) override 1512817Sksewell@umich.edu { thread->setStatus(new_status); } 1522817Sksewell@umich.edu 15310407Smitch.hayenga@arm.com /** Set the status to Active. */ 15413628SAndrea.Mondelli@ucf.edu virtual void activate() override; 1552817Sksewell@umich.edu 1562817Sksewell@umich.edu /** Set the status to Suspended. */ 15713628SAndrea.Mondelli@ucf.edu virtual void suspend() override; 1582817Sksewell@umich.edu 1592817Sksewell@umich.edu /** Set the status to Halted. */ 16013628SAndrea.Mondelli@ucf.edu virtual void halt() override; 1612817Sksewell@umich.edu 1622817Sksewell@umich.edu /** Dumps the function profiling information. 1632817Sksewell@umich.edu * @todo: Implement. 1642817Sksewell@umich.edu */ 16513628SAndrea.Mondelli@ucf.edu virtual void dumpFuncProfile() override; 1668777Sgblack@eecs.umich.edu 1672817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 16813628SAndrea.Mondelli@ucf.edu virtual void takeOverFrom(ThreadContext *old_context) override; 1692817Sksewell@umich.edu 1702817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 17113628SAndrea.Mondelli@ucf.edu virtual void regStats(const std::string &name) override; 1722817Sksewell@umich.edu 1732817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 17413628SAndrea.Mondelli@ucf.edu virtual Tick readLastActivate() override; 1752817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 17613628SAndrea.Mondelli@ucf.edu virtual Tick readLastSuspend() override; 1772817Sksewell@umich.edu 1782817Sksewell@umich.edu /** Clears the function profiling information. */ 17913628SAndrea.Mondelli@ucf.edu virtual void profileClear() override; 1802817Sksewell@umich.edu /** Samples the function profiling information. */ 18113628SAndrea.Mondelli@ucf.edu virtual void profileSample() override; 1822817Sksewell@umich.edu 1832817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 18413628SAndrea.Mondelli@ucf.edu virtual void copyArchRegs(ThreadContext *tc) override; 1852817Sksewell@umich.edu 1862817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 18713628SAndrea.Mondelli@ucf.edu virtual void clearArchRegs() override; 1882817Sksewell@umich.edu 1892817Sksewell@umich.edu /** Reads an integer register. */ 19013557Sgabeblack@google.com virtual RegVal 19113557Sgabeblack@google.com readReg(int reg_idx) 19213557Sgabeblack@google.com { 19312106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 19412106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 19512106SRekai.GonzalezAlberquilla@arm.com } 19613557Sgabeblack@google.com virtual RegVal 19713628SAndrea.Mondelli@ucf.edu readIntReg(int reg_idx) override 19813557Sgabeblack@google.com { 19912106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 20012106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 2019426SAndreas.Sandberg@ARM.com } 2022817Sksewell@umich.edu 20313557Sgabeblack@google.com virtual RegVal 20413628SAndrea.Mondelli@ucf.edu readFloatReg(int reg_idx) override 20513557Sgabeblack@google.com { 20613611Sgabeblack@google.com return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 20713611Sgabeblack@google.com reg_idx)).index()); 2089426SAndreas.Sandberg@ARM.com } 2092817Sksewell@umich.edu 21013557Sgabeblack@google.com virtual const VecRegContainer & 21113628SAndrea.Mondelli@ucf.edu readVecReg(const RegId& id) const override 21213557Sgabeblack@google.com { 21312109SRekai.GonzalezAlberquilla@arm.com return readVecRegFlat(flattenRegId(id).index()); 21412109SRekai.GonzalezAlberquilla@arm.com } 21512109SRekai.GonzalezAlberquilla@arm.com 21612109SRekai.GonzalezAlberquilla@arm.com /** 21712109SRekai.GonzalezAlberquilla@arm.com * Read vector register operand for modification, hierarchical indexing. 21812109SRekai.GonzalezAlberquilla@arm.com */ 21913557Sgabeblack@google.com virtual VecRegContainer & 22013628SAndrea.Mondelli@ucf.edu getWritableVecReg(const RegId& id) override 22113557Sgabeblack@google.com { 22212109SRekai.GonzalezAlberquilla@arm.com return getWritableVecRegFlat(flattenRegId(id).index()); 22312109SRekai.GonzalezAlberquilla@arm.com } 22412109SRekai.GonzalezAlberquilla@arm.com 22512109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22612109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 22812109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 22913628SAndrea.Mondelli@ucf.edu readVec8BitLaneReg(const RegId& id) const override 23012109SRekai.GonzalezAlberquilla@arm.com { 23112109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 23212109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 23312109SRekai.GonzalezAlberquilla@arm.com } 23412109SRekai.GonzalezAlberquilla@arm.com 23512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 23612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 23713628SAndrea.Mondelli@ucf.edu readVec16BitLaneReg(const RegId& id) const override 23812109SRekai.GonzalezAlberquilla@arm.com { 23912109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 24012109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 24112109SRekai.GonzalezAlberquilla@arm.com } 24212109SRekai.GonzalezAlberquilla@arm.com 24312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 24412109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 24513628SAndrea.Mondelli@ucf.edu readVec32BitLaneReg(const RegId& id) const override 24612109SRekai.GonzalezAlberquilla@arm.com { 24712109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 24812109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 24912109SRekai.GonzalezAlberquilla@arm.com } 25012109SRekai.GonzalezAlberquilla@arm.com 25112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 25212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 25313628SAndrea.Mondelli@ucf.edu readVec64BitLaneReg(const RegId& id) const override 25412109SRekai.GonzalezAlberquilla@arm.com { 25512109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 25612109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 25712109SRekai.GonzalezAlberquilla@arm.com } 25812109SRekai.GonzalezAlberquilla@arm.com 25912109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 26012109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26113628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::Byte>& val) override 26212109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 26312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26413628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::TwoByte>& val) override 26512109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 26612109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26713628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::FourByte>& val) override 26812109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 26912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 27013628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::EightByte>& val) override 27112109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 27212109SRekai.GonzalezAlberquilla@arm.com /** @} */ 27312109SRekai.GonzalezAlberquilla@arm.com 27413628SAndrea.Mondelli@ucf.edu virtual const VecElem& readVecElem(const RegId& reg) const override { 27512109SRekai.GonzalezAlberquilla@arm.com return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 27612109SRekai.GonzalezAlberquilla@arm.com } 27712109SRekai.GonzalezAlberquilla@arm.com 27813628SAndrea.Mondelli@ucf.edu virtual const VecPredRegContainer& 27913628SAndrea.Mondelli@ucf.edu readVecPredReg(const RegId& id) const override { 28013610Sgiacomo.gabrielli@arm.com return readVecPredRegFlat(flattenRegId(id).index()); 28113610Sgiacomo.gabrielli@arm.com } 28213610Sgiacomo.gabrielli@arm.com 28313628SAndrea.Mondelli@ucf.edu virtual VecPredRegContainer& 28413628SAndrea.Mondelli@ucf.edu getWritableVecPredReg(const RegId& id) override { 28513610Sgiacomo.gabrielli@arm.com return getWritableVecPredRegFlat(flattenRegId(id).index()); 28613610Sgiacomo.gabrielli@arm.com } 28713610Sgiacomo.gabrielli@arm.com 28813622Sgabeblack@google.com virtual RegVal 28913628SAndrea.Mondelli@ucf.edu readCCReg(int reg_idx) override 29013622Sgabeblack@google.com { 29112106SRekai.GonzalezAlberquilla@arm.com return readCCRegFlat(flattenRegId(RegId(CCRegClass, 29212106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 2939920Syasuko.eckert@amd.com } 2949920Syasuko.eckert@amd.com 2952817Sksewell@umich.edu /** Sets an integer register to a value. */ 29613557Sgabeblack@google.com virtual void 29713628SAndrea.Mondelli@ucf.edu setIntReg(int reg_idx, RegVal val) override 29813557Sgabeblack@google.com { 29912106SRekai.GonzalezAlberquilla@arm.com setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 3009426SAndreas.Sandberg@ARM.com } 3012817Sksewell@umich.edu 30213557Sgabeblack@google.com virtual void 30313628SAndrea.Mondelli@ucf.edu setFloatReg(int reg_idx, RegVal val) override 30413557Sgabeblack@google.com { 30513611Sgabeblack@google.com setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 30613611Sgabeblack@google.com reg_idx)).index(), val); 3079426SAndreas.Sandberg@ARM.com } 3082817Sksewell@umich.edu 30913557Sgabeblack@google.com virtual void 31013628SAndrea.Mondelli@ucf.edu setVecReg(const RegId& reg, const VecRegContainer& val) override 31113557Sgabeblack@google.com { 31212109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flattenRegId(reg).index(), val); 31312109SRekai.GonzalezAlberquilla@arm.com } 31412109SRekai.GonzalezAlberquilla@arm.com 31513557Sgabeblack@google.com virtual void 31613628SAndrea.Mondelli@ucf.edu setVecElem(const RegId& reg, const VecElem& val) override 31713557Sgabeblack@google.com { 31812109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 31912109SRekai.GonzalezAlberquilla@arm.com } 32012109SRekai.GonzalezAlberquilla@arm.com 32113557Sgabeblack@google.com virtual void 32213610Sgiacomo.gabrielli@arm.com setVecPredReg(const RegId& reg, 32313628SAndrea.Mondelli@ucf.edu const VecPredRegContainer& val) override 32413610Sgiacomo.gabrielli@arm.com { 32513610Sgiacomo.gabrielli@arm.com setVecPredRegFlat(flattenRegId(reg).index(), val); 32613610Sgiacomo.gabrielli@arm.com } 32713610Sgiacomo.gabrielli@arm.com 32813610Sgiacomo.gabrielli@arm.com virtual void 32913628SAndrea.Mondelli@ucf.edu setCCReg(int reg_idx, RegVal val) override 33013557Sgabeblack@google.com { 33112106SRekai.GonzalezAlberquilla@arm.com setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 3329920Syasuko.eckert@amd.com } 3339920Syasuko.eckert@amd.com 3347720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 33513628SAndrea.Mondelli@ucf.edu virtual TheISA::PCState pcState() override 3367720Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 3377720Sgblack@eecs.umich.edu 3387720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 33913628SAndrea.Mondelli@ucf.edu virtual void pcState(const TheISA::PCState &val) override; 3407720Sgblack@eecs.umich.edu 34113628SAndrea.Mondelli@ucf.edu virtual void pcStateNoRecord(const TheISA::PCState &val) override; 3428733Sgeoffrey.blake@arm.com 3432817Sksewell@umich.edu /** Reads this thread's PC. */ 34413628SAndrea.Mondelli@ucf.edu virtual Addr instAddr() override 3457720Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 3462817Sksewell@umich.edu 3472817Sksewell@umich.edu /** Reads this thread's next PC. */ 34813628SAndrea.Mondelli@ucf.edu virtual Addr nextInstAddr() override 3497720Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 3502817Sksewell@umich.edu 3517720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 35213628SAndrea.Mondelli@ucf.edu virtual MicroPC microPC() override 3537720Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 3545259Sksewell@umich.edu 3552817Sksewell@umich.edu /** Reads a miscellaneous register. */ 35613628SAndrea.Mondelli@ucf.edu virtual RegVal readMiscRegNoEffect(int misc_reg) const override 3575715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 3584172Ssaidi@eecs.umich.edu 3594172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 3604172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 36113628SAndrea.Mondelli@ucf.edu virtual RegVal readMiscReg(int misc_reg) override 3625715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 3632817Sksewell@umich.edu 3642817Sksewell@umich.edu /** Sets a misc. register. */ 36513628SAndrea.Mondelli@ucf.edu virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override; 3662817Sksewell@umich.edu 3672817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 3682817Sksewell@umich.edu * write might have as defined by the architecture. */ 36913628SAndrea.Mondelli@ucf.edu virtual void setMiscReg(int misc_reg, RegVal val) override; 3702817Sksewell@umich.edu 37113628SAndrea.Mondelli@ucf.edu virtual RegId flattenRegId(const RegId& regId) const override; 3726313Sgblack@eecs.umich.edu 3732817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 3742817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 37513628SAndrea.Mondelli@ucf.edu virtual unsigned readStCondFailures() override 3762817Sksewell@umich.edu { return thread->storeCondFailures; } 3772817Sksewell@umich.edu 3782817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 37913628SAndrea.Mondelli@ucf.edu virtual void setStCondFailures(unsigned sc_failures) override 3802817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 3812817Sksewell@umich.edu 3822817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 38313628SAndrea.Mondelli@ucf.edu virtual void syscall(int64_t callnum, Fault *fault) override 38411877Sbrandon.potter@amd.com { return cpu->syscall(callnum, thread->threadId(), fault); } 3852817Sksewell@umich.edu 3862817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 38713628SAndrea.Mondelli@ucf.edu virtual Counter readFuncExeInst() override { return thread->funcExeInst; } 3888777Sgblack@eecs.umich.edu 3895595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 39013557Sgabeblack@google.com virtual EndQuiesceEvent * 39113628SAndrea.Mondelli@ucf.edu getQuiesceEvent() override 3925595Sgblack@eecs.umich.edu { 3935595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 3945595Sgblack@eecs.umich.edu } 3959382SAli.Saidi@ARM.com /** check if the cpu is currently in state update mode and squash if not. 3969382SAli.Saidi@ARM.com * This function will return true if a trap is pending or if a fault or 3979382SAli.Saidi@ARM.com * similar is currently writing to the thread context and doesn't want 3989382SAli.Saidi@ARM.com * reset all the state (see noSquashFromTC). 3999382SAli.Saidi@ARM.com */ 40013557Sgabeblack@google.com inline void 40113557Sgabeblack@google.com conditionalSquash() 4029382SAli.Saidi@ARM.com { 4039382SAli.Saidi@ARM.com if (!thread->trapPending && !thread->noSquashFromTC) 4049382SAli.Saidi@ARM.com cpu->squashFromTC(thread->threadId()); 4059382SAli.Saidi@ARM.com } 4065595Sgblack@eecs.umich.edu 40713628SAndrea.Mondelli@ucf.edu virtual RegVal readIntRegFlat(int idx) override; 40813628SAndrea.Mondelli@ucf.edu virtual void setIntRegFlat(int idx, RegVal val) override; 4099426SAndreas.Sandberg@ARM.com 41013628SAndrea.Mondelli@ucf.edu virtual RegVal readFloatRegFlat(int idx) override; 41113628SAndrea.Mondelli@ucf.edu virtual void setFloatRegFlat(int idx, RegVal val) override; 4129920Syasuko.eckert@amd.com 41313628SAndrea.Mondelli@ucf.edu virtual const VecRegContainer& readVecRegFlat(int idx) const override; 41412109SRekai.GonzalezAlberquilla@arm.com /** Read vector register operand for modification, flat indexing. */ 41513628SAndrea.Mondelli@ucf.edu virtual VecRegContainer& getWritableVecRegFlat(int idx) override; 41613628SAndrea.Mondelli@ucf.edu virtual void setVecRegFlat(int idx, const VecRegContainer& val) override; 41712109SRekai.GonzalezAlberquilla@arm.com 41812109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 41913557Sgabeblack@google.com VecLaneT<VecElem, true> 42013557Sgabeblack@google.com readVecLaneFlat(int idx, int lId) const 42112109SRekai.GonzalezAlberquilla@arm.com { 42212109SRekai.GonzalezAlberquilla@arm.com return cpu->template readArchVecLane<VecElem>(idx, lId, 42312109SRekai.GonzalezAlberquilla@arm.com thread->threadId()); 42412109SRekai.GonzalezAlberquilla@arm.com } 42512109SRekai.GonzalezAlberquilla@arm.com 42612109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 42712109SRekai.GonzalezAlberquilla@arm.com void setVecLaneFlat(int idx, int lId, const LD& val) 42812109SRekai.GonzalezAlberquilla@arm.com { 42912109SRekai.GonzalezAlberquilla@arm.com cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 43012109SRekai.GonzalezAlberquilla@arm.com } 43112109SRekai.GonzalezAlberquilla@arm.com 43213628SAndrea.Mondelli@ucf.edu virtual const VecElem& readVecElemFlat( 43313628SAndrea.Mondelli@ucf.edu const RegIndex& idx, 43413628SAndrea.Mondelli@ucf.edu const ElemIndex& elemIndex) const override; 43513628SAndrea.Mondelli@ucf.edu virtual void setVecElemFlat( 43613628SAndrea.Mondelli@ucf.edu const RegIndex& idx, 43713628SAndrea.Mondelli@ucf.edu const ElemIndex& elemIdx, const VecElem& val) override; 43812109SRekai.GonzalezAlberquilla@arm.com 43913610Sgiacomo.gabrielli@arm.com virtual const VecPredRegContainer& readVecPredRegFlat(int idx) 44013610Sgiacomo.gabrielli@arm.com const override; 44113610Sgiacomo.gabrielli@arm.com virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; 44213610Sgiacomo.gabrielli@arm.com virtual void setVecPredRegFlat(int idx, 44313610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) override; 44413610Sgiacomo.gabrielli@arm.com 44513628SAndrea.Mondelli@ucf.edu virtual RegVal readCCRegFlat(int idx) override; 44613628SAndrea.Mondelli@ucf.edu virtual void setCCRegFlat(int idx, RegVal val) override; 4472817Sksewell@umich.edu}; 4482817Sksewell@umich.edu 4492817Sksewell@umich.edu#endif 450