thread_context.hh revision 13610
14483Sgblack@eecs.umich.edu/* 24483Sgblack@eecs.umich.edu * Copyright (c) 2011-2012, 2016-2018 ARM Limited 34483Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 44483Sgblack@eecs.umich.edu * All rights reserved 54483Sgblack@eecs.umich.edu * 64483Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 74483Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 84483Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 94483Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 104483Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 114483Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 124483Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 134483Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 144483Sgblack@eecs.umich.edu * 154483Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 164483Sgblack@eecs.umich.edu * All rights reserved. 174483Sgblack@eecs.umich.edu * 184483Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 194483Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 204483Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 214483Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 224483Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 234483Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 244483Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 254483Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 264483Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 274483Sgblack@eecs.umich.edu * this software without specific prior written permission. 284483Sgblack@eecs.umich.edu * 294483Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304483Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314483Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324483Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334483Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344483Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354483Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364483Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374483Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384483Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394483Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404483Sgblack@eecs.umich.edu * 414483Sgblack@eecs.umich.edu * Authors: Kevin Lim 424483Sgblack@eecs.umich.edu */ 434483Sgblack@eecs.umich.edu 444483Sgblack@eecs.umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 454483Sgblack@eecs.umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 464483Sgblack@eecs.umich.edu 474483Sgblack@eecs.umich.edu#include "config/the_isa.hh" 484483Sgblack@eecs.umich.edu#include "cpu/o3/isa_specific.hh" 494483Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 504483Sgblack@eecs.umich.edu 514483Sgblack@eecs.umich.educlass EndQuiesceEvent; 524483Sgblack@eecs.umich.edunamespace Kernel { 534483Sgblack@eecs.umich.edu class Statistics; 544483Sgblack@eecs.umich.edu} 554483Sgblack@eecs.umich.edu 564483Sgblack@eecs.umich.edu/** 574483Sgblack@eecs.umich.edu * Derived ThreadContext class for use with the O3CPU. It 584483Sgblack@eecs.umich.edu * provides the interface for any external objects to access a 594483Sgblack@eecs.umich.edu * single thread's state and some general CPU state. Any time 604483Sgblack@eecs.umich.edu * external objects try to update state through this interface, 614483Sgblack@eecs.umich.edu * the CPU will create an event to squash all in-flight 624483Sgblack@eecs.umich.edu * instructions in order to ensure state is maintained correctly. 634483Sgblack@eecs.umich.edu * It must be defined specifically for the O3CPU because 644483Sgblack@eecs.umich.edu * not all architectural state is located within the O3ThreadState 654483Sgblack@eecs.umich.edu * (such as the commit PC, and registers), and specific actions 664483Sgblack@eecs.umich.edu * must be taken when using this interface (such as squashing all 674483Sgblack@eecs.umich.edu * in-flight instructions when doing a write to this interface). 684483Sgblack@eecs.umich.edu */ 694483Sgblack@eecs.umich.edutemplate <class Impl> 704483Sgblack@eecs.umich.educlass O3ThreadContext : public ThreadContext 714483Sgblack@eecs.umich.edu{ 724483Sgblack@eecs.umich.edu public: 734483Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 744483Sgblack@eecs.umich.edu 754483Sgblack@eecs.umich.edu /** Pointer to the CPU. */ 764483Sgblack@eecs.umich.edu O3CPU *cpu; 774483Sgblack@eecs.umich.edu 784483Sgblack@eecs.umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 794483Sgblack@eecs.umich.edu O3ThreadState<Impl> *thread; 804483Sgblack@eecs.umich.edu 814483Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 824483Sgblack@eecs.umich.edu BaseTLB *getITBPtr() { return cpu->itb; } 834483Sgblack@eecs.umich.edu 844483Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 854483Sgblack@eecs.umich.edu BaseTLB *getDTBPtr() { return cpu->dtb; } 864483Sgblack@eecs.umich.edu 874483Sgblack@eecs.umich.edu CheckerCPU *getCheckerCpuPtr() { return NULL; } 884483Sgblack@eecs.umich.edu 894483Sgblack@eecs.umich.edu TheISA::Decoder * 904483Sgblack@eecs.umich.edu getDecoderPtr() 914483Sgblack@eecs.umich.edu { 924483Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 934483Sgblack@eecs.umich.edu } 944483Sgblack@eecs.umich.edu 954483Sgblack@eecs.umich.edu /** Returns a pointer to this CPU. */ 964483Sgblack@eecs.umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 974483Sgblack@eecs.umich.edu 984483Sgblack@eecs.umich.edu /** Reads this CPU's ID. */ 994483Sgblack@eecs.umich.edu virtual int cpuId() const { return cpu->cpuId(); } 1004483Sgblack@eecs.umich.edu 1014483Sgblack@eecs.umich.edu /** Reads this CPU's Socket ID. */ 1024483Sgblack@eecs.umich.edu virtual uint32_t socketId() const { return cpu->socketId(); } 1034483Sgblack@eecs.umich.edu 1044483Sgblack@eecs.umich.edu virtual ContextID contextId() const { return thread->contextId(); } 1054483Sgblack@eecs.umich.edu 1064483Sgblack@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 1074483Sgblack@eecs.umich.edu 1084483Sgblack@eecs.umich.edu /** Returns this thread's ID number. */ 1094483Sgblack@eecs.umich.edu virtual int threadId() const { return thread->threadId(); } 1104483Sgblack@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 1114483Sgblack@eecs.umich.edu 1124483Sgblack@eecs.umich.edu /** Returns a pointer to the system. */ 1134483Sgblack@eecs.umich.edu virtual System *getSystemPtr() { return cpu->system; } 1144483Sgblack@eecs.umich.edu 1154483Sgblack@eecs.umich.edu /** Returns a pointer to this thread's kernel statistics. */ 1164483Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 1174483Sgblack@eecs.umich.edu { return thread->kernelStats; } 1184483Sgblack@eecs.umich.edu 1194483Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1204483Sgblack@eecs.umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1214483Sgblack@eecs.umich.edu 1224483Sgblack@eecs.umich.edu virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); } 1234483Sgblack@eecs.umich.edu 1244483Sgblack@eecs.umich.edu virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 1254483Sgblack@eecs.umich.edu 1264483Sgblack@eecs.umich.edu virtual FSTranslatingPortProxy &getVirtProxy(); 1274483Sgblack@eecs.umich.edu 1284483Sgblack@eecs.umich.edu virtual void initMemProxies(ThreadContext *tc) 1294483Sgblack@eecs.umich.edu { thread->initMemProxies(tc); } 1304483Sgblack@eecs.umich.edu 1314483Sgblack@eecs.umich.edu virtual SETranslatingPortProxy &getMemProxy() 1324483Sgblack@eecs.umich.edu { return thread->getMemProxy(); } 1334483Sgblack@eecs.umich.edu 1344483Sgblack@eecs.umich.edu /** Returns this thread's status. */ 1354483Sgblack@eecs.umich.edu virtual Status status() const { return thread->status(); } 1364483Sgblack@eecs.umich.edu 1374483Sgblack@eecs.umich.edu /** Sets this thread's status. */ 1384483Sgblack@eecs.umich.edu virtual void setStatus(Status new_status) 1394483Sgblack@eecs.umich.edu { thread->setStatus(new_status); } 1404483Sgblack@eecs.umich.edu 1414483Sgblack@eecs.umich.edu /** Set the status to Active. */ 1424483Sgblack@eecs.umich.edu virtual void activate(); 1434483Sgblack@eecs.umich.edu 1444483Sgblack@eecs.umich.edu /** Set the status to Suspended. */ 1454483Sgblack@eecs.umich.edu virtual void suspend(); 1464483Sgblack@eecs.umich.edu 1474483Sgblack@eecs.umich.edu /** Set the status to Halted. */ 1484483Sgblack@eecs.umich.edu virtual void halt(); 1494483Sgblack@eecs.umich.edu 1504483Sgblack@eecs.umich.edu /** Dumps the function profiling information. 1514483Sgblack@eecs.umich.edu * @todo: Implement. 1524483Sgblack@eecs.umich.edu */ 1534483Sgblack@eecs.umich.edu virtual void dumpFuncProfile(); 1544483Sgblack@eecs.umich.edu 1554483Sgblack@eecs.umich.edu /** Takes over execution of a thread from another CPU. */ 1564483Sgblack@eecs.umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1574483Sgblack@eecs.umich.edu 1584483Sgblack@eecs.umich.edu /** Registers statistics associated with this TC. */ 1594483Sgblack@eecs.umich.edu virtual void regStats(const std::string &name); 1604483Sgblack@eecs.umich.edu 1614483Sgblack@eecs.umich.edu /** Reads the last tick that this thread was activated on. */ 1624483Sgblack@eecs.umich.edu virtual Tick readLastActivate(); 1634483Sgblack@eecs.umich.edu /** Reads the last tick that this thread was suspended on. */ 1644483Sgblack@eecs.umich.edu virtual Tick readLastSuspend(); 1654483Sgblack@eecs.umich.edu 1664483Sgblack@eecs.umich.edu /** Clears the function profiling information. */ 1674483Sgblack@eecs.umich.edu virtual void profileClear(); 1684483Sgblack@eecs.umich.edu /** Samples the function profiling information. */ 1694483Sgblack@eecs.umich.edu virtual void profileSample(); 1704483Sgblack@eecs.umich.edu 1714483Sgblack@eecs.umich.edu /** Copies the architectural registers from another TC into this TC. */ 1724483Sgblack@eecs.umich.edu virtual void copyArchRegs(ThreadContext *tc); 1734483Sgblack@eecs.umich.edu 1744483Sgblack@eecs.umich.edu /** Resets all architectural registers to 0. */ 1754483Sgblack@eecs.umich.edu virtual void clearArchRegs(); 1764483Sgblack@eecs.umich.edu 1774483Sgblack@eecs.umich.edu /** Reads an integer register. */ 1784483Sgblack@eecs.umich.edu virtual RegVal 1794483Sgblack@eecs.umich.edu readReg(int reg_idx) 1804483Sgblack@eecs.umich.edu { 1814483Sgblack@eecs.umich.edu return readIntRegFlat(flattenRegId(RegId(IntRegClass, 1824483Sgblack@eecs.umich.edu reg_idx)).index()); 1834483Sgblack@eecs.umich.edu } 1844483Sgblack@eecs.umich.edu virtual RegVal 1854483Sgblack@eecs.umich.edu readIntReg(int reg_idx) 1864483Sgblack@eecs.umich.edu { 1874483Sgblack@eecs.umich.edu return readIntRegFlat(flattenRegId(RegId(IntRegClass, 1884483Sgblack@eecs.umich.edu reg_idx)).index()); 1894483Sgblack@eecs.umich.edu } 1904483Sgblack@eecs.umich.edu 1914483Sgblack@eecs.umich.edu virtual RegVal 1924502Sgblack@eecs.umich.edu readFloatRegBits(int reg_idx) 1934502Sgblack@eecs.umich.edu { 1944502Sgblack@eecs.umich.edu return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, 1954502Sgblack@eecs.umich.edu reg_idx)).index()); 1964502Sgblack@eecs.umich.edu } 1974502Sgblack@eecs.umich.edu 1984502Sgblack@eecs.umich.edu virtual const VecRegContainer & 1994502Sgblack@eecs.umich.edu readVecReg(const RegId& id) const 2004483Sgblack@eecs.umich.edu { 2014483Sgblack@eecs.umich.edu return readVecRegFlat(flattenRegId(id).index()); 2024483Sgblack@eecs.umich.edu } 2034502Sgblack@eecs.umich.edu 2044483Sgblack@eecs.umich.edu /** 2054483Sgblack@eecs.umich.edu * Read vector register operand for modification, hierarchical indexing. 2064483Sgblack@eecs.umich.edu */ 2074483Sgblack@eecs.umich.edu virtual VecRegContainer & 2084483Sgblack@eecs.umich.edu getWritableVecReg(const RegId& id) 2094483Sgblack@eecs.umich.edu { 2104502Sgblack@eecs.umich.edu return getWritableVecRegFlat(flattenRegId(id).index()); 2114483Sgblack@eecs.umich.edu } 2124483Sgblack@eecs.umich.edu 2134483Sgblack@eecs.umich.edu /** Vector Register Lane Interfaces. */ 2144483Sgblack@eecs.umich.edu /** @{ */ 2154483Sgblack@eecs.umich.edu /** Reads source vector 8bit operand. */ 2164502Sgblack@eecs.umich.edu virtual ConstVecLane8 2174483Sgblack@eecs.umich.edu readVec8BitLaneReg(const RegId& id) const 2184483Sgblack@eecs.umich.edu { 2194483Sgblack@eecs.umich.edu return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 2204483Sgblack@eecs.umich.edu id.elemIndex()); 2214483Sgblack@eecs.umich.edu } 2224483Sgblack@eecs.umich.edu 2234502Sgblack@eecs.umich.edu /** Reads source vector 16bit operand. */ 2244483Sgblack@eecs.umich.edu virtual ConstVecLane16 2254483Sgblack@eecs.umich.edu readVec16BitLaneReg(const RegId& id) const 2264483Sgblack@eecs.umich.edu { 2274483Sgblack@eecs.umich.edu return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 2284483Sgblack@eecs.umich.edu id.elemIndex()); 2294502Sgblack@eecs.umich.edu } 2304483Sgblack@eecs.umich.edu 2314483Sgblack@eecs.umich.edu /** Reads source vector 32bit operand. */ 2324483Sgblack@eecs.umich.edu virtual ConstVecLane32 2334483Sgblack@eecs.umich.edu readVec32BitLaneReg(const RegId& id) const 2344483Sgblack@eecs.umich.edu { 2354502Sgblack@eecs.umich.edu return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 2364483Sgblack@eecs.umich.edu id.elemIndex()); 2374483Sgblack@eecs.umich.edu } 2384483Sgblack@eecs.umich.edu 2394483Sgblack@eecs.umich.edu /** Reads source vector 64bit operand. */ 2404483Sgblack@eecs.umich.edu virtual ConstVecLane64 2414502Sgblack@eecs.umich.edu readVec64BitLaneReg(const RegId& id) const 2424483Sgblack@eecs.umich.edu { 2434483Sgblack@eecs.umich.edu return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 2444483Sgblack@eecs.umich.edu id.elemIndex()); 2454483Sgblack@eecs.umich.edu } 2464502Sgblack@eecs.umich.edu 2474483Sgblack@eecs.umich.edu /** Write a lane of the destination vector register. */ 2484483Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2494483Sgblack@eecs.umich.edu const LaneData<LaneSize::Byte>& val) 2504483Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2514483Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2524483Sgblack@eecs.umich.edu const LaneData<LaneSize::TwoByte>& val) 2534502Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2544483Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2554483Sgblack@eecs.umich.edu const LaneData<LaneSize::FourByte>& val) 2564483Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2574483Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2584483Sgblack@eecs.umich.edu const LaneData<LaneSize::EightByte>& val) 2594502Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2604483Sgblack@eecs.umich.edu /** @} */ 2614483Sgblack@eecs.umich.edu 2624483Sgblack@eecs.umich.edu virtual const VecElem& readVecElem(const RegId& reg) const { 2634483Sgblack@eecs.umich.edu return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 2644483Sgblack@eecs.umich.edu } 2654483Sgblack@eecs.umich.edu 2664483Sgblack@eecs.umich.edu virtual const VecPredRegContainer& readVecPredReg(const RegId& id) const { 2674483Sgblack@eecs.umich.edu return readVecPredRegFlat(flattenRegId(id).index()); 2684483Sgblack@eecs.umich.edu } 2694483Sgblack@eecs.umich.edu 2704483Sgblack@eecs.umich.edu virtual VecPredRegContainer& getWritableVecPredReg(const RegId& id) { 2714483Sgblack@eecs.umich.edu return getWritableVecPredRegFlat(flattenRegId(id).index()); 2724483Sgblack@eecs.umich.edu } 2734483Sgblack@eecs.umich.edu 2744483Sgblack@eecs.umich.edu virtual CCReg readCCReg(int reg_idx) { 2754483Sgblack@eecs.umich.edu return readCCRegFlat(flattenRegId(RegId(CCRegClass, 2764483Sgblack@eecs.umich.edu reg_idx)).index()); 2774483Sgblack@eecs.umich.edu } 2784483Sgblack@eecs.umich.edu 2794483Sgblack@eecs.umich.edu /** Sets an integer register to a value. */ 2804483Sgblack@eecs.umich.edu virtual void 2814483Sgblack@eecs.umich.edu setIntReg(int reg_idx, RegVal val) 2824483Sgblack@eecs.umich.edu { 2834483Sgblack@eecs.umich.edu setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 2844483Sgblack@eecs.umich.edu } 2854483Sgblack@eecs.umich.edu 2864483Sgblack@eecs.umich.edu virtual void 2874483Sgblack@eecs.umich.edu setFloatRegBits(int reg_idx, RegVal val) 2884483Sgblack@eecs.umich.edu { 2894483Sgblack@eecs.umich.edu setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, 2904483Sgblack@eecs.umich.edu reg_idx)).index(), val); 2914483Sgblack@eecs.umich.edu } 2924483Sgblack@eecs.umich.edu 2934483Sgblack@eecs.umich.edu virtual void 2944483Sgblack@eecs.umich.edu setVecReg(const RegId& reg, const VecRegContainer& val) 2954483Sgblack@eecs.umich.edu { 2964483Sgblack@eecs.umich.edu setVecRegFlat(flattenRegId(reg).index(), val); 2974483Sgblack@eecs.umich.edu } 2984483Sgblack@eecs.umich.edu 2994483Sgblack@eecs.umich.edu virtual void 3004483Sgblack@eecs.umich.edu setVecElem(const RegId& reg, const VecElem& val) 3014483Sgblack@eecs.umich.edu { 3024483Sgblack@eecs.umich.edu setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 3034483Sgblack@eecs.umich.edu } 3044483Sgblack@eecs.umich.edu 3054483Sgblack@eecs.umich.edu virtual void 3064483Sgblack@eecs.umich.edu setVecPredReg(const RegId& reg, 3074483Sgblack@eecs.umich.edu const VecPredRegContainer& val) 3084483Sgblack@eecs.umich.edu { 3094483Sgblack@eecs.umich.edu setVecPredRegFlat(flattenRegId(reg).index(), val); 3104483Sgblack@eecs.umich.edu } 3114483Sgblack@eecs.umich.edu 3124483Sgblack@eecs.umich.edu virtual void 3134483Sgblack@eecs.umich.edu setCCReg(int reg_idx, CCReg val) 3144483Sgblack@eecs.umich.edu { 3154483Sgblack@eecs.umich.edu setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 3164483Sgblack@eecs.umich.edu } 3174483Sgblack@eecs.umich.edu 3184483Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 3194502Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() 3204483Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 3214483Sgblack@eecs.umich.edu 3224483Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 3234483Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val); 3244483Sgblack@eecs.umich.edu 3254483Sgblack@eecs.umich.edu virtual void pcStateNoRecord(const TheISA::PCState &val); 3264483Sgblack@eecs.umich.edu 3274483Sgblack@eecs.umich.edu /** Reads this thread's PC. */ 3284483Sgblack@eecs.umich.edu virtual Addr instAddr() 3294483Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 3304483Sgblack@eecs.umich.edu 3314483Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 3324502Sgblack@eecs.umich.edu virtual Addr nextInstAddr() 3334483Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 3344483Sgblack@eecs.umich.edu 3354483Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 3364483Sgblack@eecs.umich.edu virtual MicroPC microPC() 3374483Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 3384483Sgblack@eecs.umich.edu 3394483Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 3404483Sgblack@eecs.umich.edu virtual RegVal readMiscRegNoEffect(int misc_reg) const 3414483Sgblack@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 3424483Sgblack@eecs.umich.edu 3434483Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the 3444483Sgblack@eecs.umich.edu * read might have as defined by the architecture. */ 3454483Sgblack@eecs.umich.edu virtual RegVal readMiscReg(int misc_reg) 3464483Sgblack@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 3474483Sgblack@eecs.umich.edu 3484483Sgblack@eecs.umich.edu /** Sets a misc. register. */ 3494483Sgblack@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, RegVal val); 3504483Sgblack@eecs.umich.edu 3514483Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the 3524483Sgblack@eecs.umich.edu * write might have as defined by the architecture. */ 3534483Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, RegVal val); 3544483Sgblack@eecs.umich.edu 3554483Sgblack@eecs.umich.edu virtual RegId flattenRegId(const RegId& regId) const; 3564483Sgblack@eecs.umich.edu 3574483Sgblack@eecs.umich.edu /** Returns the number of consecutive store conditional failures. */ 3584483Sgblack@eecs.umich.edu // @todo: Figure out where these store cond failures should go. 3594483Sgblack@eecs.umich.edu virtual unsigned readStCondFailures() 3604483Sgblack@eecs.umich.edu { return thread->storeCondFailures; } 3614483Sgblack@eecs.umich.edu 3624483Sgblack@eecs.umich.edu /** Sets the number of consecutive store conditional failures. */ 3634483Sgblack@eecs.umich.edu virtual void setStCondFailures(unsigned sc_failures) 3644483Sgblack@eecs.umich.edu { thread->storeCondFailures = sc_failures; } 3654483Sgblack@eecs.umich.edu 3664483Sgblack@eecs.umich.edu /** Executes a syscall in SE mode. */ 3674483Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum, Fault *fault) 3684483Sgblack@eecs.umich.edu { return cpu->syscall(callnum, thread->threadId(), fault); } 3694483Sgblack@eecs.umich.edu 3704483Sgblack@eecs.umich.edu /** Reads the funcExeInst counter. */ 3714483Sgblack@eecs.umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 3724483Sgblack@eecs.umich.edu 3734483Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 3744483Sgblack@eecs.umich.edu virtual EndQuiesceEvent * 3754483Sgblack@eecs.umich.edu getQuiesceEvent() 3764483Sgblack@eecs.umich.edu { 3774483Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 3784483Sgblack@eecs.umich.edu } 3794483Sgblack@eecs.umich.edu /** check if the cpu is currently in state update mode and squash if not. 3804483Sgblack@eecs.umich.edu * This function will return true if a trap is pending or if a fault or 3814483Sgblack@eecs.umich.edu * similar is currently writing to the thread context and doesn't want 3824483Sgblack@eecs.umich.edu * reset all the state (see noSquashFromTC). 3834483Sgblack@eecs.umich.edu */ 3844483Sgblack@eecs.umich.edu inline void 3854483Sgblack@eecs.umich.edu conditionalSquash() 3864483Sgblack@eecs.umich.edu { 3874483Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->noSquashFromTC) 3884483Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3894483Sgblack@eecs.umich.edu } 3904483Sgblack@eecs.umich.edu 3914483Sgblack@eecs.umich.edu virtual RegVal readIntRegFlat(int idx); 3924483Sgblack@eecs.umich.edu virtual void setIntRegFlat(int idx, RegVal val); 3934483Sgblack@eecs.umich.edu 3944483Sgblack@eecs.umich.edu virtual RegVal readFloatRegBitsFlat(int idx); 3954483Sgblack@eecs.umich.edu virtual void setFloatRegBitsFlat(int idx, RegVal val); 3964483Sgblack@eecs.umich.edu 3974483Sgblack@eecs.umich.edu virtual const VecRegContainer& readVecRegFlat(int idx) const; 3984483Sgblack@eecs.umich.edu /** Read vector register operand for modification, flat indexing. */ 3994483Sgblack@eecs.umich.edu virtual VecRegContainer& getWritableVecRegFlat(int idx); 4004483Sgblack@eecs.umich.edu virtual void setVecRegFlat(int idx, const VecRegContainer& val); 4014483Sgblack@eecs.umich.edu 4024483Sgblack@eecs.umich.edu template <typename VecElem> 4034483Sgblack@eecs.umich.edu VecLaneT<VecElem, true> 4044483Sgblack@eecs.umich.edu readVecLaneFlat(int idx, int lId) const 4054483Sgblack@eecs.umich.edu { 4064483Sgblack@eecs.umich.edu return cpu->template readArchVecLane<VecElem>(idx, lId, 4074483Sgblack@eecs.umich.edu thread->threadId()); 4084483Sgblack@eecs.umich.edu } 4094483Sgblack@eecs.umich.edu 4104483Sgblack@eecs.umich.edu template <typename LD> 4114483Sgblack@eecs.umich.edu void setVecLaneFlat(int idx, int lId, const LD& val) 4124483Sgblack@eecs.umich.edu { 4134483Sgblack@eecs.umich.edu cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 4144483Sgblack@eecs.umich.edu } 4154483Sgblack@eecs.umich.edu 4164483Sgblack@eecs.umich.edu virtual const VecElem& readVecElemFlat(const RegIndex& idx, 4174483Sgblack@eecs.umich.edu const ElemIndex& elemIndex) const; 4184483Sgblack@eecs.umich.edu virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, 4194483Sgblack@eecs.umich.edu const VecElem& val); 4204483Sgblack@eecs.umich.edu 4214483Sgblack@eecs.umich.edu virtual const VecPredRegContainer& readVecPredRegFlat(int idx) 4224483Sgblack@eecs.umich.edu const override; 4234483Sgblack@eecs.umich.edu virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; 4244483Sgblack@eecs.umich.edu virtual void setVecPredRegFlat(int idx, 4254483Sgblack@eecs.umich.edu const VecPredRegContainer& val) override; 4264483Sgblack@eecs.umich.edu 4274483Sgblack@eecs.umich.edu virtual CCReg readCCRegFlat(int idx); 4284483Sgblack@eecs.umich.edu virtual void setCCRegFlat(int idx, CCReg val); 4294483Sgblack@eecs.umich.edu}; 4304483Sgblack@eecs.umich.edu 4314483Sgblack@eecs.umich.edu#endif 4324483Sgblack@eecs.umich.edu