store_set.hh revision 2107
11689SN/A/*
29444SAndreas.Sandberg@ARM.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
38707Sandreas.hansson@arm.com * All rights reserved.
48707Sandreas.hansson@arm.com *
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68707Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are
78707Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright
88707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer;
98707Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright
108707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the
118707Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution;
128707Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its
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141689SN/A * this software without specific prior written permission.
157897Shestness@cs.utexas.edu *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
271689SN/A */
281689SN/A
291689SN/A#ifndef __CPU_O3_CPU_STORE_SET_HH__
301689SN/A#define __CPU_O3_CPU_STORE_SET_HH__
311689SN/A
321689SN/A#include <vector>
331689SN/A
341689SN/A#include "arch/isa_traits.hh"
351689SN/A#include "cpu/inst_seq.hh"
361689SN/A
371689SN/Aclass StoreSet
381689SN/A{
391689SN/A  protected:
402665Ssaidi@eecs.umich.edu    typedef TheISA::Addr Addr;
412665Ssaidi@eecs.umich.edu  public:
422756Sksewell@umich.edu    typedef unsigned SSID;
437897Shestness@cs.utexas.edu
441689SN/A  public:
451689SN/A    StoreSet(int SSIT_size, int LFST_size);
462325SN/A
472325SN/A    void violation(Addr store_PC, Addr load_PC);
481060SN/A
491060SN/A    void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
501060SN/A
512292SN/A    void insertStore(Addr store_PC, InstSeqNum store_seq_num);
522292SN/A
531681SN/A    InstSeqNum checkInst(Addr PC);
541060SN/A
552980Sgblack@eecs.umich.edu    void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
561060SN/A
576658Snate@binkert.org    void squash(InstSeqNum squashed_num);
581717SN/A
591717SN/A    void clear();
602292SN/A
612292SN/A  private:
628229Snate@binkert.org    inline int calcIndex(Addr PC)
638229Snate@binkert.org    { return (PC >> offset_bits) & index_mask; }
648229Snate@binkert.org
658229Snate@binkert.org    inline SSID calcSSID(Addr PC)
662817Sksewell@umich.edu    { return ((PC ^ (PC >> 10)) % LFST_size); }
678229Snate@binkert.org
681060SN/A    SSID *SSIT;
691060SN/A
702316SN/A    std::vector<bool> validSSIT;
712316SN/A
722680Sktlim@umich.edu    InstSeqNum *LFST;
732817Sksewell@umich.edu
742817Sksewell@umich.edu    std::vector<bool> validLFST;
752843Sktlim@umich.edu
762843Sktlim@umich.edu    int *SSCounters;
772669Sktlim@umich.edu
781060SN/A    int SSIT_size;
791060SN/A
808737Skoansin.tan@gmail.com    int LFST_size;
815529Snate@binkert.org
822733Sktlim@umich.edu    int index_mask;
831060SN/A
841060SN/A    // HACK: Hardcoded for now.
851060SN/A    int offset_bits;
865529Snate@binkert.org};
872292SN/A
882292SN/A#endif // __CPU_O3_CPU_STORE_SET_HH__
891060SN/A