rob_impl.hh revision 9944
18706Sandreas.hansson@arm.com/* 28706Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38706Sandreas.hansson@arm.com * All rights reserved 48706Sandreas.hansson@arm.com * 58706Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68706Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78706Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88706Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98706Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108706Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118706Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128706Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 136892SBrad.Beckmann@amd.com * 146892SBrad.Beckmann@amd.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 156892SBrad.Beckmann@amd.com * All rights reserved. 166892SBrad.Beckmann@amd.com * 176892SBrad.Beckmann@amd.com * Redistribution and use in source and binary forms, with or without 186892SBrad.Beckmann@amd.com * modification, are permitted provided that the following conditions are 196892SBrad.Beckmann@amd.com * met: redistributions of source code must retain the above copyright 206892SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer; 216892SBrad.Beckmann@amd.com * redistributions in binary form must reproduce the above copyright 226892SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer in the 236892SBrad.Beckmann@amd.com * documentation and/or other materials provided with the distribution; 246892SBrad.Beckmann@amd.com * neither the name of the copyright holders nor the names of its 256892SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 266892SBrad.Beckmann@amd.com * this software without specific prior written permission. 276892SBrad.Beckmann@amd.com * 286892SBrad.Beckmann@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296892SBrad.Beckmann@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306892SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316892SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326892SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336892SBrad.Beckmann@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346892SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356892SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366892SBrad.Beckmann@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376892SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386892SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396892SBrad.Beckmann@amd.com * 406892SBrad.Beckmann@amd.com * Authors: Kevin Lim 416892SBrad.Beckmann@amd.com * Korey Sewell 427563SBrad.Beckmann@amd.com */ 436892SBrad.Beckmann@amd.com 446892SBrad.Beckmann@amd.com#ifndef __CPU_O3_ROB_IMPL_HH__ 456892SBrad.Beckmann@amd.com#define __CPU_O3_ROB_IMPL_HH__ 4610118Snilay@cs.wisc.edu 4710118Snilay@cs.wisc.edu#include <list> 4810524Snilay@cs.wisc.edu 4910118Snilay@cs.wisc.edu#include "cpu/o3/rob.hh" 506892SBrad.Beckmann@amd.com#include "debug/Fetch.hh" 517538SBrad.Beckmann@amd.com#include "debug/ROB.hh" 528939SBrad.Beckmann@amd.com 538939SBrad.Beckmann@amd.comusing namespace std; 548939SBrad.Beckmann@amd.com 559791Sakash.bagdia@arm.comtemplate <class Impl> 569791Sakash.bagdia@arm.comROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 579791Sakash.bagdia@arm.com std::string _smtROBPolicy, unsigned _smtROBThreshold, 589791Sakash.bagdia@arm.com ThreadID _numThreads) 5910525Snilay@cs.wisc.edu : cpu(_cpu), 6010525Snilay@cs.wisc.edu numEntries(_numEntries), 6110525Snilay@cs.wisc.edu squashWidth(_squashWidth), 629841Snilay@cs.wisc.edu numInstsInROB(0), 639841Snilay@cs.wisc.edu numThreads(_numThreads) 649841Snilay@cs.wisc.edu{ 659841Snilay@cs.wisc.edu std::string policy = _smtROBPolicy; 669841Snilay@cs.wisc.edu 677538SBrad.Beckmann@amd.com //Convert string to lowercase 687538SBrad.Beckmann@amd.com std::transform(policy.begin(), policy.end(), policy.begin(), 697538SBrad.Beckmann@amd.com (int(*)(int)) tolower); 707538SBrad.Beckmann@amd.com 717538SBrad.Beckmann@amd.com //Figure out rob policy 729576Snilay@cs.wisc.edu if (policy == "dynamic") { 739576Snilay@cs.wisc.edu robPolicy = Dynamic; 748612Stushar@csail.mit.edu 758612Stushar@csail.mit.edu //Set Max Entries to Total ROB Capacity 767538SBrad.Beckmann@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 777538SBrad.Beckmann@amd.com maxEntries[tid] = numEntries; 787917SBrad.Beckmann@amd.com } 797563SBrad.Beckmann@amd.com 807563SBrad.Beckmann@amd.com } else if (policy == "partitioned") { 817538SBrad.Beckmann@amd.com robPolicy = Partitioned; 827566SBrad.Beckmann@amd.com DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n"); 837566SBrad.Beckmann@amd.com 847809Snilay@cs.wisc.edu //@todo:make work if part_amt doesnt divide evenly. 857809Snilay@cs.wisc.edu int part_amt = numEntries / numThreads; 867809Snilay@cs.wisc.edu 877809Snilay@cs.wisc.edu //Divide ROB up evenly 887538SBrad.Beckmann@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 897538SBrad.Beckmann@amd.com maxEntries[tid] = part_amt; 907538SBrad.Beckmann@amd.com } 917538SBrad.Beckmann@amd.com 9210524Snilay@cs.wisc.edu } else if (policy == "threshold") { 9310524Snilay@cs.wisc.edu robPolicy = Threshold; 9410524Snilay@cs.wisc.edu DPRINTF(Fetch, "ROB sharing policy set to Threshold\n"); 9510524Snilay@cs.wisc.edu 9610524Snilay@cs.wisc.edu int threshold = _smtROBThreshold;; 9710524Snilay@cs.wisc.edu 9810524Snilay@cs.wisc.edu //Divide up by threshold amount 9910524Snilay@cs.wisc.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 10010524Snilay@cs.wisc.edu maxEntries[tid] = threshold; 10110524Snilay@cs.wisc.edu } 10210524Snilay@cs.wisc.edu } else { 10310524Snilay@cs.wisc.edu assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic," 10410524Snilay@cs.wisc.edu "Partitioned, Threshold}"); 10510524Snilay@cs.wisc.edu } 10610524Snilay@cs.wisc.edu 10710524Snilay@cs.wisc.edu resetState(); 10810524Snilay@cs.wisc.edu} 10910524Snilay@cs.wisc.edu 11010524Snilay@cs.wisc.edutemplate <class Impl> 11110524Snilay@cs.wisc.eduvoid 11210524Snilay@cs.wisc.eduROB<Impl>::resetState() 11310524Snilay@cs.wisc.edu{ 11410524Snilay@cs.wisc.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 11510524Snilay@cs.wisc.edu doneSquashing[tid] = true; 11610524Snilay@cs.wisc.edu threadEntries[tid] = 0; 11710524Snilay@cs.wisc.edu squashIt[tid] = instList[tid].end(); 11810524Snilay@cs.wisc.edu squashedSeqNum[tid] = 0; 11910524Snilay@cs.wisc.edu } 12010524Snilay@cs.wisc.edu numInstsInROB = 0; 12110524Snilay@cs.wisc.edu 12210524Snilay@cs.wisc.edu // Initialize the "universal" ROB head & tail point to invalid 12310524Snilay@cs.wisc.edu // pointers 12410524Snilay@cs.wisc.edu head = instList[0].end(); 12510524Snilay@cs.wisc.edu tail = instList[0].end(); 12610524Snilay@cs.wisc.edu} 12710524Snilay@cs.wisc.edu 12810524Snilay@cs.wisc.edutemplate <class Impl> 12910524Snilay@cs.wisc.edustd::string 13010524Snilay@cs.wisc.eduROB<Impl>::name() const 13110524Snilay@cs.wisc.edu{ 13210524Snilay@cs.wisc.edu return cpu->name() + ".rob"; 13310524Snilay@cs.wisc.edu} 13410524Snilay@cs.wisc.edu 13510524Snilay@cs.wisc.edutemplate <class Impl> 13610524Snilay@cs.wisc.eduvoid 13710524Snilay@cs.wisc.eduROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 13810524Snilay@cs.wisc.edu{ 13910524Snilay@cs.wisc.edu DPRINTF(ROB, "Setting active threads list pointer.\n"); 14010524Snilay@cs.wisc.edu activeThreads = at_ptr; 14110524Snilay@cs.wisc.edu} 14210524Snilay@cs.wisc.edu 1439100SBrad.Beckmann@amd.comtemplate <class Impl> 1449100SBrad.Beckmann@amd.comvoid 1459100SBrad.Beckmann@amd.comROB<Impl>::drainSanityCheck() const 1469100SBrad.Beckmann@amd.com{ 1479100SBrad.Beckmann@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) 1489100SBrad.Beckmann@amd.com assert(instList[tid].empty()); 1499100SBrad.Beckmann@amd.com assert(isEmpty()); 1509100SBrad.Beckmann@amd.com} 1519100SBrad.Beckmann@amd.com 1529100SBrad.Beckmann@amd.comtemplate <class Impl> 15310519Snilay@cs.wisc.eduvoid 1546892SBrad.Beckmann@amd.comROB<Impl>::takeOverFrom() 15510524Snilay@cs.wisc.edu{ 1568436SBrad.Beckmann@amd.com resetState(); 1578436SBrad.Beckmann@amd.com} 1588257SBrad.Beckmann@amd.com 1598257SBrad.Beckmann@amd.comtemplate <class Impl> 16010122Snilay@cs.wisc.eduvoid 16110122Snilay@cs.wisc.eduROB<Impl>::resetEntries() 16210122Snilay@cs.wisc.edu{ 16310122Snilay@cs.wisc.edu if (robPolicy != Dynamic || numThreads > 1) { 16410122Snilay@cs.wisc.edu int active_threads = activeThreads->size(); 16510122Snilay@cs.wisc.edu 1668257SBrad.Beckmann@amd.com list<ThreadID>::iterator threads = activeThreads->begin(); 16710122Snilay@cs.wisc.edu list<ThreadID>::iterator end = activeThreads->end(); 16810122Snilay@cs.wisc.edu 16910122Snilay@cs.wisc.edu while (threads != end) { 17010122Snilay@cs.wisc.edu ThreadID tid = *threads++; 17110122Snilay@cs.wisc.edu 17210122Snilay@cs.wisc.edu if (robPolicy == Partitioned) { 1738257SBrad.Beckmann@amd.com maxEntries[tid] = numEntries / active_threads; 17410122Snilay@cs.wisc.edu } else if (robPolicy == Threshold && active_threads == 1) { 17510122Snilay@cs.wisc.edu maxEntries[tid] = numEntries; 17610122Snilay@cs.wisc.edu } 17710122Snilay@cs.wisc.edu } 17810122Snilay@cs.wisc.edu } 1799148Spowerjg@cs.wisc.edu} 18010311Snilay@cs.wisc.edu 18110311Snilay@cs.wisc.edutemplate <class Impl> 18210311Snilay@cs.wisc.eduint 18310311Snilay@cs.wisc.eduROB<Impl>::entryAmount(ThreadID num_threads) 18410311Snilay@cs.wisc.edu{ 18510551Ssteve.reinhardt@amd.com if (robPolicy == Partitioned) { 18610551Ssteve.reinhardt@amd.com return numEntries / num_threads; 18710311Snilay@cs.wisc.edu } else { 18810311Snilay@cs.wisc.edu return 0; 18910551Ssteve.reinhardt@amd.com } 19010551Ssteve.reinhardt@amd.com} 19110551Ssteve.reinhardt@amd.com 19210311Snilay@cs.wisc.edutemplate <class Impl> 19310551Ssteve.reinhardt@amd.comint 19410311Snilay@cs.wisc.eduROB<Impl>::countInsts() 19510311Snilay@cs.wisc.edu{ 19610311Snilay@cs.wisc.edu int total = 0; 19710311Snilay@cs.wisc.edu 19810311Snilay@cs.wisc.edu for (ThreadID tid = 0; tid < numThreads; tid++) 19910311Snilay@cs.wisc.edu total += countInsts(tid); 20010311Snilay@cs.wisc.edu 20110311Snilay@cs.wisc.edu return total; 20210311Snilay@cs.wisc.edu} 20310311Snilay@cs.wisc.edu 20410311Snilay@cs.wisc.edutemplate <class Impl> 20510311Snilay@cs.wisc.eduint 20610311Snilay@cs.wisc.eduROB<Impl>::countInsts(ThreadID tid) 2079148Spowerjg@cs.wisc.edu{ 2089862Snilay@cs.wisc.edu return instList[tid].size(); 2099862Snilay@cs.wisc.edu} 21010122Snilay@cs.wisc.edu 21110122Snilay@cs.wisc.edutemplate <class Impl> 21210122Snilay@cs.wisc.eduvoid 21310122Snilay@cs.wisc.eduROB<Impl>::insertInst(DynInstPtr &inst) 21410122Snilay@cs.wisc.edu{ 2158257SBrad.Beckmann@amd.com assert(inst); 2168612Stushar@csail.mit.edu 2178612Stushar@csail.mit.edu robWrites++; 2189593Snilay@cs.wisc.edu 2199593Snilay@cs.wisc.edu DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState()); 2206892SBrad.Beckmann@amd.com 22110524Snilay@cs.wisc.edu assert(numInstsInROB != numEntries); 22210116Snilay@cs.wisc.edu 22310116Snilay@cs.wisc.edu ThreadID tid = inst->threadNumber; 22410116Snilay@cs.wisc.edu 22510116Snilay@cs.wisc.edu instList[tid].push_back(inst); 22610116Snilay@cs.wisc.edu 22710116Snilay@cs.wisc.edu //Set Up head iterator if this is the 1st instruction in the ROB 22810116Snilay@cs.wisc.edu if (numInstsInROB == 0) { 22910116Snilay@cs.wisc.edu head = instList[tid].begin(); 23010116Snilay@cs.wisc.edu assert((*head) == inst); 23110116Snilay@cs.wisc.edu } 23210120Snilay@cs.wisc.edu 23310012Snilay@cs.wisc.edu //Must Decrement for iterator to actually be valid since __.end() 2347809Snilay@cs.wisc.edu //actually points to 1 after the last inst 23510525Snilay@cs.wisc.edu tail = instList[tid].end(); 23610630Snilay@cs.wisc.edu tail--; 23710630Snilay@cs.wisc.edu 23810706Spower.jg@gmail.com inst->setInROB(); 23910706Spower.jg@gmail.com 24010630Snilay@cs.wisc.edu ++numInstsInROB; 24110630Snilay@cs.wisc.edu ++threadEntries[tid]; 24210529Smorr@cs.wisc.edu 24310529Smorr@cs.wisc.edu assert((*tail) == inst); 24410529Smorr@cs.wisc.edu 24510529Smorr@cs.wisc.edu DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]); 24610529Smorr@cs.wisc.edu} 24710529Smorr@cs.wisc.edu 24810529Smorr@cs.wisc.edutemplate <class Impl> 249void 250ROB<Impl>::retireHead(ThreadID tid) 251{ 252 robWrites++; 253 254 assert(numInstsInROB > 0); 255 256 // Get the head ROB instruction. 257 InstIt head_it = instList[tid].begin(); 258 259 DynInstPtr head_inst = (*head_it); 260 261 assert(head_inst->readyToCommit()); 262 263 DPRINTF(ROB, "[tid:%u]: Retiring head instruction, " 264 "instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(), 265 head_inst->seqNum); 266 267 --numInstsInROB; 268 --threadEntries[tid]; 269 270 head_inst->clearInROB(); 271 head_inst->setCommitted(); 272 273 instList[tid].erase(head_it); 274 275 //Update "Global" Head of ROB 276 updateHead(); 277 278 // @todo: A special case is needed if the instruction being 279 // retired is the only instruction in the ROB; otherwise the tail 280 // iterator will become invalidated. 281 cpu->removeFrontInst(head_inst); 282} 283 284template <class Impl> 285bool 286ROB<Impl>::isHeadReady(ThreadID tid) 287{ 288 robReads++; 289 if (threadEntries[tid] != 0) { 290 return instList[tid].front()->readyToCommit(); 291 } 292 293 return false; 294} 295 296template <class Impl> 297bool 298ROB<Impl>::canCommit() 299{ 300 //@todo: set ActiveThreads through ROB or CPU 301 list<ThreadID>::iterator threads = activeThreads->begin(); 302 list<ThreadID>::iterator end = activeThreads->end(); 303 304 while (threads != end) { 305 ThreadID tid = *threads++; 306 307 if (isHeadReady(tid)) { 308 return true; 309 } 310 } 311 312 return false; 313} 314 315template <class Impl> 316unsigned 317ROB<Impl>::numFreeEntries() 318{ 319 return numEntries - numInstsInROB; 320} 321 322template <class Impl> 323unsigned 324ROB<Impl>::numFreeEntries(ThreadID tid) 325{ 326 return maxEntries[tid] - threadEntries[tid]; 327} 328 329template <class Impl> 330void 331ROB<Impl>::doSquash(ThreadID tid) 332{ 333 robWrites++; 334 DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n", 335 tid, squashedSeqNum[tid]); 336 337 assert(squashIt[tid] != instList[tid].end()); 338 339 if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) { 340 DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 341 tid); 342 343 squashIt[tid] = instList[tid].end(); 344 345 doneSquashing[tid] = true; 346 return; 347 } 348 349 bool robTailUpdate = false; 350 351 for (int numSquashed = 0; 352 numSquashed < squashWidth && 353 squashIt[tid] != instList[tid].end() && 354 (*squashIt[tid])->seqNum > squashedSeqNum[tid]; 355 ++numSquashed) 356 { 357 DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq num %i.\n", 358 (*squashIt[tid])->threadNumber, 359 (*squashIt[tid])->pcState(), 360 (*squashIt[tid])->seqNum); 361 362 // Mark the instruction as squashed, and ready to commit so that 363 // it can drain out of the pipeline. 364 (*squashIt[tid])->setSquashed(); 365 366 (*squashIt[tid])->setCanCommit(); 367 368 369 if (squashIt[tid] == instList[tid].begin()) { 370 DPRINTF(ROB, "Reached head of instruction list while " 371 "squashing.\n"); 372 373 squashIt[tid] = instList[tid].end(); 374 375 doneSquashing[tid] = true; 376 377 return; 378 } 379 380 InstIt tail_thread = instList[tid].end(); 381 tail_thread--; 382 383 if ((*squashIt[tid]) == (*tail_thread)) 384 robTailUpdate = true; 385 386 squashIt[tid]--; 387 } 388 389 390 // Check if ROB is done squashing. 391 if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) { 392 DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 393 tid); 394 395 squashIt[tid] = instList[tid].end(); 396 397 doneSquashing[tid] = true; 398 } 399 400 if (robTailUpdate) { 401 updateTail(); 402 } 403} 404 405 406template <class Impl> 407void 408ROB<Impl>::updateHead() 409{ 410 InstSeqNum lowest_num = 0; 411 bool first_valid = true; 412 413 // @todo: set ActiveThreads through ROB or CPU 414 list<ThreadID>::iterator threads = activeThreads->begin(); 415 list<ThreadID>::iterator end = activeThreads->end(); 416 417 while (threads != end) { 418 ThreadID tid = *threads++; 419 420 if (instList[tid].empty()) 421 continue; 422 423 if (first_valid) { 424 head = instList[tid].begin(); 425 lowest_num = (*head)->seqNum; 426 first_valid = false; 427 continue; 428 } 429 430 InstIt head_thread = instList[tid].begin(); 431 432 DynInstPtr head_inst = (*head_thread); 433 434 assert(head_inst != 0); 435 436 if (head_inst->seqNum < lowest_num) { 437 head = head_thread; 438 lowest_num = head_inst->seqNum; 439 } 440 } 441 442 if (first_valid) { 443 head = instList[0].end(); 444 } 445 446} 447 448template <class Impl> 449void 450ROB<Impl>::updateTail() 451{ 452 tail = instList[0].end(); 453 bool first_valid = true; 454 455 list<ThreadID>::iterator threads = activeThreads->begin(); 456 list<ThreadID>::iterator end = activeThreads->end(); 457 458 while (threads != end) { 459 ThreadID tid = *threads++; 460 461 if (instList[tid].empty()) { 462 continue; 463 } 464 465 // If this is the first valid then assign w/out 466 // comparison 467 if (first_valid) { 468 tail = instList[tid].end(); 469 tail--; 470 first_valid = false; 471 continue; 472 } 473 474 // Assign new tail if this thread's tail is younger 475 // than our current "tail high" 476 InstIt tail_thread = instList[tid].end(); 477 tail_thread--; 478 479 if ((*tail_thread)->seqNum > (*tail)->seqNum) { 480 tail = tail_thread; 481 } 482 } 483} 484 485 486template <class Impl> 487void 488ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid) 489{ 490 if (isEmpty()) { 491 DPRINTF(ROB, "Does not need to squash due to being empty " 492 "[sn:%i]\n", 493 squash_num); 494 495 return; 496 } 497 498 DPRINTF(ROB, "Starting to squash within the ROB.\n"); 499 500 robStatus[tid] = ROBSquashing; 501 502 doneSquashing[tid] = false; 503 504 squashedSeqNum[tid] = squash_num; 505 506 if (!instList[tid].empty()) { 507 InstIt tail_thread = instList[tid].end(); 508 tail_thread--; 509 510 squashIt[tid] = tail_thread; 511 512 doSquash(tid); 513 } 514} 515 516template <class Impl> 517typename Impl::DynInstPtr 518ROB<Impl>::readHeadInst(ThreadID tid) 519{ 520 if (threadEntries[tid] != 0) { 521 InstIt head_thread = instList[tid].begin(); 522 523 assert((*head_thread)->isInROB()==true); 524 525 return *head_thread; 526 } else { 527 return dummyInst; 528 } 529} 530 531template <class Impl> 532typename Impl::DynInstPtr 533ROB<Impl>::readTailInst(ThreadID tid) 534{ 535 InstIt tail_thread = instList[tid].end(); 536 tail_thread--; 537 538 return *tail_thread; 539} 540 541template <class Impl> 542void 543ROB<Impl>::regStats() 544{ 545 using namespace Stats; 546 robReads 547 .name(name() + ".rob_reads") 548 .desc("The number of ROB reads"); 549 550 robWrites 551 .name(name() + ".rob_writes") 552 .desc("The number of ROB writes"); 553} 554 555template <class Impl> 556typename Impl::DynInstPtr 557ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst) 558{ 559 for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) { 560 if ((*it)->seqNum == squash_inst) { 561 return *it; 562 } 563 } 564 return NULL; 565} 566 567#endif//__CPU_O3_ROB_IMPL_HH__ 568