rob_impl.hh revision 9444
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2012 ARM Limited 36019Shines@cs.fsu.edu * All rights reserved 46019Shines@cs.fsu.edu * 56019Shines@cs.fsu.edu * The license below extends only to copyright in the software and shall 66019Shines@cs.fsu.edu * not be construed as granting a license to any other intellectual 76019Shines@cs.fsu.edu * property including but not limited to intellectual property relating 86019Shines@cs.fsu.edu * to a hardware implementation of the functionality of the software 96019Shines@cs.fsu.edu * licensed hereunder. You may use the software subject to the license 106019Shines@cs.fsu.edu * terms below provided that you ensure that this notice is replicated 116019Shines@cs.fsu.edu * unmodified and in its entirety in all distributions of the software, 126019Shines@cs.fsu.edu * modified or unmodified, in source code or in binary form. 136019Shines@cs.fsu.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Kevin Lim 416019Shines@cs.fsu.edu * Korey Sewell 426019Shines@cs.fsu.edu */ 436019Shines@cs.fsu.edu 446019Shines@cs.fsu.edu#include <list> 456019Shines@cs.fsu.edu 466243Sgblack@eecs.umich.edu#include "cpu/o3/rob.hh" 476243Sgblack@eecs.umich.edu#include "debug/Fetch.hh" 486243Sgblack@eecs.umich.edu#include "debug/ROB.hh" 496243Sgblack@eecs.umich.edu 506243Sgblack@eecs.umich.eduusing namespace std; 516019Shines@cs.fsu.edu 526019Shines@cs.fsu.edutemplate <class Impl> 536019Shines@cs.fsu.eduROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 546019Shines@cs.fsu.edu std::string _smtROBPolicy, unsigned _smtROBThreshold, 556019Shines@cs.fsu.edu ThreadID _numThreads) 566019Shines@cs.fsu.edu : cpu(_cpu), 576019Shines@cs.fsu.edu numEntries(_numEntries), 586019Shines@cs.fsu.edu squashWidth(_squashWidth), 596019Shines@cs.fsu.edu numInstsInROB(0), 606019Shines@cs.fsu.edu numThreads(_numThreads) 616019Shines@cs.fsu.edu{ 626019Shines@cs.fsu.edu std::string policy = _smtROBPolicy; 636019Shines@cs.fsu.edu 646019Shines@cs.fsu.edu //Convert string to lowercase 656019Shines@cs.fsu.edu std::transform(policy.begin(), policy.end(), policy.begin(), 666019Shines@cs.fsu.edu (int(*)(int)) tolower); 676019Shines@cs.fsu.edu 686019Shines@cs.fsu.edu //Figure out rob policy 696019Shines@cs.fsu.edu if (policy == "dynamic") { 706019Shines@cs.fsu.edu robPolicy = Dynamic; 716019Shines@cs.fsu.edu 726019Shines@cs.fsu.edu //Set Max Entries to Total ROB Capacity 736019Shines@cs.fsu.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 746019Shines@cs.fsu.edu maxEntries[tid] = numEntries; 756019Shines@cs.fsu.edu } 766019Shines@cs.fsu.edu 776019Shines@cs.fsu.edu } else if (policy == "partitioned") { 786019Shines@cs.fsu.edu robPolicy = Partitioned; 796019Shines@cs.fsu.edu DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n"); 806019Shines@cs.fsu.edu 816019Shines@cs.fsu.edu //@todo:make work if part_amt doesnt divide evenly. 826252Sgblack@eecs.umich.edu int part_amt = numEntries / numThreads; 836243Sgblack@eecs.umich.edu 846243Sgblack@eecs.umich.edu //Divide ROB up evenly 856243Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 866019Shines@cs.fsu.edu maxEntries[tid] = part_amt; 876019Shines@cs.fsu.edu } 886019Shines@cs.fsu.edu 896019Shines@cs.fsu.edu } else if (policy == "threshold") { 906019Shines@cs.fsu.edu robPolicy = Threshold; 916252Sgblack@eecs.umich.edu DPRINTF(Fetch, "ROB sharing policy set to Threshold\n"); 926243Sgblack@eecs.umich.edu 936243Sgblack@eecs.umich.edu int threshold = _smtROBThreshold;; 946243Sgblack@eecs.umich.edu 956019Shines@cs.fsu.edu //Divide up by threshold amount 966019Shines@cs.fsu.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 976019Shines@cs.fsu.edu maxEntries[tid] = threshold; 986019Shines@cs.fsu.edu } 996019Shines@cs.fsu.edu } else { 1006019Shines@cs.fsu.edu assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic," 1016019Shines@cs.fsu.edu "Partitioned, Threshold}"); 1026252Sgblack@eecs.umich.edu } 1036243Sgblack@eecs.umich.edu 1046243Sgblack@eecs.umich.edu resetState(); 1056243Sgblack@eecs.umich.edu} 1066019Shines@cs.fsu.edu 1076019Shines@cs.fsu.edutemplate <class Impl> 1086019Shines@cs.fsu.eduvoid 1096019Shines@cs.fsu.eduROB<Impl>::resetState() 1106019Shines@cs.fsu.edu{ 1116019Shines@cs.fsu.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1126019Shines@cs.fsu.edu doneSquashing[tid] = true; 1136019Shines@cs.fsu.edu threadEntries[tid] = 0; 1146019Shines@cs.fsu.edu squashIt[tid] = instList[tid].end(); 1156019Shines@cs.fsu.edu squashedSeqNum[tid] = 0; 1166019Shines@cs.fsu.edu } 1176019Shines@cs.fsu.edu numInstsInROB = 0; 1186019Shines@cs.fsu.edu 1196019Shines@cs.fsu.edu // Initialize the "universal" ROB head & tail point to invalid 1206019Shines@cs.fsu.edu // pointers 1216019Shines@cs.fsu.edu head = instList[0].end(); 1226724Sgblack@eecs.umich.edu tail = instList[0].end(); 1236724Sgblack@eecs.umich.edu} 1246019Shines@cs.fsu.edu 1256019Shines@cs.fsu.edutemplate <class Impl> 1266019Shines@cs.fsu.edustd::string 1276019Shines@cs.fsu.eduROB<Impl>::name() const 1286019Shines@cs.fsu.edu{ 1296252Sgblack@eecs.umich.edu return cpu->name() + ".rob"; 1306243Sgblack@eecs.umich.edu} 1316243Sgblack@eecs.umich.edu 1326243Sgblack@eecs.umich.edutemplate <class Impl> 1336019Shines@cs.fsu.eduvoid 1346019Shines@cs.fsu.eduROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 1356019Shines@cs.fsu.edu{ 1366019Shines@cs.fsu.edu DPRINTF(ROB, "Setting active threads list pointer.\n"); 1376019Shines@cs.fsu.edu activeThreads = at_ptr; 1386019Shines@cs.fsu.edu} 1396019Shines@cs.fsu.edu 140template <class Impl> 141void 142ROB<Impl>::drainSanityCheck() const 143{ 144 for (ThreadID tid = 0; tid < numThreads; tid++) 145 assert(instList[tid].empty()); 146 assert(isEmpty()); 147} 148 149template <class Impl> 150void 151ROB<Impl>::takeOverFrom() 152{ 153 resetState(); 154} 155 156template <class Impl> 157void 158ROB<Impl>::resetEntries() 159{ 160 if (robPolicy != Dynamic || numThreads > 1) { 161 int active_threads = activeThreads->size(); 162 163 list<ThreadID>::iterator threads = activeThreads->begin(); 164 list<ThreadID>::iterator end = activeThreads->end(); 165 166 while (threads != end) { 167 ThreadID tid = *threads++; 168 169 if (robPolicy == Partitioned) { 170 maxEntries[tid] = numEntries / active_threads; 171 } else if (robPolicy == Threshold && active_threads == 1) { 172 maxEntries[tid] = numEntries; 173 } 174 } 175 } 176} 177 178template <class Impl> 179int 180ROB<Impl>::entryAmount(ThreadID num_threads) 181{ 182 if (robPolicy == Partitioned) { 183 return numEntries / num_threads; 184 } else { 185 return 0; 186 } 187} 188 189template <class Impl> 190int 191ROB<Impl>::countInsts() 192{ 193 int total = 0; 194 195 for (ThreadID tid = 0; tid < numThreads; tid++) 196 total += countInsts(tid); 197 198 return total; 199} 200 201template <class Impl> 202int 203ROB<Impl>::countInsts(ThreadID tid) 204{ 205 return instList[tid].size(); 206} 207 208template <class Impl> 209void 210ROB<Impl>::insertInst(DynInstPtr &inst) 211{ 212 assert(inst); 213 214 robWrites++; 215 216 DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState()); 217 218 assert(numInstsInROB != numEntries); 219 220 ThreadID tid = inst->threadNumber; 221 222 instList[tid].push_back(inst); 223 224 //Set Up head iterator if this is the 1st instruction in the ROB 225 if (numInstsInROB == 0) { 226 head = instList[tid].begin(); 227 assert((*head) == inst); 228 } 229 230 //Must Decrement for iterator to actually be valid since __.end() 231 //actually points to 1 after the last inst 232 tail = instList[tid].end(); 233 tail--; 234 235 inst->setInROB(); 236 237 ++numInstsInROB; 238 ++threadEntries[tid]; 239 240 assert((*tail) == inst); 241 242 DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]); 243} 244 245template <class Impl> 246void 247ROB<Impl>::retireHead(ThreadID tid) 248{ 249 robWrites++; 250 251 assert(numInstsInROB > 0); 252 253 // Get the head ROB instruction. 254 InstIt head_it = instList[tid].begin(); 255 256 DynInstPtr head_inst = (*head_it); 257 258 assert(head_inst->readyToCommit()); 259 260 DPRINTF(ROB, "[tid:%u]: Retiring head instruction, " 261 "instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(), 262 head_inst->seqNum); 263 264 --numInstsInROB; 265 --threadEntries[tid]; 266 267 head_inst->clearInROB(); 268 head_inst->setCommitted(); 269 270 instList[tid].erase(head_it); 271 272 //Update "Global" Head of ROB 273 updateHead(); 274 275 // @todo: A special case is needed if the instruction being 276 // retired is the only instruction in the ROB; otherwise the tail 277 // iterator will become invalidated. 278 cpu->removeFrontInst(head_inst); 279} 280 281template <class Impl> 282bool 283ROB<Impl>::isHeadReady(ThreadID tid) 284{ 285 robReads++; 286 if (threadEntries[tid] != 0) { 287 return instList[tid].front()->readyToCommit(); 288 } 289 290 return false; 291} 292 293template <class Impl> 294bool 295ROB<Impl>::canCommit() 296{ 297 //@todo: set ActiveThreads through ROB or CPU 298 list<ThreadID>::iterator threads = activeThreads->begin(); 299 list<ThreadID>::iterator end = activeThreads->end(); 300 301 while (threads != end) { 302 ThreadID tid = *threads++; 303 304 if (isHeadReady(tid)) { 305 return true; 306 } 307 } 308 309 return false; 310} 311 312template <class Impl> 313unsigned 314ROB<Impl>::numFreeEntries() 315{ 316 return numEntries - numInstsInROB; 317} 318 319template <class Impl> 320unsigned 321ROB<Impl>::numFreeEntries(ThreadID tid) 322{ 323 return maxEntries[tid] - threadEntries[tid]; 324} 325 326template <class Impl> 327void 328ROB<Impl>::doSquash(ThreadID tid) 329{ 330 robWrites++; 331 DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n", 332 tid, squashedSeqNum[tid]); 333 334 assert(squashIt[tid] != instList[tid].end()); 335 336 if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) { 337 DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 338 tid); 339 340 squashIt[tid] = instList[tid].end(); 341 342 doneSquashing[tid] = true; 343 return; 344 } 345 346 bool robTailUpdate = false; 347 348 for (int numSquashed = 0; 349 numSquashed < squashWidth && 350 squashIt[tid] != instList[tid].end() && 351 (*squashIt[tid])->seqNum > squashedSeqNum[tid]; 352 ++numSquashed) 353 { 354 DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq num %i.\n", 355 (*squashIt[tid])->threadNumber, 356 (*squashIt[tid])->pcState(), 357 (*squashIt[tid])->seqNum); 358 359 // Mark the instruction as squashed, and ready to commit so that 360 // it can drain out of the pipeline. 361 (*squashIt[tid])->setSquashed(); 362 363 (*squashIt[tid])->setCanCommit(); 364 365 366 if (squashIt[tid] == instList[tid].begin()) { 367 DPRINTF(ROB, "Reached head of instruction list while " 368 "squashing.\n"); 369 370 squashIt[tid] = instList[tid].end(); 371 372 doneSquashing[tid] = true; 373 374 return; 375 } 376 377 InstIt tail_thread = instList[tid].end(); 378 tail_thread--; 379 380 if ((*squashIt[tid]) == (*tail_thread)) 381 robTailUpdate = true; 382 383 squashIt[tid]--; 384 } 385 386 387 // Check if ROB is done squashing. 388 if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) { 389 DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 390 tid); 391 392 squashIt[tid] = instList[tid].end(); 393 394 doneSquashing[tid] = true; 395 } 396 397 if (robTailUpdate) { 398 updateTail(); 399 } 400} 401 402 403template <class Impl> 404void 405ROB<Impl>::updateHead() 406{ 407 DynInstPtr head_inst; 408 InstSeqNum lowest_num = 0; 409 bool first_valid = true; 410 411 // @todo: set ActiveThreads through ROB or CPU 412 list<ThreadID>::iterator threads = activeThreads->begin(); 413 list<ThreadID>::iterator end = activeThreads->end(); 414 415 while (threads != end) { 416 ThreadID tid = *threads++; 417 418 if (instList[tid].empty()) 419 continue; 420 421 if (first_valid) { 422 head = instList[tid].begin(); 423 lowest_num = (*head)->seqNum; 424 first_valid = false; 425 continue; 426 } 427 428 InstIt head_thread = instList[tid].begin(); 429 430 DynInstPtr head_inst = (*head_thread); 431 432 assert(head_inst != 0); 433 434 if (head_inst->seqNum < lowest_num) { 435 head = head_thread; 436 lowest_num = head_inst->seqNum; 437 } 438 } 439 440 if (first_valid) { 441 head = instList[0].end(); 442 } 443 444} 445 446template <class Impl> 447void 448ROB<Impl>::updateTail() 449{ 450 tail = instList[0].end(); 451 bool first_valid = true; 452 453 list<ThreadID>::iterator threads = activeThreads->begin(); 454 list<ThreadID>::iterator end = activeThreads->end(); 455 456 while (threads != end) { 457 ThreadID tid = *threads++; 458 459 if (instList[tid].empty()) { 460 continue; 461 } 462 463 // If this is the first valid then assign w/out 464 // comparison 465 if (first_valid) { 466 tail = instList[tid].end(); 467 tail--; 468 first_valid = false; 469 continue; 470 } 471 472 // Assign new tail if this thread's tail is younger 473 // than our current "tail high" 474 InstIt tail_thread = instList[tid].end(); 475 tail_thread--; 476 477 if ((*tail_thread)->seqNum > (*tail)->seqNum) { 478 tail = tail_thread; 479 } 480 } 481} 482 483 484template <class Impl> 485void 486ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid) 487{ 488 if (isEmpty()) { 489 DPRINTF(ROB, "Does not need to squash due to being empty " 490 "[sn:%i]\n", 491 squash_num); 492 493 return; 494 } 495 496 DPRINTF(ROB, "Starting to squash within the ROB.\n"); 497 498 robStatus[tid] = ROBSquashing; 499 500 doneSquashing[tid] = false; 501 502 squashedSeqNum[tid] = squash_num; 503 504 if (!instList[tid].empty()) { 505 InstIt tail_thread = instList[tid].end(); 506 tail_thread--; 507 508 squashIt[tid] = tail_thread; 509 510 doSquash(tid); 511 } 512} 513 514template <class Impl> 515typename Impl::DynInstPtr 516ROB<Impl>::readHeadInst(ThreadID tid) 517{ 518 if (threadEntries[tid] != 0) { 519 InstIt head_thread = instList[tid].begin(); 520 521 assert((*head_thread)->isInROB()==true); 522 523 return *head_thread; 524 } else { 525 return dummyInst; 526 } 527} 528 529template <class Impl> 530typename Impl::DynInstPtr 531ROB<Impl>::readTailInst(ThreadID tid) 532{ 533 InstIt tail_thread = instList[tid].end(); 534 tail_thread--; 535 536 return *tail_thread; 537} 538 539template <class Impl> 540void 541ROB<Impl>::regStats() 542{ 543 using namespace Stats; 544 robReads 545 .name(name() + ".rob_reads") 546 .desc("The number of ROB reads"); 547 548 robWrites 549 .name(name() + ".rob_writes") 550 .desc("The number of ROB writes"); 551} 552 553template <class Impl> 554typename Impl::DynInstPtr 555ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst) 556{ 557 for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) { 558 if ((*it)->seqNum == squash_inst) { 559 return *it; 560 } 561 } 562 return NULL; 563} 564