rob_impl.hh revision 9444
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412831Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 446221Snate@binkert.org#include <list> 456221Snate@binkert.org 461717SN/A#include "cpu/o3/rob.hh" 478232Snate@binkert.org#include "debug/Fetch.hh" 488232Snate@binkert.org#include "debug/ROB.hh" 491060SN/A 506221Snate@binkert.orgusing namespace std; 512292SN/A 521061SN/Atemplate <class Impl> 534329Sktlim@umich.eduROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 542980Sgblack@eecs.umich.edu std::string _smtROBPolicy, unsigned _smtROBThreshold, 556221Snate@binkert.org ThreadID _numThreads) 564329Sktlim@umich.edu : cpu(_cpu), 574329Sktlim@umich.edu numEntries(_numEntries), 581060SN/A squashWidth(_squashWidth), 591060SN/A numInstsInROB(0), 602292SN/A numThreads(_numThreads) 611060SN/A{ 622980Sgblack@eecs.umich.edu std::string policy = _smtROBPolicy; 632292SN/A 642292SN/A //Convert string to lowercase 652292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 662292SN/A (int(*)(int)) tolower); 672292SN/A 682292SN/A //Figure out rob policy 692292SN/A if (policy == "dynamic") { 702292SN/A robPolicy = Dynamic; 712292SN/A 722292SN/A //Set Max Entries to Total ROB Capacity 736221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 746221Snate@binkert.org maxEntries[tid] = numEntries; 752292SN/A } 762292SN/A 772292SN/A } else if (policy == "partitioned") { 782292SN/A robPolicy = Partitioned; 794329Sktlim@umich.edu DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n"); 802292SN/A 812292SN/A //@todo:make work if part_amt doesnt divide evenly. 822292SN/A int part_amt = numEntries / numThreads; 832292SN/A 842292SN/A //Divide ROB up evenly 856221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 866221Snate@binkert.org maxEntries[tid] = part_amt; 872292SN/A } 882292SN/A 892292SN/A } else if (policy == "threshold") { 902292SN/A robPolicy = Threshold; 914329Sktlim@umich.edu DPRINTF(Fetch, "ROB sharing policy set to Threshold\n"); 922292SN/A 932292SN/A int threshold = _smtROBThreshold;; 942292SN/A 952292SN/A //Divide up by threshold amount 966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 976221Snate@binkert.org maxEntries[tid] = threshold; 982292SN/A } 992292SN/A } else { 1002292SN/A assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic," 1012292SN/A "Partitioned, Threshold}"); 1022292SN/A } 1031060SN/A 1049444SAndreas.Sandberg@ARM.com resetState(); 1059444SAndreas.Sandberg@ARM.com} 1069444SAndreas.Sandberg@ARM.com 1079444SAndreas.Sandberg@ARM.comtemplate <class Impl> 1089444SAndreas.Sandberg@ARM.comvoid 1099444SAndreas.Sandberg@ARM.comROB<Impl>::resetState() 1109444SAndreas.Sandberg@ARM.com{ 1119444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 1129444SAndreas.Sandberg@ARM.com doneSquashing[tid] = true; 1139444SAndreas.Sandberg@ARM.com threadEntries[tid] = 0; 1146221Snate@binkert.org squashIt[tid] = instList[tid].end(); 1159444SAndreas.Sandberg@ARM.com squashedSeqNum[tid] = 0; 1162292SN/A } 1179444SAndreas.Sandberg@ARM.com numInstsInROB = 0; 1181060SN/A 1192292SN/A // Initialize the "universal" ROB head & tail point to invalid 1202292SN/A // pointers 1212292SN/A head = instList[0].end(); 1222292SN/A tail = instList[0].end(); 1232292SN/A} 1242292SN/A 1252292SN/Atemplate <class Impl> 1264329Sktlim@umich.edustd::string 1274329Sktlim@umich.eduROB<Impl>::name() const 1284329Sktlim@umich.edu{ 1294329Sktlim@umich.edu return cpu->name() + ".rob"; 1304329Sktlim@umich.edu} 1314329Sktlim@umich.edu 1324329Sktlim@umich.edutemplate <class Impl> 1332292SN/Avoid 1346221Snate@binkert.orgROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 1352292SN/A{ 1362292SN/A DPRINTF(ROB, "Setting active threads list pointer.\n"); 1372292SN/A activeThreads = at_ptr; 1382292SN/A} 1392292SN/A 1402307SN/Atemplate <class Impl> 1412307SN/Avoid 1429444SAndreas.Sandberg@ARM.comROB<Impl>::drainSanityCheck() const 1432307SN/A{ 1449444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) 1459444SAndreas.Sandberg@ARM.com assert(instList[tid].empty()); 1469444SAndreas.Sandberg@ARM.com assert(isEmpty()); 1472307SN/A} 1482307SN/A 1492307SN/Atemplate <class Impl> 1502307SN/Avoid 1512307SN/AROB<Impl>::takeOverFrom() 1522307SN/A{ 1539444SAndreas.Sandberg@ARM.com resetState(); 1542307SN/A} 1552292SN/A 1562292SN/Atemplate <class Impl> 1572292SN/Avoid 1582292SN/AROB<Impl>::resetEntries() 1592292SN/A{ 1602292SN/A if (robPolicy != Dynamic || numThreads > 1) { 1613867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 1622292SN/A 1636221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 1646221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 1652292SN/A 1663867Sbinkertn@umich.edu while (threads != end) { 1676221Snate@binkert.org ThreadID tid = *threads++; 1683867Sbinkertn@umich.edu 1692292SN/A if (robPolicy == Partitioned) { 1703867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 1712292SN/A } else if (robPolicy == Threshold && active_threads == 1) { 1723867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 1732292SN/A } 1742292SN/A } 1752292SN/A } 1762292SN/A} 1772292SN/A 1782292SN/Atemplate <class Impl> 1792292SN/Aint 1806221Snate@binkert.orgROB<Impl>::entryAmount(ThreadID num_threads) 1812292SN/A{ 1822292SN/A if (robPolicy == Partitioned) { 1832292SN/A return numEntries / num_threads; 1842292SN/A } else { 1852292SN/A return 0; 1862292SN/A } 1871060SN/A} 1881060SN/A 1891061SN/Atemplate <class Impl> 1901060SN/Aint 1911060SN/AROB<Impl>::countInsts() 1921060SN/A{ 1936221Snate@binkert.org int total = 0; 1941061SN/A 1956221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 1966221Snate@binkert.org total += countInsts(tid); 1971060SN/A 1982292SN/A return total; 1992292SN/A} 2001060SN/A 2012292SN/Atemplate <class Impl> 2022292SN/Aint 2036221Snate@binkert.orgROB<Impl>::countInsts(ThreadID tid) 2042292SN/A{ 2052292SN/A return instList[tid].size(); 2061060SN/A} 2071060SN/A 2081061SN/Atemplate <class Impl> 2091060SN/Avoid 2101061SN/AROB<Impl>::insertInst(DynInstPtr &inst) 2111060SN/A{ 2121060SN/A assert(inst); 2131060SN/A 2147897Shestness@cs.utexas.edu robWrites++; 2157897Shestness@cs.utexas.edu 2167720Sgblack@eecs.umich.edu DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState()); 2171060SN/A 2181060SN/A assert(numInstsInROB != numEntries); 2191060SN/A 2206221Snate@binkert.org ThreadID tid = inst->threadNumber; 2211060SN/A 2222292SN/A instList[tid].push_back(inst); 2232292SN/A 2242292SN/A //Set Up head iterator if this is the 1st instruction in the ROB 2252292SN/A if (numInstsInROB == 0) { 2262292SN/A head = instList[tid].begin(); 2272292SN/A assert((*head) == inst); 2281060SN/A } 2291060SN/A 2302292SN/A //Must Decrement for iterator to actually be valid since __.end() 2312292SN/A //actually points to 1 after the last inst 2322292SN/A tail = instList[tid].end(); 2332292SN/A tail--; 2342292SN/A 2352292SN/A inst->setInROB(); 2362292SN/A 2372292SN/A ++numInstsInROB; 2382292SN/A ++threadEntries[tid]; 2392292SN/A 2401060SN/A assert((*tail) == inst); 2411060SN/A 2422292SN/A DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]); 2431060SN/A} 2441060SN/A 2452292SN/Atemplate <class Impl> 2462292SN/Avoid 2476221Snate@binkert.orgROB<Impl>::retireHead(ThreadID tid) 2482292SN/A{ 2497897Shestness@cs.utexas.edu robWrites++; 2507897Shestness@cs.utexas.edu 2511061SN/A assert(numInstsInROB > 0); 2521060SN/A 2531060SN/A // Get the head ROB instruction. 2542292SN/A InstIt head_it = instList[tid].begin(); 2551060SN/A 2562292SN/A DynInstPtr head_inst = (*head_it); 2571858SN/A 2581060SN/A assert(head_inst->readyToCommit()); 2591060SN/A 2602292SN/A DPRINTF(ROB, "[tid:%u]: Retiring head instruction, " 2617720Sgblack@eecs.umich.edu "instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(), 2621060SN/A head_inst->seqNum); 2631060SN/A 2641060SN/A --numInstsInROB; 2652292SN/A --threadEntries[tid]; 2661060SN/A 2672731Sktlim@umich.edu head_inst->clearInROB(); 2682292SN/A head_inst->setCommitted(); 2692292SN/A 2702292SN/A instList[tid].erase(head_it); 2712292SN/A 2722292SN/A //Update "Global" Head of ROB 2732292SN/A updateHead(); 2742292SN/A 2752329SN/A // @todo: A special case is needed if the instruction being 2762329SN/A // retired is the only instruction in the ROB; otherwise the tail 2772329SN/A // iterator will become invalidated. 2781681SN/A cpu->removeFrontInst(head_inst); 2791060SN/A} 2802292SN/A 2812292SN/Atemplate <class Impl> 2822292SN/Abool 2836221Snate@binkert.orgROB<Impl>::isHeadReady(ThreadID tid) 2842292SN/A{ 2857897Shestness@cs.utexas.edu robReads++; 2862292SN/A if (threadEntries[tid] != 0) { 2872292SN/A return instList[tid].front()->readyToCommit(); 2882292SN/A } 2892292SN/A 2902292SN/A return false; 2912292SN/A} 2922292SN/A 2932292SN/Atemplate <class Impl> 2942292SN/Abool 2952292SN/AROB<Impl>::canCommit() 2962292SN/A{ 2972292SN/A //@todo: set ActiveThreads through ROB or CPU 2986221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 2996221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3002292SN/A 3013867Sbinkertn@umich.edu while (threads != end) { 3026221Snate@binkert.org ThreadID tid = *threads++; 3032292SN/A 3042292SN/A if (isHeadReady(tid)) { 3052292SN/A return true; 3062292SN/A } 3071060SN/A } 3081060SN/A 3091060SN/A return false; 3101060SN/A} 3111060SN/A 3121061SN/Atemplate <class Impl> 3131060SN/Aunsigned 3141060SN/AROB<Impl>::numFreeEntries() 3151060SN/A{ 3161060SN/A return numEntries - numInstsInROB; 3171060SN/A} 3181060SN/A 3191061SN/Atemplate <class Impl> 3202292SN/Aunsigned 3216221Snate@binkert.orgROB<Impl>::numFreeEntries(ThreadID tid) 3221060SN/A{ 3232292SN/A return maxEntries[tid] - threadEntries[tid]; 3241060SN/A} 3251060SN/A 3261061SN/Atemplate <class Impl> 3271060SN/Avoid 3286221Snate@binkert.orgROB<Impl>::doSquash(ThreadID tid) 3291060SN/A{ 3307897Shestness@cs.utexas.edu robWrites++; 3312292SN/A DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n", 3322877Sksewell@umich.edu tid, squashedSeqNum[tid]); 3331858SN/A 3342292SN/A assert(squashIt[tid] != instList[tid].end()); 3352292SN/A 3362877Sksewell@umich.edu if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) { 3372292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 3382292SN/A tid); 3392292SN/A 3402292SN/A squashIt[tid] = instList[tid].end(); 3412292SN/A 3422292SN/A doneSquashing[tid] = true; 3432292SN/A return; 3442292SN/A } 3452292SN/A 3462292SN/A bool robTailUpdate = false; 3471858SN/A 3481858SN/A for (int numSquashed = 0; 3492292SN/A numSquashed < squashWidth && 3502292SN/A squashIt[tid] != instList[tid].end() && 3512877Sksewell@umich.edu (*squashIt[tid])->seqNum > squashedSeqNum[tid]; 3521858SN/A ++numSquashed) 3531858SN/A { 3547720Sgblack@eecs.umich.edu DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq num %i.\n", 3552292SN/A (*squashIt[tid])->threadNumber, 3567720Sgblack@eecs.umich.edu (*squashIt[tid])->pcState(), 3572292SN/A (*squashIt[tid])->seqNum); 3581858SN/A 3591858SN/A // Mark the instruction as squashed, and ready to commit so that 3601858SN/A // it can drain out of the pipeline. 3612292SN/A (*squashIt[tid])->setSquashed(); 3621858SN/A 3632292SN/A (*squashIt[tid])->setCanCommit(); 3641858SN/A 3652292SN/A 3662292SN/A if (squashIt[tid] == instList[tid].begin()) { 3672292SN/A DPRINTF(ROB, "Reached head of instruction list while " 3681858SN/A "squashing.\n"); 3691858SN/A 3702292SN/A squashIt[tid] = instList[tid].end(); 3711858SN/A 3722292SN/A doneSquashing[tid] = true; 3731858SN/A 3741858SN/A return; 3751858SN/A } 3761858SN/A 3772292SN/A InstIt tail_thread = instList[tid].end(); 3782292SN/A tail_thread--; 3792292SN/A 3802292SN/A if ((*squashIt[tid]) == (*tail_thread)) 3812292SN/A robTailUpdate = true; 3822292SN/A 3832292SN/A squashIt[tid]--; 3841858SN/A } 3851858SN/A 3861858SN/A 3871858SN/A // Check if ROB is done squashing. 3882877Sksewell@umich.edu if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) { 3892292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 3902292SN/A tid); 3911858SN/A 3922292SN/A squashIt[tid] = instList[tid].end(); 3931858SN/A 3942292SN/A doneSquashing[tid] = true; 3952292SN/A } 3962292SN/A 3972292SN/A if (robTailUpdate) { 3982292SN/A updateTail(); 3992292SN/A } 4002292SN/A} 4012292SN/A 4022292SN/A 4032292SN/Atemplate <class Impl> 4042292SN/Avoid 4052292SN/AROB<Impl>::updateHead() 4062292SN/A{ 4072292SN/A DynInstPtr head_inst; 4082292SN/A InstSeqNum lowest_num = 0; 4092292SN/A bool first_valid = true; 4102292SN/A 4112292SN/A // @todo: set ActiveThreads through ROB or CPU 4126221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4136221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4142292SN/A 4153867Sbinkertn@umich.edu while (threads != end) { 4166221Snate@binkert.org ThreadID tid = *threads++; 4172292SN/A 4183867Sbinkertn@umich.edu if (instList[tid].empty()) 4192292SN/A continue; 4202292SN/A 4212292SN/A if (first_valid) { 4223867Sbinkertn@umich.edu head = instList[tid].begin(); 4232292SN/A lowest_num = (*head)->seqNum; 4242292SN/A first_valid = false; 4252292SN/A continue; 4262292SN/A } 4272292SN/A 4283867Sbinkertn@umich.edu InstIt head_thread = instList[tid].begin(); 4292292SN/A 4302292SN/A DynInstPtr head_inst = (*head_thread); 4312292SN/A 4322292SN/A assert(head_inst != 0); 4332292SN/A 4342292SN/A if (head_inst->seqNum < lowest_num) { 4352292SN/A head = head_thread; 4362292SN/A lowest_num = head_inst->seqNum; 4372292SN/A } 4382292SN/A } 4392292SN/A 4402292SN/A if (first_valid) { 4412292SN/A head = instList[0].end(); 4422292SN/A } 4432292SN/A 4442292SN/A} 4452292SN/A 4462292SN/Atemplate <class Impl> 4472292SN/Avoid 4482292SN/AROB<Impl>::updateTail() 4492292SN/A{ 4502292SN/A tail = instList[0].end(); 4512292SN/A bool first_valid = true; 4522292SN/A 4536221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4546221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4552292SN/A 4563867Sbinkertn@umich.edu while (threads != end) { 4576221Snate@binkert.org ThreadID tid = *threads++; 4582292SN/A 4592292SN/A if (instList[tid].empty()) { 4602292SN/A continue; 4612292SN/A } 4622292SN/A 4632292SN/A // If this is the first valid then assign w/out 4642292SN/A // comparison 4652292SN/A if (first_valid) { 4662292SN/A tail = instList[tid].end(); 4672292SN/A tail--; 4682292SN/A first_valid = false; 4692292SN/A continue; 4702292SN/A } 4712292SN/A 4722292SN/A // Assign new tail if this thread's tail is younger 4732292SN/A // than our current "tail high" 4742292SN/A InstIt tail_thread = instList[tid].end(); 4752292SN/A tail_thread--; 4762292SN/A 4772292SN/A if ((*tail_thread)->seqNum > (*tail)->seqNum) { 4782292SN/A tail = tail_thread; 4792292SN/A } 4802292SN/A } 4812292SN/A} 4822292SN/A 4832292SN/A 4842292SN/Atemplate <class Impl> 4852292SN/Avoid 4866221Snate@binkert.orgROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid) 4872292SN/A{ 4882292SN/A if (isEmpty()) { 4892292SN/A DPRINTF(ROB, "Does not need to squash due to being empty " 4902292SN/A "[sn:%i]\n", 4912292SN/A squash_num); 4922292SN/A 4932292SN/A return; 4942292SN/A } 4952292SN/A 4962292SN/A DPRINTF(ROB, "Starting to squash within the ROB.\n"); 4972292SN/A 4982292SN/A robStatus[tid] = ROBSquashing; 4992292SN/A 5002292SN/A doneSquashing[tid] = false; 5011060SN/A 5022877Sksewell@umich.edu squashedSeqNum[tid] = squash_num; 5031060SN/A 5042292SN/A if (!instList[tid].empty()) { 5052292SN/A InstIt tail_thread = instList[tid].end(); 5062292SN/A tail_thread--; 5071060SN/A 5082292SN/A squashIt[tid] = tail_thread; 5091060SN/A 5102292SN/A doSquash(tid); 5111858SN/A } 5121060SN/A} 5132877Sksewell@umich.edu 5142292SN/Atemplate <class Impl> 5152292SN/Atypename Impl::DynInstPtr 5166221Snate@binkert.orgROB<Impl>::readHeadInst(ThreadID tid) 5172292SN/A{ 5182292SN/A if (threadEntries[tid] != 0) { 5192292SN/A InstIt head_thread = instList[tid].begin(); 5201060SN/A 5212292SN/A assert((*head_thread)->isInROB()==true); 5221858SN/A 5232292SN/A return *head_thread; 5242292SN/A } else { 5252292SN/A return dummyInst; 5262292SN/A } 5271858SN/A} 5282877Sksewell@umich.edu 5292292SN/Atemplate <class Impl> 5302292SN/Atypename Impl::DynInstPtr 5316221Snate@binkert.orgROB<Impl>::readTailInst(ThreadID tid) 5322292SN/A{ 5332292SN/A InstIt tail_thread = instList[tid].end(); 5342292SN/A tail_thread--; 5352292SN/A 5362292SN/A return *tail_thread; 5372292SN/A} 5382292SN/A 5397897Shestness@cs.utexas.edutemplate <class Impl> 5407897Shestness@cs.utexas.eduvoid 5417897Shestness@cs.utexas.eduROB<Impl>::regStats() 5427897Shestness@cs.utexas.edu{ 5437897Shestness@cs.utexas.edu using namespace Stats; 5447897Shestness@cs.utexas.edu robReads 5457897Shestness@cs.utexas.edu .name(name() + ".rob_reads") 5467897Shestness@cs.utexas.edu .desc("The number of ROB reads"); 5477897Shestness@cs.utexas.edu 5487897Shestness@cs.utexas.edu robWrites 5497897Shestness@cs.utexas.edu .name(name() + ".rob_writes") 5507897Shestness@cs.utexas.edu .desc("The number of ROB writes"); 5517897Shestness@cs.utexas.edu} 5527897Shestness@cs.utexas.edu 5538822Snilay@cs.wisc.edutemplate <class Impl> 5548822Snilay@cs.wisc.edutypename Impl::DynInstPtr 5558822Snilay@cs.wisc.eduROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst) 5568822Snilay@cs.wisc.edu{ 5578822Snilay@cs.wisc.edu for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) { 5588822Snilay@cs.wisc.edu if ((*it)->seqNum == squash_inst) { 5598822Snilay@cs.wisc.edu return *it; 5608822Snilay@cs.wisc.edu } 5618822Snilay@cs.wisc.edu } 5628822Snilay@cs.wisc.edu return NULL; 5638822Snilay@cs.wisc.edu} 564