rob_impl.hh revision 6221
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 326221Snate@binkert.org#include <list> 336221Snate@binkert.org 341858SN/A#include "config/full_system.hh" 351717SN/A#include "cpu/o3/rob.hh" 361060SN/A 376221Snate@binkert.orgusing namespace std; 382292SN/A 391061SN/Atemplate <class Impl> 404329Sktlim@umich.eduROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 412980Sgblack@eecs.umich.edu std::string _smtROBPolicy, unsigned _smtROBThreshold, 426221Snate@binkert.org ThreadID _numThreads) 434329Sktlim@umich.edu : cpu(_cpu), 444329Sktlim@umich.edu numEntries(_numEntries), 451060SN/A squashWidth(_squashWidth), 461060SN/A numInstsInROB(0), 472292SN/A numThreads(_numThreads) 481060SN/A{ 496221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 502877Sksewell@umich.edu squashedSeqNum[tid] = 0; 512292SN/A doneSquashing[tid] = true; 522292SN/A threadEntries[tid] = 0; 532292SN/A } 542292SN/A 552980Sgblack@eecs.umich.edu std::string policy = _smtROBPolicy; 562292SN/A 572292SN/A //Convert string to lowercase 582292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 592292SN/A (int(*)(int)) tolower); 602292SN/A 612292SN/A //Figure out rob policy 622292SN/A if (policy == "dynamic") { 632292SN/A robPolicy = Dynamic; 642292SN/A 652292SN/A //Set Max Entries to Total ROB Capacity 666221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 676221Snate@binkert.org maxEntries[tid] = numEntries; 682292SN/A } 692292SN/A 702292SN/A } else if (policy == "partitioned") { 712292SN/A robPolicy = Partitioned; 724329Sktlim@umich.edu DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n"); 732292SN/A 742292SN/A //@todo:make work if part_amt doesnt divide evenly. 752292SN/A int part_amt = numEntries / numThreads; 762292SN/A 772292SN/A //Divide ROB up evenly 786221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 796221Snate@binkert.org maxEntries[tid] = part_amt; 802292SN/A } 812292SN/A 822292SN/A } else if (policy == "threshold") { 832292SN/A robPolicy = Threshold; 844329Sktlim@umich.edu DPRINTF(Fetch, "ROB sharing policy set to Threshold\n"); 852292SN/A 862292SN/A int threshold = _smtROBThreshold;; 872292SN/A 882292SN/A //Divide up by threshold amount 896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 906221Snate@binkert.org maxEntries[tid] = threshold; 912292SN/A } 922292SN/A } else { 932292SN/A assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic," 942292SN/A "Partitioned, Threshold}"); 952292SN/A } 961060SN/A 972292SN/A // Set the per-thread iterators to the end of the instruction list. 986221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 996221Snate@binkert.org squashIt[tid] = instList[tid].end(); 1002292SN/A } 1011060SN/A 1022292SN/A // Initialize the "universal" ROB head & tail point to invalid 1032292SN/A // pointers 1042292SN/A head = instList[0].end(); 1052292SN/A tail = instList[0].end(); 1062292SN/A} 1072292SN/A 1082292SN/Atemplate <class Impl> 1094329Sktlim@umich.edustd::string 1104329Sktlim@umich.eduROB<Impl>::name() const 1114329Sktlim@umich.edu{ 1124329Sktlim@umich.edu return cpu->name() + ".rob"; 1134329Sktlim@umich.edu} 1144329Sktlim@umich.edu 1154329Sktlim@umich.edutemplate <class Impl> 1162292SN/Avoid 1176221Snate@binkert.orgROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 1182292SN/A{ 1192292SN/A DPRINTF(ROB, "Setting active threads list pointer.\n"); 1202292SN/A activeThreads = at_ptr; 1212292SN/A} 1222292SN/A 1232307SN/Atemplate <class Impl> 1242307SN/Avoid 1252307SN/AROB<Impl>::switchOut() 1262307SN/A{ 1276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1282307SN/A instList[tid].clear(); 1292307SN/A } 1302307SN/A} 1312307SN/A 1322307SN/Atemplate <class Impl> 1332307SN/Avoid 1342307SN/AROB<Impl>::takeOverFrom() 1352307SN/A{ 1366221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1372307SN/A doneSquashing[tid] = true; 1382307SN/A threadEntries[tid] = 0; 1392307SN/A squashIt[tid] = instList[tid].end(); 1402307SN/A } 1412307SN/A numInstsInROB = 0; 1422307SN/A 1432307SN/A // Initialize the "universal" ROB head & tail point to invalid 1442307SN/A // pointers 1452307SN/A head = instList[0].end(); 1462307SN/A tail = instList[0].end(); 1472307SN/A} 1482292SN/A 1492292SN/Atemplate <class Impl> 1502292SN/Avoid 1512292SN/AROB<Impl>::resetEntries() 1522292SN/A{ 1532292SN/A if (robPolicy != Dynamic || numThreads > 1) { 1543867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 1552292SN/A 1566221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 1576221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 1582292SN/A 1593867Sbinkertn@umich.edu while (threads != end) { 1606221Snate@binkert.org ThreadID tid = *threads++; 1613867Sbinkertn@umich.edu 1622292SN/A if (robPolicy == Partitioned) { 1633867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 1642292SN/A } else if (robPolicy == Threshold && active_threads == 1) { 1653867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 1662292SN/A } 1672292SN/A } 1682292SN/A } 1692292SN/A} 1702292SN/A 1712292SN/Atemplate <class Impl> 1722292SN/Aint 1736221Snate@binkert.orgROB<Impl>::entryAmount(ThreadID num_threads) 1742292SN/A{ 1752292SN/A if (robPolicy == Partitioned) { 1762292SN/A return numEntries / num_threads; 1772292SN/A } else { 1782292SN/A return 0; 1792292SN/A } 1801060SN/A} 1811060SN/A 1821061SN/Atemplate <class Impl> 1831060SN/Aint 1841060SN/AROB<Impl>::countInsts() 1851060SN/A{ 1866221Snate@binkert.org int total = 0; 1871061SN/A 1886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 1896221Snate@binkert.org total += countInsts(tid); 1901060SN/A 1912292SN/A return total; 1922292SN/A} 1931060SN/A 1942292SN/Atemplate <class Impl> 1952292SN/Aint 1966221Snate@binkert.orgROB<Impl>::countInsts(ThreadID tid) 1972292SN/A{ 1982292SN/A return instList[tid].size(); 1991060SN/A} 2001060SN/A 2011061SN/Atemplate <class Impl> 2021060SN/Avoid 2031061SN/AROB<Impl>::insertInst(DynInstPtr &inst) 2041060SN/A{ 2052292SN/A //assert(numInstsInROB == countInsts()); 2061060SN/A assert(inst); 2071060SN/A 2082292SN/A DPRINTF(ROB, "Adding inst PC %#x to the ROB.\n", inst->readPC()); 2091060SN/A 2101060SN/A assert(numInstsInROB != numEntries); 2111060SN/A 2126221Snate@binkert.org ThreadID tid = inst->threadNumber; 2131060SN/A 2142292SN/A instList[tid].push_back(inst); 2152292SN/A 2162292SN/A //Set Up head iterator if this is the 1st instruction in the ROB 2172292SN/A if (numInstsInROB == 0) { 2182292SN/A head = instList[tid].begin(); 2192292SN/A assert((*head) == inst); 2201060SN/A } 2211060SN/A 2222292SN/A //Must Decrement for iterator to actually be valid since __.end() 2232292SN/A //actually points to 1 after the last inst 2242292SN/A tail = instList[tid].end(); 2252292SN/A tail--; 2262292SN/A 2272292SN/A inst->setInROB(); 2282292SN/A 2292292SN/A ++numInstsInROB; 2302292SN/A ++threadEntries[tid]; 2312292SN/A 2321060SN/A assert((*tail) == inst); 2331060SN/A 2342292SN/A DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]); 2351060SN/A} 2361060SN/A 2371060SN/A// Whatever calls this function needs to ensure that it properly frees up 2381060SN/A// registers prior to this function. 2392329SN/A/* 2401061SN/Atemplate <class Impl> 2411060SN/Avoid 2421060SN/AROB<Impl>::retireHead() 2431060SN/A{ 2442292SN/A //assert(numInstsInROB == countInsts()); 2452292SN/A assert(numInstsInROB > 0); 2462292SN/A 2476221Snate@binkert.org ThreadID tid = (*head)->threadNumber; 2482292SN/A 2492292SN/A retireHead(tid); 2502292SN/A 2512292SN/A if (numInstsInROB == 0) { 2522292SN/A tail = instList[tid].end(); 2532292SN/A } 2542292SN/A} 2552329SN/A*/ 2562292SN/A 2572292SN/Atemplate <class Impl> 2582292SN/Avoid 2596221Snate@binkert.orgROB<Impl>::retireHead(ThreadID tid) 2602292SN/A{ 2612292SN/A //assert(numInstsInROB == countInsts()); 2621061SN/A assert(numInstsInROB > 0); 2631060SN/A 2641060SN/A // Get the head ROB instruction. 2652292SN/A InstIt head_it = instList[tid].begin(); 2661060SN/A 2672292SN/A DynInstPtr head_inst = (*head_it); 2681858SN/A 2691060SN/A assert(head_inst->readyToCommit()); 2701060SN/A 2712292SN/A DPRINTF(ROB, "[tid:%u]: Retiring head instruction, " 2722292SN/A "instruction PC %#x,[sn:%lli]\n", tid, head_inst->readPC(), 2731060SN/A head_inst->seqNum); 2741060SN/A 2751060SN/A --numInstsInROB; 2762292SN/A --threadEntries[tid]; 2771060SN/A 2782731Sktlim@umich.edu head_inst->clearInROB(); 2792292SN/A head_inst->setCommitted(); 2802292SN/A 2812292SN/A instList[tid].erase(head_it); 2822292SN/A 2832292SN/A //Update "Global" Head of ROB 2842292SN/A updateHead(); 2852292SN/A 2862329SN/A // @todo: A special case is needed if the instruction being 2872329SN/A // retired is the only instruction in the ROB; otherwise the tail 2882329SN/A // iterator will become invalidated. 2891681SN/A cpu->removeFrontInst(head_inst); 2901060SN/A} 2912329SN/A/* 2921061SN/Atemplate <class Impl> 2931060SN/Abool 2941060SN/AROB<Impl>::isHeadReady() 2951060SN/A{ 2961060SN/A if (numInstsInROB != 0) { 2972292SN/A return (*head)->readyToCommit(); 2982292SN/A } 2992292SN/A 3002292SN/A return false; 3012292SN/A} 3022329SN/A*/ 3032292SN/Atemplate <class Impl> 3042292SN/Abool 3056221Snate@binkert.orgROB<Impl>::isHeadReady(ThreadID tid) 3062292SN/A{ 3072292SN/A if (threadEntries[tid] != 0) { 3082292SN/A return instList[tid].front()->readyToCommit(); 3092292SN/A } 3102292SN/A 3112292SN/A return false; 3122292SN/A} 3132292SN/A 3142292SN/Atemplate <class Impl> 3152292SN/Abool 3162292SN/AROB<Impl>::canCommit() 3172292SN/A{ 3182292SN/A //@todo: set ActiveThreads through ROB or CPU 3196221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3206221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3212292SN/A 3223867Sbinkertn@umich.edu while (threads != end) { 3236221Snate@binkert.org ThreadID tid = *threads++; 3242292SN/A 3252292SN/A if (isHeadReady(tid)) { 3262292SN/A return true; 3272292SN/A } 3281060SN/A } 3291060SN/A 3301060SN/A return false; 3311060SN/A} 3321060SN/A 3331061SN/Atemplate <class Impl> 3341060SN/Aunsigned 3351060SN/AROB<Impl>::numFreeEntries() 3361060SN/A{ 3372292SN/A //assert(numInstsInROB == countInsts()); 3381060SN/A 3391060SN/A return numEntries - numInstsInROB; 3401060SN/A} 3411060SN/A 3421061SN/Atemplate <class Impl> 3432292SN/Aunsigned 3446221Snate@binkert.orgROB<Impl>::numFreeEntries(ThreadID tid) 3451060SN/A{ 3462292SN/A return maxEntries[tid] - threadEntries[tid]; 3471060SN/A} 3481060SN/A 3491061SN/Atemplate <class Impl> 3501060SN/Avoid 3516221Snate@binkert.orgROB<Impl>::doSquash(ThreadID tid) 3521060SN/A{ 3532292SN/A DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n", 3542877Sksewell@umich.edu tid, squashedSeqNum[tid]); 3551858SN/A 3562292SN/A assert(squashIt[tid] != instList[tid].end()); 3572292SN/A 3582877Sksewell@umich.edu if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) { 3592292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 3602292SN/A tid); 3612292SN/A 3622292SN/A squashIt[tid] = instList[tid].end(); 3632292SN/A 3642292SN/A doneSquashing[tid] = true; 3652292SN/A return; 3662292SN/A } 3672292SN/A 3682292SN/A bool robTailUpdate = false; 3691858SN/A 3701858SN/A for (int numSquashed = 0; 3712292SN/A numSquashed < squashWidth && 3722292SN/A squashIt[tid] != instList[tid].end() && 3732877Sksewell@umich.edu (*squashIt[tid])->seqNum > squashedSeqNum[tid]; 3741858SN/A ++numSquashed) 3751858SN/A { 3762292SN/A DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %#x, seq num %i.\n", 3772292SN/A (*squashIt[tid])->threadNumber, 3782292SN/A (*squashIt[tid])->readPC(), 3792292SN/A (*squashIt[tid])->seqNum); 3801858SN/A 3811858SN/A // Mark the instruction as squashed, and ready to commit so that 3821858SN/A // it can drain out of the pipeline. 3832292SN/A (*squashIt[tid])->setSquashed(); 3841858SN/A 3852292SN/A (*squashIt[tid])->setCanCommit(); 3861858SN/A 3872292SN/A 3882292SN/A if (squashIt[tid] == instList[tid].begin()) { 3892292SN/A DPRINTF(ROB, "Reached head of instruction list while " 3901858SN/A "squashing.\n"); 3911858SN/A 3922292SN/A squashIt[tid] = instList[tid].end(); 3931858SN/A 3942292SN/A doneSquashing[tid] = true; 3951858SN/A 3961858SN/A return; 3971858SN/A } 3981858SN/A 3992292SN/A InstIt tail_thread = instList[tid].end(); 4002292SN/A tail_thread--; 4012292SN/A 4022292SN/A if ((*squashIt[tid]) == (*tail_thread)) 4032292SN/A robTailUpdate = true; 4042292SN/A 4052292SN/A squashIt[tid]--; 4061858SN/A } 4071858SN/A 4081858SN/A 4091858SN/A // Check if ROB is done squashing. 4102877Sksewell@umich.edu if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) { 4112292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 4122292SN/A tid); 4131858SN/A 4142292SN/A squashIt[tid] = instList[tid].end(); 4151858SN/A 4162292SN/A doneSquashing[tid] = true; 4172292SN/A } 4182292SN/A 4192292SN/A if (robTailUpdate) { 4202292SN/A updateTail(); 4212292SN/A } 4222292SN/A} 4232292SN/A 4242292SN/A 4252292SN/Atemplate <class Impl> 4262292SN/Avoid 4272292SN/AROB<Impl>::updateHead() 4282292SN/A{ 4292292SN/A DynInstPtr head_inst; 4302292SN/A InstSeqNum lowest_num = 0; 4312292SN/A bool first_valid = true; 4322292SN/A 4332292SN/A // @todo: set ActiveThreads through ROB or CPU 4346221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4356221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4362292SN/A 4373867Sbinkertn@umich.edu while (threads != end) { 4386221Snate@binkert.org ThreadID tid = *threads++; 4392292SN/A 4403867Sbinkertn@umich.edu if (instList[tid].empty()) 4412292SN/A continue; 4422292SN/A 4432292SN/A if (first_valid) { 4443867Sbinkertn@umich.edu head = instList[tid].begin(); 4452292SN/A lowest_num = (*head)->seqNum; 4462292SN/A first_valid = false; 4472292SN/A continue; 4482292SN/A } 4492292SN/A 4503867Sbinkertn@umich.edu InstIt head_thread = instList[tid].begin(); 4512292SN/A 4522292SN/A DynInstPtr head_inst = (*head_thread); 4532292SN/A 4542292SN/A assert(head_inst != 0); 4552292SN/A 4562292SN/A if (head_inst->seqNum < lowest_num) { 4572292SN/A head = head_thread; 4582292SN/A lowest_num = head_inst->seqNum; 4592292SN/A } 4602292SN/A } 4612292SN/A 4622292SN/A if (first_valid) { 4632292SN/A head = instList[0].end(); 4642292SN/A } 4652292SN/A 4662292SN/A} 4672292SN/A 4682292SN/Atemplate <class Impl> 4692292SN/Avoid 4702292SN/AROB<Impl>::updateTail() 4712292SN/A{ 4722292SN/A tail = instList[0].end(); 4732292SN/A bool first_valid = true; 4742292SN/A 4756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4772292SN/A 4783867Sbinkertn@umich.edu while (threads != end) { 4796221Snate@binkert.org ThreadID tid = *threads++; 4802292SN/A 4812292SN/A if (instList[tid].empty()) { 4822292SN/A continue; 4832292SN/A } 4842292SN/A 4852292SN/A // If this is the first valid then assign w/out 4862292SN/A // comparison 4872292SN/A if (first_valid) { 4882292SN/A tail = instList[tid].end(); 4892292SN/A tail--; 4902292SN/A first_valid = false; 4912292SN/A continue; 4922292SN/A } 4932292SN/A 4942292SN/A // Assign new tail if this thread's tail is younger 4952292SN/A // than our current "tail high" 4962292SN/A InstIt tail_thread = instList[tid].end(); 4972292SN/A tail_thread--; 4982292SN/A 4992292SN/A if ((*tail_thread)->seqNum > (*tail)->seqNum) { 5002292SN/A tail = tail_thread; 5012292SN/A } 5022292SN/A } 5032292SN/A} 5042292SN/A 5052292SN/A 5062292SN/Atemplate <class Impl> 5072292SN/Avoid 5086221Snate@binkert.orgROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid) 5092292SN/A{ 5102292SN/A if (isEmpty()) { 5112292SN/A DPRINTF(ROB, "Does not need to squash due to being empty " 5122292SN/A "[sn:%i]\n", 5132292SN/A squash_num); 5142292SN/A 5152292SN/A return; 5162292SN/A } 5172292SN/A 5182292SN/A DPRINTF(ROB, "Starting to squash within the ROB.\n"); 5192292SN/A 5202292SN/A robStatus[tid] = ROBSquashing; 5212292SN/A 5222292SN/A doneSquashing[tid] = false; 5231060SN/A 5242877Sksewell@umich.edu squashedSeqNum[tid] = squash_num; 5251060SN/A 5262292SN/A if (!instList[tid].empty()) { 5272292SN/A InstIt tail_thread = instList[tid].end(); 5282292SN/A tail_thread--; 5291060SN/A 5302292SN/A squashIt[tid] = tail_thread; 5311060SN/A 5322292SN/A doSquash(tid); 5331858SN/A } 5341060SN/A} 5352329SN/A/* 5361858SN/Atemplate <class Impl> 5372292SN/Atypename Impl::DynInstPtr 5382292SN/AROB<Impl>::readHeadInst() 5391858SN/A{ 5402292SN/A if (numInstsInROB != 0) { 5412292SN/A assert((*head)->isInROB()==true); 5422292SN/A return *head; 5432292SN/A } else { 5442292SN/A return dummyInst; 5452292SN/A } 5462292SN/A} 5472329SN/A*/ 5482877Sksewell@umich.edu 5492292SN/Atemplate <class Impl> 5502292SN/Atypename Impl::DynInstPtr 5516221Snate@binkert.orgROB<Impl>::readHeadInst(ThreadID tid) 5522292SN/A{ 5532292SN/A if (threadEntries[tid] != 0) { 5542292SN/A InstIt head_thread = instList[tid].begin(); 5551060SN/A 5562292SN/A assert((*head_thread)->isInROB()==true); 5571858SN/A 5582292SN/A return *head_thread; 5592292SN/A } else { 5602292SN/A return dummyInst; 5612292SN/A } 5621858SN/A} 5632877Sksewell@umich.edu 5642329SN/A/* 5651061SN/Atemplate <class Impl> 5661060SN/Auint64_t 5671060SN/AROB<Impl>::readHeadPC() 5681060SN/A{ 5692292SN/A //assert(numInstsInROB == countInsts()); 5701060SN/A 5712292SN/A DynInstPtr head_inst = *head; 5721060SN/A 5731060SN/A return head_inst->readPC(); 5741060SN/A} 5751060SN/A 5761061SN/Atemplate <class Impl> 5771060SN/Auint64_t 5786221Snate@binkert.orgROB<Impl>::readHeadPC(ThreadID tid) 5792292SN/A{ 5802292SN/A //assert(numInstsInROB == countInsts()); 5812292SN/A InstIt head_thread = instList[tid].begin(); 5822292SN/A 5832292SN/A return (*head_thread)->readPC(); 5842292SN/A} 5852292SN/A 5862292SN/A 5872292SN/Atemplate <class Impl> 5882292SN/Auint64_t 5891060SN/AROB<Impl>::readHeadNextPC() 5901060SN/A{ 5912292SN/A //assert(numInstsInROB == countInsts()); 5921060SN/A 5932292SN/A DynInstPtr head_inst = *head; 5941060SN/A 5951060SN/A return head_inst->readNextPC(); 5961060SN/A} 5971060SN/A 5981061SN/Atemplate <class Impl> 5992292SN/Auint64_t 6006221Snate@binkert.orgROB<Impl>::readHeadNextPC(ThreadID tid) 6012292SN/A{ 6022292SN/A //assert(numInstsInROB == countInsts()); 6032292SN/A InstIt head_thread = instList[tid].begin(); 6042292SN/A 6052292SN/A return (*head_thread)->readNextPC(); 6062292SN/A} 6072292SN/A 6082292SN/Atemplate <class Impl> 6091060SN/AInstSeqNum 6101060SN/AROB<Impl>::readHeadSeqNum() 6111060SN/A{ 6122292SN/A //assert(numInstsInROB == countInsts()); 6132292SN/A DynInstPtr head_inst = *head; 6141060SN/A 6151060SN/A return head_inst->seqNum; 6161060SN/A} 6171060SN/A 6181061SN/Atemplate <class Impl> 6192292SN/AInstSeqNum 6206221Snate@binkert.orgROB<Impl>::readHeadSeqNum(ThreadID tid) 6212292SN/A{ 6222292SN/A InstIt head_thread = instList[tid].begin(); 6232292SN/A 6242292SN/A return ((*head_thread)->seqNum); 6252292SN/A} 6262292SN/A 6272292SN/Atemplate <class Impl> 6282292SN/Atypename Impl::DynInstPtr 6292292SN/AROB<Impl>::readTailInst() 6302292SN/A{ 6312292SN/A //assert(numInstsInROB == countInsts()); 6322292SN/A //assert(tail != instList[0].end()); 6332292SN/A 6342292SN/A return (*tail); 6352292SN/A} 6362329SN/A*/ 6372292SN/Atemplate <class Impl> 6382292SN/Atypename Impl::DynInstPtr 6396221Snate@binkert.orgROB<Impl>::readTailInst(ThreadID tid) 6402292SN/A{ 6412292SN/A //assert(tail_thread[tid] != instList[tid].end()); 6422292SN/A 6432292SN/A InstIt tail_thread = instList[tid].end(); 6442292SN/A tail_thread--; 6452292SN/A 6462292SN/A return *tail_thread; 6472292SN/A} 6482292SN/A 6492329SN/A/* 6502292SN/Atemplate <class Impl> 6511060SN/Auint64_t 6521060SN/AROB<Impl>::readTailPC() 6531060SN/A{ 6542292SN/A //assert(numInstsInROB == countInsts()); 6551060SN/A 6562292SN/A //assert(tail != instList[0].end()); 6571060SN/A 6581060SN/A return (*tail)->readPC(); 6591060SN/A} 6601060SN/A 6611061SN/Atemplate <class Impl> 6622292SN/Auint64_t 6636221Snate@binkert.orgROB<Impl>::readTailPC(ThreadID tid) 6642292SN/A{ 6652292SN/A //assert(tail_thread[tid] != instList[tid].end()); 6662292SN/A 6672292SN/A InstIt tail_thread = instList[tid].end(); 6682292SN/A tail_thread--; 6692292SN/A 6702292SN/A return (*tail_thread)->readPC(); 6712292SN/A} 6722292SN/A 6732292SN/Atemplate <class Impl> 6741060SN/AInstSeqNum 6751060SN/AROB<Impl>::readTailSeqNum() 6761060SN/A{ 6771060SN/A // Return the last sequence number that has not been squashed. Other 6781060SN/A // stages can use it to squash any instructions younger than the current 6791060SN/A // tail. 6801060SN/A return (*tail)->seqNum; 6811060SN/A} 6821060SN/A 6832292SN/Atemplate <class Impl> 6842292SN/AInstSeqNum 6856221Snate@binkert.orgROB<Impl>::readTailSeqNum(ThreadID tid) 6862292SN/A{ 6872292SN/A // Return the last sequence number that has not been squashed. Other 6882292SN/A // stages can use it to squash any instructions younger than the current 6892292SN/A // tail. 6902292SN/A // assert(tail_thread[tid] != instList[tid].end()); 6912292SN/A 6922292SN/A InstIt tail_thread = instList[tid].end(); 6932292SN/A tail_thread--; 6942292SN/A 6952292SN/A return (*tail_thread)->seqNum; 6962292SN/A} 6972329SN/A*/ 698