rob_impl.hh revision 1858
111317Sm.alian1369@gmail.com/* 211317Sm.alian1369@gmail.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 311317Sm.alian1369@gmail.com * All rights reserved. 411317Sm.alian1369@gmail.com * 511317Sm.alian1369@gmail.com * Redistribution and use in source and binary forms, with or without 611317Sm.alian1369@gmail.com * modification, are permitted provided that the following conditions are 711317Sm.alian1369@gmail.com * met: redistributions of source code must retain the above copyright 811317Sm.alian1369@gmail.com * notice, this list of conditions and the following disclaimer; 911317Sm.alian1369@gmail.com * redistributions in binary form must reproduce the above copyright 1011317Sm.alian1369@gmail.com * notice, this list of conditions and the following disclaimer in the 1111317Sm.alian1369@gmail.com * documentation and/or other materials provided with the distribution; 1211317Sm.alian1369@gmail.com * neither the name of the copyright holders nor the names of its 1311317Sm.alian1369@gmail.com * contributors may be used to endorse or promote products derived from 1411317Sm.alian1369@gmail.com * this software without specific prior written permission. 1511317Sm.alian1369@gmail.com * 1611317Sm.alian1369@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711317Sm.alian1369@gmail.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811317Sm.alian1369@gmail.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911317Sm.alian1369@gmail.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011317Sm.alian1369@gmail.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111317Sm.alian1369@gmail.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211317Sm.alian1369@gmail.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311317Sm.alian1369@gmail.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411317Sm.alian1369@gmail.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511317Sm.alian1369@gmail.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611317Sm.alian1369@gmail.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711317Sm.alian1369@gmail.com */ 2811317Sm.alian1369@gmail.com 2911317Sm.alian1369@gmail.com#ifndef __CPU_O3_CPU_ROB_IMPL_HH__ 3011317Sm.alian1369@gmail.com#define __CPU_O3_CPU_ROB_IMPL_HH__ 3111317Sm.alian1369@gmail.com 3211317Sm.alian1369@gmail.com#include "config/full_system.hh" 3311317Sm.alian1369@gmail.com#include "cpu/o3/rob.hh" 3411317Sm.alian1369@gmail.com 3511317Sm.alian1369@gmail.comtemplate <class Impl> 3611317Sm.alian1369@gmail.comROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth) 3711317Sm.alian1369@gmail.com : numEntries(_numEntries), 3811317Sm.alian1369@gmail.com squashWidth(_squashWidth), 3911317Sm.alian1369@gmail.com numInstsInROB(0), 4011317Sm.alian1369@gmail.com squashedSeqNum(0) 4111317Sm.alian1369@gmail.com{ 4211317Sm.alian1369@gmail.com doneSquashing = true; 4311317Sm.alian1369@gmail.com} 4411317Sm.alian1369@gmail.com 4511317Sm.alian1369@gmail.comtemplate <class Impl> 4611317Sm.alian1369@gmail.comvoid 4711317Sm.alian1369@gmail.comROB<Impl>::setCPU(FullCPU *cpu_ptr) 4811317Sm.alian1369@gmail.com{ 4911317Sm.alian1369@gmail.com cpu = cpu_ptr; 5011317Sm.alian1369@gmail.com 5111317Sm.alian1369@gmail.com // Set the tail to the beginning of the CPU instruction list so that 5211317Sm.alian1369@gmail.com // upon the first instruction being inserted into the ROB, the tail 5311317Sm.alian1369@gmail.com // iterator can simply be incremented. 5411317Sm.alian1369@gmail.com tail = cpu->instList.begin(); 5511317Sm.alian1369@gmail.com 5611317Sm.alian1369@gmail.com // Set the squash iterator to the end of the instruction list. 5711317Sm.alian1369@gmail.com squashIt = cpu->instList.end(); 5811317Sm.alian1369@gmail.com} 5911317Sm.alian1369@gmail.com 6011317Sm.alian1369@gmail.comtemplate <class Impl> 6111317Sm.alian1369@gmail.comint 6211317Sm.alian1369@gmail.comROB<Impl>::countInsts() 6311317Sm.alian1369@gmail.com{ 6411317Sm.alian1369@gmail.com // Start at 1; if the tail matches cpu->instList.begin(), then there is 6511317Sm.alian1369@gmail.com // one inst in the ROB. 6611317Sm.alian1369@gmail.com int return_val = 1; 6711317Sm.alian1369@gmail.com 6811317Sm.alian1369@gmail.com // There are quite a few special cases. Do not use this function other 6911317Sm.alian1369@gmail.com // than for debugging purposes. 7011317Sm.alian1369@gmail.com if (cpu->instList.begin() == cpu->instList.end()) { 7111317Sm.alian1369@gmail.com // In this case there are no instructions in the list. The ROB 7211317Sm.alian1369@gmail.com // must be empty. 7311317Sm.alian1369@gmail.com return 0; 7411317Sm.alian1369@gmail.com } else if (tail == cpu->instList.end()) { 7511317Sm.alian1369@gmail.com // In this case, the tail is not yet pointing to anything valid. 7611317Sm.alian1369@gmail.com // The ROB must be empty. 7711317Sm.alian1369@gmail.com return 0; 7811317Sm.alian1369@gmail.com } 7911317Sm.alian1369@gmail.com 8011317Sm.alian1369@gmail.com // Iterate through the ROB from the head to the tail, counting the 8111317Sm.alian1369@gmail.com // entries. 8211317Sm.alian1369@gmail.com for (InstIt_t i = cpu->instList.begin(); i != tail; ++i) 8311317Sm.alian1369@gmail.com { 8411317Sm.alian1369@gmail.com assert(i != cpu->instList.end()); 8511317Sm.alian1369@gmail.com ++return_val; 8611317Sm.alian1369@gmail.com } 8711317Sm.alian1369@gmail.com 8811317Sm.alian1369@gmail.com return return_val; 8911317Sm.alian1369@gmail.com 9011317Sm.alian1369@gmail.com // Because the head won't be tracked properly until the ROB gets the 9111317Sm.alian1369@gmail.com // first instruction, and any time that the ROB is empty and has not 9211317Sm.alian1369@gmail.com // yet gotten the instruction, this function doesn't work. 9311317Sm.alian1369@gmail.com// return numInstsInROB; 9411317Sm.alian1369@gmail.com} 9511317Sm.alian1369@gmail.com 9611317Sm.alian1369@gmail.comtemplate <class Impl> 9711317Sm.alian1369@gmail.comvoid 9811317Sm.alian1369@gmail.comROB<Impl>::insertInst(DynInstPtr &inst) 9911317Sm.alian1369@gmail.com{ 10011317Sm.alian1369@gmail.com // Make sure we have the right number of instructions. 10111317Sm.alian1369@gmail.com assert(numInstsInROB == countInsts()); 10211317Sm.alian1369@gmail.com // Make sure the instruction is valid. 10311317Sm.alian1369@gmail.com assert(inst); 10411317Sm.alian1369@gmail.com 10511317Sm.alian1369@gmail.com DPRINTF(ROB, "ROB: Adding inst PC %#x to the ROB.\n", inst->readPC()); 10611317Sm.alian1369@gmail.com 10711317Sm.alian1369@gmail.com // If the ROB is full then exit. 10811317Sm.alian1369@gmail.com assert(numInstsInROB != numEntries); 10911317Sm.alian1369@gmail.com 11011317Sm.alian1369@gmail.com ++numInstsInROB; 11111317Sm.alian1369@gmail.com 11211317Sm.alian1369@gmail.com // Increment the tail iterator, moving it one instruction back. 11311317Sm.alian1369@gmail.com // There is a special case if the ROB was empty prior to this insertion, 11411317Sm.alian1369@gmail.com // in which case the tail will be pointing at instList.end(). If that 11511317Sm.alian1369@gmail.com // happens, then reset the tail to the beginning of the list. 11611317Sm.alian1369@gmail.com if (tail != cpu->instList.end()) { 11711317Sm.alian1369@gmail.com ++tail; 11811317Sm.alian1369@gmail.com } else { 11911317Sm.alian1369@gmail.com tail = cpu->instList.begin(); 12011317Sm.alian1369@gmail.com } 12111317Sm.alian1369@gmail.com 12211317Sm.alian1369@gmail.com // Make sure the tail iterator is actually pointing at the instruction 12311317Sm.alian1369@gmail.com // added. 124 assert((*tail) == inst); 125 126 DPRINTF(ROB, "ROB: Now has %d instructions.\n", numInstsInROB); 127 128} 129 130// Whatever calls this function needs to ensure that it properly frees up 131// registers prior to this function. 132template <class Impl> 133void 134ROB<Impl>::retireHead() 135{ 136 assert(numInstsInROB == countInsts()); 137 assert(numInstsInROB > 0); 138 139 // Get the head ROB instruction. 140 DynInstPtr head_inst = cpu->instList.front(); 141 142 // Make certain this can retire. 143 assert(head_inst->readyToCommit()); 144 145 DPRINTF(ROB, "ROB: Retiring head instruction of the ROB, " 146 "instruction PC %#x, seq num %i\n", head_inst->readPC(), 147 head_inst->seqNum); 148 149 // Keep track of how many instructions are in the ROB. 150 --numInstsInROB; 151 152 // Tell CPU to remove the instruction from the list of instructions. 153 // A special case is needed if the instruction being retired is the 154 // only instruction in the ROB; otherwise the tail iterator will become 155 // invalidated. 156 cpu->removeFrontInst(head_inst); 157 158 if (numInstsInROB == 0) { 159 tail = cpu->instList.end(); 160 } 161} 162 163template <class Impl> 164bool 165ROB<Impl>::isHeadReady() 166{ 167 if (numInstsInROB != 0) { 168 return cpu->instList.front()->readyToCommit(); 169 } 170 171 return false; 172} 173 174template <class Impl> 175unsigned 176ROB<Impl>::numFreeEntries() 177{ 178 assert(numInstsInROB == countInsts()); 179 180 return numEntries - numInstsInROB; 181} 182 183template <class Impl> 184void 185ROB<Impl>::doSquash() 186{ 187 DPRINTF(ROB, "ROB: Squashing instructions.\n"); 188 189 assert(squashIt != cpu->instList.end()); 190 191 for (int numSquashed = 0; 192 numSquashed < squashWidth && (*squashIt)->seqNum != squashedSeqNum; 193 ++numSquashed) 194 { 195 // Ensure that the instruction is younger. 196 assert((*squashIt)->seqNum > squashedSeqNum); 197 198 DPRINTF(ROB, "ROB: Squashing instruction PC %#x, seq num %i.\n", 199 (*squashIt)->readPC(), (*squashIt)->seqNum); 200 201 // Mark the instruction as squashed, and ready to commit so that 202 // it can drain out of the pipeline. 203 (*squashIt)->setSquashed(); 204 205 (*squashIt)->setCanCommit(); 206 207 // Special case for when squashing due to a syscall. It's possible 208 // that the squash happened after the head instruction was already 209 // committed, meaning that (*squashIt)->seqNum != squashedSeqNum 210 // will never be false. Normally the squash would never be able 211 // to go past the head of the ROB; in this case it might, so it 212 // must be handled otherwise it will segfault. 213#if !FULL_SYSTEM 214 if (squashIt == cpu->instList.begin()) { 215 DPRINTF(ROB, "ROB: Reached head of instruction list while " 216 "squashing.\n"); 217 218 squashIt = cpu->instList.end(); 219 220 doneSquashing = true; 221 222 return; 223 } 224#endif 225 226 // Move the tail iterator to the next instruction. 227 squashIt--; 228 } 229 230 231 // Check if ROB is done squashing. 232 if ((*squashIt)->seqNum == squashedSeqNum) { 233 DPRINTF(ROB, "ROB: Done squashing instructions.\n"); 234 235 squashIt = cpu->instList.end(); 236 237 doneSquashing = true; 238 } 239} 240 241template <class Impl> 242void 243ROB<Impl>::squash(InstSeqNum squash_num) 244{ 245 DPRINTF(ROB, "ROB: Starting to squash within the ROB.\n"); 246 doneSquashing = false; 247 248 squashedSeqNum = squash_num; 249 250 assert(tail != cpu->instList.end()); 251 252 squashIt = tail; 253 254 doSquash(); 255} 256 257template <class Impl> 258uint64_t 259ROB<Impl>::readHeadPC() 260{ 261 assert(numInstsInROB == countInsts()); 262 263 DynInstPtr head_inst = cpu->instList.front(); 264 265 return head_inst->readPC(); 266} 267 268template <class Impl> 269uint64_t 270ROB<Impl>::readHeadNextPC() 271{ 272 assert(numInstsInROB == countInsts()); 273 274 DynInstPtr head_inst = cpu->instList.front(); 275 276 return head_inst->readNextPC(); 277} 278 279template <class Impl> 280InstSeqNum 281ROB<Impl>::readHeadSeqNum() 282{ 283 // Return the last sequence number that has not been squashed. Other 284 // stages can use it to squash any instructions younger than the current 285 // tail. 286 DynInstPtr head_inst = cpu->instList.front(); 287 288 return head_inst->seqNum; 289} 290 291template <class Impl> 292uint64_t 293ROB<Impl>::readTailPC() 294{ 295 assert(numInstsInROB == countInsts()); 296 297 assert(tail != cpu->instList.end()); 298 299 return (*tail)->readPC(); 300} 301 302template <class Impl> 303InstSeqNum 304ROB<Impl>::readTailSeqNum() 305{ 306 // Return the last sequence number that has not been squashed. Other 307 // stages can use it to squash any instructions younger than the current 308 // tail. 309 return (*tail)->seqNum; 310} 311 312#endif // __CPU_O3_CPU_ROB_IMPL_HH__ 313