rob_impl.hh revision 13453
13536SN/A/*
211274Sshingarov@labware.com * Copyright (c) 2012 ARM Limited
310595Sgabeblack@google.com * All rights reserved
412109SRekai.GonzalezAlberquilla@arm.com *
57752SWilliam.Wang@arm.com * The license below extends only to copyright in the software and shall
67752SWilliam.Wang@arm.com * not be construed as granting a license to any other intellectual
77752SWilliam.Wang@arm.com * property including but not limited to intellectual property relating
87752SWilliam.Wang@arm.com * to a hardware implementation of the functionality of the software
97752SWilliam.Wang@arm.com * licensed hereunder.  You may use the software subject to the license
107752SWilliam.Wang@arm.com * terms below provided that you ensure that this notice is replicated
117752SWilliam.Wang@arm.com * unmodified and in its entirety in all distributions of the software,
127752SWilliam.Wang@arm.com * modified or unmodified, in source code or in binary form.
137752SWilliam.Wang@arm.com *
147752SWilliam.Wang@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan
157752SWilliam.Wang@arm.com * All rights reserved.
163536SN/A *
173536SN/A * Redistribution and use in source and binary forms, with or without
183536SN/A * modification, are permitted provided that the following conditions are
193536SN/A * met: redistributions of source code must retain the above copyright
203536SN/A * notice, this list of conditions and the following disclaimer;
213536SN/A * redistributions in binary form must reproduce the above copyright
223536SN/A * notice, this list of conditions and the following disclaimer in the
233536SN/A * documentation and/or other materials provided with the distribution;
243536SN/A * neither the name of the copyright holders nor the names of its
253536SN/A * contributors may be used to endorse or promote products derived from
263536SN/A * this software without specific prior written permission.
273536SN/A *
283536SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
293536SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
303536SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
313536SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
323536SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
333536SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
343536SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
353536SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
363536SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
373536SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
383536SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
393536SN/A *
403536SN/A * Authors: Kevin Lim
413536SN/A *          Korey Sewell
423536SN/A */
437752SWilliam.Wang@arm.com
4411274Sshingarov@labware.com#ifndef __CPU_O3_ROB_IMPL_HH__
453536SN/A#define __CPU_O3_ROB_IMPL_HH__
463536SN/A
473536SN/A#include <list>
488332Snate@binkert.org
498332Snate@binkert.org#include "base/logging.hh"
503536SN/A#include "cpu/o3/rob.hh"
513536SN/A#include "debug/Fetch.hh"
523536SN/A#include "debug/ROB.hh"
533536SN/A#include "params/DerivO3CPU.hh"
543536SN/A
553536SN/Ausing namespace std;
563536SN/A
575543SN/Atemplate <class Impl>
585543SN/AROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params)
593536SN/A    : cpu(_cpu),
603536SN/A      numEntries(params->numROBEntries),
613536SN/A      squashWidth(params->squashWidth),
623536SN/A      numInstsInROB(0),
633536SN/A      numThreads(params->numThreads)
643536SN/A{
653536SN/A    std::string policy = params->smtROBPolicy;
663536SN/A
673536SN/A    //Convert string to lowercase
683536SN/A    std::transform(policy.begin(), policy.end(), policy.begin(),
693536SN/A                   (int(*)(int)) tolower);
705543SN/A
715543SN/A    //Figure out rob policy
723536SN/A    if (policy == "dynamic") {
733536SN/A        robPolicy = Dynamic;
743536SN/A
753536SN/A        //Set Max Entries to Total ROB Capacity
763536SN/A        for (ThreadID tid = 0; tid < numThreads; tid++) {
773536SN/A            maxEntries[tid] = numEntries;
783536SN/A        }
793536SN/A
803536SN/A    } else if (policy == "partitioned") {
813536SN/A        robPolicy = Partitioned;
823536SN/A        DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
833536SN/A
843536SN/A        //@todo:make work if part_amt doesnt divide evenly.
853536SN/A        int part_amt = numEntries / numThreads;
863536SN/A
873536SN/A        //Divide ROB up evenly
885543SN/A        for (ThreadID tid = 0; tid < numThreads; tid++) {
893536SN/A            maxEntries[tid] = part_amt;
903536SN/A        }
913536SN/A
923536SN/A    } else if (policy == "threshold") {
933536SN/A        robPolicy = Threshold;
943536SN/A        DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
953536SN/A
963536SN/A        int threshold =  params->smtROBThreshold;;
973536SN/A
983536SN/A        //Divide up by threshold amount
993536SN/A        for (ThreadID tid = 0; tid < numThreads; tid++) {
1003536SN/A            maxEntries[tid] = threshold;
1013536SN/A        }
1023536SN/A    } else {
1033536SN/A        panic("Invalid ROB sharing policy. Options are: Dynamic, "
1043536SN/A                "Partitioned, Threshold");
1053536SN/A    }
1063536SN/A    for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
1073536SN/A        maxEntries[tid] = 0;
1085543SN/A    }
1095543SN/A
1103536SN/A    resetState();
1113536SN/A}
1123536SN/A
1133536SN/Atemplate <class Impl>
1143536SN/Avoid
1153536SN/AROB<Impl>::resetState()
1163536SN/A{
1173536SN/A    for (ThreadID tid = 0; tid  < Impl::MaxThreads; tid++) {
1183536SN/A        threadEntries[tid] = 0;
1193536SN/A        squashIt[tid] = instList[tid].end();
1203536SN/A        squashedSeqNum[tid] = 0;
1213536SN/A        doneSquashing[tid] = true;
1223536SN/A    }
1233536SN/A    numInstsInROB = 0;
1243536SN/A
1253536SN/A    // Initialize the "universal" ROB head & tail point to invalid
1263536SN/A    // pointers
1273536SN/A    head = instList[0].end();
1283536SN/A    tail = instList[0].end();
1293536SN/A}
1303536SN/A
1313536SN/Atemplate <class Impl>
1323536SN/Astd::string
1333536SN/AROB<Impl>::name() const
1343536SN/A{
13511793Sbrandon.potter@amd.com    return cpu->name() + ".rob";
13611793Sbrandon.potter@amd.com}
1373536SN/A
1385569SN/Atemplate <class Impl>
1393536SN/Avoid
1403536SN/AROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
1413536SN/A{
1429020Sgblack@eecs.umich.edu    DPRINTF(ROB, "Setting active threads list pointer.\n");
1438229Snate@binkert.org    activeThreads = at_ptr;
1448229Snate@binkert.org}
14510037SARM gem5 Developers
1467752SWilliam.Wang@arm.comtemplate <class Impl>
1477752SWilliam.Wang@arm.comvoid
14810707SAndreas.Sandberg@ARM.comROB<Impl>::drainSanityCheck() const
1493536SN/A{
1503536SN/A    for (ThreadID tid = 0; tid  < numThreads; tid++)
1513536SN/A        assert(instList[tid].empty());
1523536SN/A    assert(isEmpty());
1538229Snate@binkert.org}
1543536SN/A
1557752SWilliam.Wang@arm.comtemplate <class Impl>
1568232Snate@binkert.orgvoid
1578232Snate@binkert.orgROB<Impl>::takeOverFrom()
1588229Snate@binkert.org{
1593536SN/A    resetState();
1603536SN/A}
1618782Sgblack@eecs.umich.edu
1623536SN/Atemplate <class Impl>
1633536SN/Avoid
1643536SN/AROB<Impl>::resetEntries()
1657752SWilliam.Wang@arm.com{
1663536SN/A    if (robPolicy != Dynamic || numThreads > 1) {
16712449Sgabeblack@google.com        int active_threads = activeThreads->size();
16812449Sgabeblack@google.com
1693536SN/A        list<ThreadID>::iterator threads = activeThreads->begin();
1703536SN/A        list<ThreadID>::iterator end = activeThreads->end();
1713536SN/A
1725569SN/A        while (threads != end) {
1735569SN/A            ThreadID tid = *threads++;
1745569SN/A
1753536SN/A            if (robPolicy == Partitioned) {
1763536SN/A                maxEntries[tid] = numEntries / active_threads;
1773536SN/A            } else if (robPolicy == Threshold && active_threads == 1) {
1788782Sgblack@eecs.umich.edu                maxEntries[tid] = numEntries;
17910707SAndreas.Sandberg@ARM.com            }
18012449Sgabeblack@google.com        }
18110707SAndreas.Sandberg@ARM.com    }
18210707SAndreas.Sandberg@ARM.com}
1838782Sgblack@eecs.umich.edu
18410707SAndreas.Sandberg@ARM.comtemplate <class Impl>
1858782Sgblack@eecs.umich.eduint
1868782Sgblack@eecs.umich.eduROB<Impl>::entryAmount(ThreadID num_threads)
1878782Sgblack@eecs.umich.edu{
1888782Sgblack@eecs.umich.edu    if (robPolicy == Partitioned) {
18912455Sgabeblack@google.com        return numEntries / num_threads;
19012455Sgabeblack@google.com    } else {
19112455Sgabeblack@google.com        return 0;
1928782Sgblack@eecs.umich.edu    }
1933536SN/A}
1943536SN/A
1953536SN/Atemplate <class Impl>
19611274Sshingarov@labware.comint
1973536SN/AROB<Impl>::countInsts()
19811274Sshingarov@labware.com{
1997752SWilliam.Wang@arm.com    int total = 0;
20011274Sshingarov@labware.com
20111274Sshingarov@labware.com    for (ThreadID tid = 0; tid < numThreads; tid++)
20211274Sshingarov@labware.com        total += countInsts(tid);
20311274Sshingarov@labware.com
20411274Sshingarov@labware.com    return total;
2053536SN/A}
20613471Sciro.santilli@arm.com
20713471Sciro.santilli@arm.comtemplate <class Impl>
20813471Sciro.santilli@arm.comint
20913471Sciro.santilli@arm.comROB<Impl>::countInsts(ThreadID tid)
21013471Sciro.santilli@arm.com{
21113471Sciro.santilli@arm.com    return instList[tid].size();
21213471Sciro.santilli@arm.com}
2133536SN/A
2143536SN/Atemplate <class Impl>
2153536SN/Avoid
2163536SN/AROB<Impl>::insertInst(const DynInstPtr &inst)
21711274Sshingarov@labware.com{
2183536SN/A    assert(inst);
21911274Sshingarov@labware.com
2207752SWilliam.Wang@arm.com    robWrites++;
22111274Sshingarov@labware.com
22211274Sshingarov@labware.com    DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState());
22313469Sciro.santilli@arm.com
22413469Sciro.santilli@arm.com    assert(numInstsInROB != numEntries);
22513469Sciro.santilli@arm.com
22611274Sshingarov@labware.com    ThreadID tid = inst->threadNumber;
22711274Sshingarov@labware.com
22811274Sshingarov@labware.com    instList[tid].push_back(inst);
22911274Sshingarov@labware.com
23011274Sshingarov@labware.com    //Set Up head iterator if this is the 1st instruction in the ROB
2317752SWilliam.Wang@arm.com    if (numInstsInROB == 0) {
23213471Sciro.santilli@arm.com        head = instList[tid].begin();
23313471Sciro.santilli@arm.com        assert((*head) == inst);
23413471Sciro.santilli@arm.com    }
23513471Sciro.santilli@arm.com
23613471Sciro.santilli@arm.com    //Must Decrement for iterator to actually be valid  since __.end()
23713471Sciro.santilli@arm.com    //actually points to 1 after the last inst
23813471Sciro.santilli@arm.com    tail = instList[tid].end();
23913471Sciro.santilli@arm.com    tail--;
2403536SN/A
2413536SN/A    inst->setInROB();
2423536SN/A
24311274Sshingarov@labware.com    ++numInstsInROB;
24411274Sshingarov@labware.com    ++threadEntries[tid];
2453536SN/A
24611274Sshingarov@labware.com    assert((*tail) == inst);
24711274Sshingarov@labware.com
24811274Sshingarov@labware.com    DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]);
24911274Sshingarov@labware.com}
25011274Sshingarov@labware.com
25111274Sshingarov@labware.comtemplate <class Impl>
25211274Sshingarov@labware.comvoid
25311274Sshingarov@labware.comROB<Impl>::retireHead(ThreadID tid)
25411274Sshingarov@labware.com{
25511274Sshingarov@labware.com    robWrites++;
25611274Sshingarov@labware.com
25711274Sshingarov@labware.com    assert(numInstsInROB > 0);
25811274Sshingarov@labware.com
25911274Sshingarov@labware.com    // Get the head ROB instruction by copying it and remove it from the list
26011274Sshingarov@labware.com    InstIt head_it = instList[tid].begin();
26111274Sshingarov@labware.com
26211274Sshingarov@labware.com    DynInstPtr head_inst = std::move(*head_it);
26311274Sshingarov@labware.com    instList[tid].erase(head_it);
26411274Sshingarov@labware.com
26511274Sshingarov@labware.com    assert(head_inst->readyToCommit());
26611274Sshingarov@labware.com
26711274Sshingarov@labware.com    DPRINTF(ROB, "[tid:%u]: Retiring head instruction, "
26811274Sshingarov@labware.com            "instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(),
26911274Sshingarov@labware.com            head_inst->seqNum);
2703536SN/A
2713536SN/A    --numInstsInROB;
27211274Sshingarov@labware.com    --threadEntries[tid];
27311274Sshingarov@labware.com
27411274Sshingarov@labware.com    head_inst->clearInROB();
27511274Sshingarov@labware.com    head_inst->setCommitted();
27611274Sshingarov@labware.com
27711274Sshingarov@labware.com    //Update "Global" Head of ROB
27811274Sshingarov@labware.com    updateHead();
27911274Sshingarov@labware.com
28011274Sshingarov@labware.com    // @todo: A special case is needed if the instruction being
28111274Sshingarov@labware.com    // retired is the only instruction in the ROB; otherwise the tail
28211274Sshingarov@labware.com    // iterator will become invalidated.
28311274Sshingarov@labware.com    cpu->removeFrontInst(head_inst);
28411274Sshingarov@labware.com}
28511274Sshingarov@labware.com
28611274Sshingarov@labware.comtemplate <class Impl>
28711274Sshingarov@labware.combool
28811274Sshingarov@labware.comROB<Impl>::isHeadReady(ThreadID tid)
28911274Sshingarov@labware.com{
29011274Sshingarov@labware.com    robReads++;
29111274Sshingarov@labware.com    if (threadEntries[tid] != 0) {
29213469Sciro.santilli@arm.com        return instList[tid].front()->readyToCommit();
29313469Sciro.santilli@arm.com    }
29413469Sciro.santilli@arm.com
29511274Sshingarov@labware.com    return false;
29611274Sshingarov@labware.com}
29711274Sshingarov@labware.com
29811274Sshingarov@labware.comtemplate <class Impl>
29911274Sshingarov@labware.combool
30011274Sshingarov@labware.comROB<Impl>::canCommit()
30111274Sshingarov@labware.com{
30212449Sgabeblack@google.com    //@todo: set ActiveThreads through ROB or CPU
30311274Sshingarov@labware.com    list<ThreadID>::iterator threads = activeThreads->begin();
30411274Sshingarov@labware.com    list<ThreadID>::iterator end = activeThreads->end();
30512449Sgabeblack@google.com
30612221Sshingarov@gmail.com    while (threads != end) {
30712221Sshingarov@gmail.com        ThreadID tid = *threads++;
30812031Sgabeblack@google.com
30911274Sshingarov@labware.com        if (isHeadReady(tid)) {
310            return true;
311        }
312    }
313
314    return false;
315}
316
317template <class Impl>
318unsigned
319ROB<Impl>::numFreeEntries()
320{
321    return numEntries - numInstsInROB;
322}
323
324template <class Impl>
325unsigned
326ROB<Impl>::numFreeEntries(ThreadID tid)
327{
328    return maxEntries[tid] - threadEntries[tid];
329}
330
331template <class Impl>
332void
333ROB<Impl>::doSquash(ThreadID tid)
334{
335    robWrites++;
336    DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n",
337            tid, squashedSeqNum[tid]);
338
339    assert(squashIt[tid] != instList[tid].end());
340
341    if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) {
342        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
343                tid);
344
345        squashIt[tid] = instList[tid].end();
346
347        doneSquashing[tid] = true;
348        return;
349    }
350
351    bool robTailUpdate = false;
352
353    for (int numSquashed = 0;
354         numSquashed < squashWidth &&
355         squashIt[tid] != instList[tid].end() &&
356         (*squashIt[tid])->seqNum > squashedSeqNum[tid];
357         ++numSquashed)
358    {
359        DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq num %i.\n",
360                (*squashIt[tid])->threadNumber,
361                (*squashIt[tid])->pcState(),
362                (*squashIt[tid])->seqNum);
363
364        // Mark the instruction as squashed, and ready to commit so that
365        // it can drain out of the pipeline.
366        (*squashIt[tid])->setSquashed();
367
368        (*squashIt[tid])->setCanCommit();
369
370
371        if (squashIt[tid] == instList[tid].begin()) {
372            DPRINTF(ROB, "Reached head of instruction list while "
373                    "squashing.\n");
374
375            squashIt[tid] = instList[tid].end();
376
377            doneSquashing[tid] = true;
378
379            return;
380        }
381
382        InstIt tail_thread = instList[tid].end();
383        tail_thread--;
384
385        if ((*squashIt[tid]) == (*tail_thread))
386            robTailUpdate = true;
387
388        squashIt[tid]--;
389    }
390
391
392    // Check if ROB is done squashing.
393    if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) {
394        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
395                tid);
396
397        squashIt[tid] = instList[tid].end();
398
399        doneSquashing[tid] = true;
400    }
401
402    if (robTailUpdate) {
403        updateTail();
404    }
405}
406
407
408template <class Impl>
409void
410ROB<Impl>::updateHead()
411{
412    InstSeqNum lowest_num = 0;
413    bool first_valid = true;
414
415    // @todo: set ActiveThreads through ROB or CPU
416    list<ThreadID>::iterator threads = activeThreads->begin();
417    list<ThreadID>::iterator end = activeThreads->end();
418
419    while (threads != end) {
420        ThreadID tid = *threads++;
421
422        if (instList[tid].empty())
423            continue;
424
425        if (first_valid) {
426            head = instList[tid].begin();
427            lowest_num = (*head)->seqNum;
428            first_valid = false;
429            continue;
430        }
431
432        InstIt head_thread = instList[tid].begin();
433
434        DynInstPtr head_inst = (*head_thread);
435
436        assert(head_inst != 0);
437
438        if (head_inst->seqNum < lowest_num) {
439            head = head_thread;
440            lowest_num = head_inst->seqNum;
441        }
442    }
443
444    if (first_valid) {
445        head = instList[0].end();
446    }
447
448}
449
450template <class Impl>
451void
452ROB<Impl>::updateTail()
453{
454    tail = instList[0].end();
455    bool first_valid = true;
456
457    list<ThreadID>::iterator threads = activeThreads->begin();
458    list<ThreadID>::iterator end = activeThreads->end();
459
460    while (threads != end) {
461        ThreadID tid = *threads++;
462
463        if (instList[tid].empty()) {
464            continue;
465        }
466
467        // If this is the first valid then assign w/out
468        // comparison
469        if (first_valid) {
470            tail = instList[tid].end();
471            tail--;
472            first_valid = false;
473            continue;
474        }
475
476        // Assign new tail if this thread's tail is younger
477        // than our current "tail high"
478        InstIt tail_thread = instList[tid].end();
479        tail_thread--;
480
481        if ((*tail_thread)->seqNum > (*tail)->seqNum) {
482            tail = tail_thread;
483        }
484    }
485}
486
487
488template <class Impl>
489void
490ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid)
491{
492    if (isEmpty(tid)) {
493        DPRINTF(ROB, "Does not need to squash due to being empty "
494                "[sn:%i]\n",
495                squash_num);
496
497        return;
498    }
499
500    DPRINTF(ROB, "Starting to squash within the ROB.\n");
501
502    robStatus[tid] = ROBSquashing;
503
504    doneSquashing[tid] = false;
505
506    squashedSeqNum[tid] = squash_num;
507
508    if (!instList[tid].empty()) {
509        InstIt tail_thread = instList[tid].end();
510        tail_thread--;
511
512        squashIt[tid] = tail_thread;
513
514        doSquash(tid);
515    }
516}
517
518template <class Impl>
519const typename Impl::DynInstPtr&
520ROB<Impl>::readHeadInst(ThreadID tid)
521{
522    if (threadEntries[tid] != 0) {
523        InstIt head_thread = instList[tid].begin();
524
525        assert((*head_thread)->isInROB());
526
527        return *head_thread;
528    } else {
529        return dummyInst;
530    }
531}
532
533template <class Impl>
534typename Impl::DynInstPtr
535ROB<Impl>::readTailInst(ThreadID tid)
536{
537    InstIt tail_thread = instList[tid].end();
538    tail_thread--;
539
540    return *tail_thread;
541}
542
543template <class Impl>
544void
545ROB<Impl>::regStats()
546{
547    using namespace Stats;
548    robReads
549        .name(name() + ".rob_reads")
550        .desc("The number of ROB reads");
551
552    robWrites
553        .name(name() + ".rob_writes")
554        .desc("The number of ROB writes");
555}
556
557template <class Impl>
558typename Impl::DynInstPtr
559ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
560{
561    for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) {
562        if ((*it)->seqNum == squash_inst) {
563            return *it;
564        }
565    }
566    return NULL;
567}
568
569#endif//__CPU_O3_ROB_IMPL_HH__
570