rob_impl.hh revision 10164
11689SN/A/*
29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited
39444SAndreas.Sandberg@ARM.com * All rights reserved
49444SAndreas.Sandberg@ARM.com *
59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall
69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual
79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating
89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software
99444SAndreas.Sandberg@ARM.com * licensed hereunder.  You may use the software subject to the license
109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated
119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software,
129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form.
139444SAndreas.Sandberg@ARM.com *
142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
271689SN/A *
281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665Ssaidi@eecs.umich.edu *
402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
412831Sksewell@umich.edu *          Korey Sewell
421689SN/A */
431689SN/A
449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_ROB_IMPL_HH__
459944Smatt.horsnell@ARM.com#define __CPU_O3_ROB_IMPL_HH__
469944Smatt.horsnell@ARM.com
476221Snate@binkert.org#include <list>
486221Snate@binkert.org
491717SN/A#include "cpu/o3/rob.hh"
508232Snate@binkert.org#include "debug/Fetch.hh"
518232Snate@binkert.org#include "debug/ROB.hh"
529954SFaissal.Sleiman@arm.com#include "params/DerivO3CPU.hh"
531060SN/A
546221Snate@binkert.orgusing namespace std;
552292SN/A
561061SN/Atemplate <class Impl>
579954SFaissal.Sleiman@arm.comROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params)
584329Sktlim@umich.edu    : cpu(_cpu),
599954SFaissal.Sleiman@arm.com      numEntries(params->numROBEntries),
609954SFaissal.Sleiman@arm.com      squashWidth(params->squashWidth),
611060SN/A      numInstsInROB(0),
629954SFaissal.Sleiman@arm.com      numThreads(params->numThreads)
631060SN/A{
649954SFaissal.Sleiman@arm.com    std::string policy = params->smtROBPolicy;
652292SN/A
662292SN/A    //Convert string to lowercase
672292SN/A    std::transform(policy.begin(), policy.end(), policy.begin(),
682292SN/A                   (int(*)(int)) tolower);
692292SN/A
702292SN/A    //Figure out rob policy
712292SN/A    if (policy == "dynamic") {
722292SN/A        robPolicy = Dynamic;
732292SN/A
742292SN/A        //Set Max Entries to Total ROB Capacity
756221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
766221Snate@binkert.org            maxEntries[tid] = numEntries;
772292SN/A        }
782292SN/A
792292SN/A    } else if (policy == "partitioned") {
802292SN/A        robPolicy = Partitioned;
814329Sktlim@umich.edu        DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
822292SN/A
832292SN/A        //@todo:make work if part_amt doesnt divide evenly.
842292SN/A        int part_amt = numEntries / numThreads;
852292SN/A
862292SN/A        //Divide ROB up evenly
876221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
886221Snate@binkert.org            maxEntries[tid] = part_amt;
892292SN/A        }
902292SN/A
912292SN/A    } else if (policy == "threshold") {
922292SN/A        robPolicy = Threshold;
934329Sktlim@umich.edu        DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
942292SN/A
959954SFaissal.Sleiman@arm.com        int threshold =  params->smtROBThreshold;;
962292SN/A
972292SN/A        //Divide up by threshold amount
986221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
996221Snate@binkert.org            maxEntries[tid] = threshold;
1002292SN/A        }
1012292SN/A    } else {
1022292SN/A        assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
1032292SN/A                    "Partitioned, Threshold}");
1042292SN/A    }
1051060SN/A
1069444SAndreas.Sandberg@ARM.com    resetState();
1079444SAndreas.Sandberg@ARM.com}
1089444SAndreas.Sandberg@ARM.com
1099444SAndreas.Sandberg@ARM.comtemplate <class Impl>
1109444SAndreas.Sandberg@ARM.comvoid
1119444SAndreas.Sandberg@ARM.comROB<Impl>::resetState()
1129444SAndreas.Sandberg@ARM.com{
1139444SAndreas.Sandberg@ARM.com    for (ThreadID tid = 0; tid  < numThreads; tid++) {
1149444SAndreas.Sandberg@ARM.com        doneSquashing[tid] = true;
1159444SAndreas.Sandberg@ARM.com        threadEntries[tid] = 0;
1166221Snate@binkert.org        squashIt[tid] = instList[tid].end();
1179444SAndreas.Sandberg@ARM.com        squashedSeqNum[tid] = 0;
1182292SN/A    }
1199444SAndreas.Sandberg@ARM.com    numInstsInROB = 0;
1201060SN/A
1212292SN/A    // Initialize the "universal" ROB head & tail point to invalid
1222292SN/A    // pointers
1232292SN/A    head = instList[0].end();
1242292SN/A    tail = instList[0].end();
1252292SN/A}
1262292SN/A
1272292SN/Atemplate <class Impl>
1284329Sktlim@umich.edustd::string
1294329Sktlim@umich.eduROB<Impl>::name() const
1304329Sktlim@umich.edu{
1314329Sktlim@umich.edu    return cpu->name() + ".rob";
1324329Sktlim@umich.edu}
1334329Sktlim@umich.edu
1344329Sktlim@umich.edutemplate <class Impl>
1352292SN/Avoid
1366221Snate@binkert.orgROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
1372292SN/A{
1382292SN/A    DPRINTF(ROB, "Setting active threads list pointer.\n");
1392292SN/A    activeThreads = at_ptr;
1402292SN/A}
1412292SN/A
1422307SN/Atemplate <class Impl>
1432307SN/Avoid
1449444SAndreas.Sandberg@ARM.comROB<Impl>::drainSanityCheck() const
1452307SN/A{
1469444SAndreas.Sandberg@ARM.com    for (ThreadID tid = 0; tid  < numThreads; tid++)
1479444SAndreas.Sandberg@ARM.com        assert(instList[tid].empty());
1489444SAndreas.Sandberg@ARM.com    assert(isEmpty());
1492307SN/A}
1502307SN/A
1512307SN/Atemplate <class Impl>
1522307SN/Avoid
1532307SN/AROB<Impl>::takeOverFrom()
1542307SN/A{
1559444SAndreas.Sandberg@ARM.com    resetState();
1562307SN/A}
1572292SN/A
1582292SN/Atemplate <class Impl>
1592292SN/Avoid
1602292SN/AROB<Impl>::resetEntries()
1612292SN/A{
1622292SN/A    if (robPolicy != Dynamic || numThreads > 1) {
1633867Sbinkertn@umich.edu        int active_threads = activeThreads->size();
1642292SN/A
1656221Snate@binkert.org        list<ThreadID>::iterator threads = activeThreads->begin();
1666221Snate@binkert.org        list<ThreadID>::iterator end = activeThreads->end();
1672292SN/A
1683867Sbinkertn@umich.edu        while (threads != end) {
1696221Snate@binkert.org            ThreadID tid = *threads++;
1703867Sbinkertn@umich.edu
1712292SN/A            if (robPolicy == Partitioned) {
1723867Sbinkertn@umich.edu                maxEntries[tid] = numEntries / active_threads;
1732292SN/A            } else if (robPolicy == Threshold && active_threads == 1) {
1743867Sbinkertn@umich.edu                maxEntries[tid] = numEntries;
1752292SN/A            }
1762292SN/A        }
1772292SN/A    }
1782292SN/A}
1792292SN/A
1802292SN/Atemplate <class Impl>
1812292SN/Aint
1826221Snate@binkert.orgROB<Impl>::entryAmount(ThreadID num_threads)
1832292SN/A{
1842292SN/A    if (robPolicy == Partitioned) {
1852292SN/A        return numEntries / num_threads;
1862292SN/A    } else {
1872292SN/A        return 0;
1882292SN/A    }
1891060SN/A}
1901060SN/A
1911061SN/Atemplate <class Impl>
1921060SN/Aint
1931060SN/AROB<Impl>::countInsts()
1941060SN/A{
1956221Snate@binkert.org    int total = 0;
1961061SN/A
1976221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++)
1986221Snate@binkert.org        total += countInsts(tid);
1991060SN/A
2002292SN/A    return total;
2012292SN/A}
2021060SN/A
2032292SN/Atemplate <class Impl>
2042292SN/Aint
2056221Snate@binkert.orgROB<Impl>::countInsts(ThreadID tid)
2062292SN/A{
2072292SN/A    return instList[tid].size();
2081060SN/A}
2091060SN/A
2101061SN/Atemplate <class Impl>
2111060SN/Avoid
2121061SN/AROB<Impl>::insertInst(DynInstPtr &inst)
2131060SN/A{
2141060SN/A    assert(inst);
2151060SN/A
2167897Shestness@cs.utexas.edu    robWrites++;
2177897Shestness@cs.utexas.edu
2187720Sgblack@eecs.umich.edu    DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState());
2191060SN/A
2201060SN/A    assert(numInstsInROB != numEntries);
2211060SN/A
2226221Snate@binkert.org    ThreadID tid = inst->threadNumber;
2231060SN/A
2242292SN/A    instList[tid].push_back(inst);
2252292SN/A
2262292SN/A    //Set Up head iterator if this is the 1st instruction in the ROB
2272292SN/A    if (numInstsInROB == 0) {
2282292SN/A        head = instList[tid].begin();
2292292SN/A        assert((*head) == inst);
2301060SN/A    }
2311060SN/A
2322292SN/A    //Must Decrement for iterator to actually be valid  since __.end()
2332292SN/A    //actually points to 1 after the last inst
2342292SN/A    tail = instList[tid].end();
2352292SN/A    tail--;
2362292SN/A
2372292SN/A    inst->setInROB();
2382292SN/A
2392292SN/A    ++numInstsInROB;
2402292SN/A    ++threadEntries[tid];
2412292SN/A
2421060SN/A    assert((*tail) == inst);
2431060SN/A
2442292SN/A    DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]);
2451060SN/A}
2461060SN/A
2472292SN/Atemplate <class Impl>
2482292SN/Avoid
2496221Snate@binkert.orgROB<Impl>::retireHead(ThreadID tid)
2502292SN/A{
2517897Shestness@cs.utexas.edu    robWrites++;
2527897Shestness@cs.utexas.edu
2531061SN/A    assert(numInstsInROB > 0);
2541060SN/A
2551060SN/A    // Get the head ROB instruction.
2562292SN/A    InstIt head_it = instList[tid].begin();
2571060SN/A
2582292SN/A    DynInstPtr head_inst = (*head_it);
2591858SN/A
2601060SN/A    assert(head_inst->readyToCommit());
2611060SN/A
2622292SN/A    DPRINTF(ROB, "[tid:%u]: Retiring head instruction, "
2637720Sgblack@eecs.umich.edu            "instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(),
2641060SN/A            head_inst->seqNum);
2651060SN/A
2661060SN/A    --numInstsInROB;
2672292SN/A    --threadEntries[tid];
2681060SN/A
2692731Sktlim@umich.edu    head_inst->clearInROB();
2702292SN/A    head_inst->setCommitted();
2712292SN/A
2722292SN/A    instList[tid].erase(head_it);
2732292SN/A
2742292SN/A    //Update "Global" Head of ROB
2752292SN/A    updateHead();
2762292SN/A
2772329SN/A    // @todo: A special case is needed if the instruction being
2782329SN/A    // retired is the only instruction in the ROB; otherwise the tail
2792329SN/A    // iterator will become invalidated.
2801681SN/A    cpu->removeFrontInst(head_inst);
2811060SN/A}
2822292SN/A
2832292SN/Atemplate <class Impl>
2842292SN/Abool
2856221Snate@binkert.orgROB<Impl>::isHeadReady(ThreadID tid)
2862292SN/A{
2877897Shestness@cs.utexas.edu    robReads++;
2882292SN/A    if (threadEntries[tid] != 0) {
2892292SN/A        return instList[tid].front()->readyToCommit();
2902292SN/A    }
2912292SN/A
2922292SN/A    return false;
2932292SN/A}
2942292SN/A
2952292SN/Atemplate <class Impl>
2962292SN/Abool
2972292SN/AROB<Impl>::canCommit()
2982292SN/A{
2992292SN/A    //@todo: set ActiveThreads through ROB or CPU
3006221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
3016221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
3022292SN/A
3033867Sbinkertn@umich.edu    while (threads != end) {
3046221Snate@binkert.org        ThreadID tid = *threads++;
3052292SN/A
3062292SN/A        if (isHeadReady(tid)) {
3072292SN/A            return true;
3082292SN/A        }
3091060SN/A    }
3101060SN/A
3111060SN/A    return false;
3121060SN/A}
3131060SN/A
3141061SN/Atemplate <class Impl>
3151060SN/Aunsigned
3161060SN/AROB<Impl>::numFreeEntries()
3171060SN/A{
3181060SN/A    return numEntries - numInstsInROB;
3191060SN/A}
3201060SN/A
3211061SN/Atemplate <class Impl>
3222292SN/Aunsigned
3236221Snate@binkert.orgROB<Impl>::numFreeEntries(ThreadID tid)
3241060SN/A{
3252292SN/A    return maxEntries[tid] - threadEntries[tid];
3261060SN/A}
3271060SN/A
3281061SN/Atemplate <class Impl>
3291060SN/Avoid
3306221Snate@binkert.orgROB<Impl>::doSquash(ThreadID tid)
3311060SN/A{
3327897Shestness@cs.utexas.edu    robWrites++;
3332292SN/A    DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n",
3342877Sksewell@umich.edu            tid, squashedSeqNum[tid]);
3351858SN/A
3362292SN/A    assert(squashIt[tid] != instList[tid].end());
3372292SN/A
3382877Sksewell@umich.edu    if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) {
3392292SN/A        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
3402292SN/A                tid);
3412292SN/A
3422292SN/A        squashIt[tid] = instList[tid].end();
3432292SN/A
3442292SN/A        doneSquashing[tid] = true;
3452292SN/A        return;
3462292SN/A    }
3472292SN/A
3482292SN/A    bool robTailUpdate = false;
3491858SN/A
3501858SN/A    for (int numSquashed = 0;
3512292SN/A         numSquashed < squashWidth &&
3522292SN/A         squashIt[tid] != instList[tid].end() &&
3532877Sksewell@umich.edu         (*squashIt[tid])->seqNum > squashedSeqNum[tid];
3541858SN/A         ++numSquashed)
3551858SN/A    {
3567720Sgblack@eecs.umich.edu        DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq num %i.\n",
3572292SN/A                (*squashIt[tid])->threadNumber,
3587720Sgblack@eecs.umich.edu                (*squashIt[tid])->pcState(),
3592292SN/A                (*squashIt[tid])->seqNum);
3601858SN/A
3611858SN/A        // Mark the instruction as squashed, and ready to commit so that
3621858SN/A        // it can drain out of the pipeline.
3632292SN/A        (*squashIt[tid])->setSquashed();
3641858SN/A
3652292SN/A        (*squashIt[tid])->setCanCommit();
3661858SN/A
3672292SN/A
3682292SN/A        if (squashIt[tid] == instList[tid].begin()) {
3692292SN/A            DPRINTF(ROB, "Reached head of instruction list while "
3701858SN/A                    "squashing.\n");
3711858SN/A
3722292SN/A            squashIt[tid] = instList[tid].end();
3731858SN/A
3742292SN/A            doneSquashing[tid] = true;
3751858SN/A
3761858SN/A            return;
3771858SN/A        }
3781858SN/A
3792292SN/A        InstIt tail_thread = instList[tid].end();
3802292SN/A        tail_thread--;
3812292SN/A
3822292SN/A        if ((*squashIt[tid]) == (*tail_thread))
3832292SN/A            robTailUpdate = true;
3842292SN/A
3852292SN/A        squashIt[tid]--;
3861858SN/A    }
3871858SN/A
3881858SN/A
3891858SN/A    // Check if ROB is done squashing.
3902877Sksewell@umich.edu    if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) {
3912292SN/A        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
3922292SN/A                tid);
3931858SN/A
3942292SN/A        squashIt[tid] = instList[tid].end();
3951858SN/A
3962292SN/A        doneSquashing[tid] = true;
3972292SN/A    }
3982292SN/A
3992292SN/A    if (robTailUpdate) {
4002292SN/A        updateTail();
4012292SN/A    }
4022292SN/A}
4032292SN/A
4042292SN/A
4052292SN/Atemplate <class Impl>
4062292SN/Avoid
4072292SN/AROB<Impl>::updateHead()
4082292SN/A{
4092292SN/A    InstSeqNum lowest_num = 0;
4102292SN/A    bool first_valid = true;
4112292SN/A
4122292SN/A    // @todo: set ActiveThreads through ROB or CPU
4136221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
4146221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
4152292SN/A
4163867Sbinkertn@umich.edu    while (threads != end) {
4176221Snate@binkert.org        ThreadID tid = *threads++;
4182292SN/A
4193867Sbinkertn@umich.edu        if (instList[tid].empty())
4202292SN/A            continue;
4212292SN/A
4222292SN/A        if (first_valid) {
4233867Sbinkertn@umich.edu            head = instList[tid].begin();
4242292SN/A            lowest_num = (*head)->seqNum;
4252292SN/A            first_valid = false;
4262292SN/A            continue;
4272292SN/A        }
4282292SN/A
4293867Sbinkertn@umich.edu        InstIt head_thread = instList[tid].begin();
4302292SN/A
4312292SN/A        DynInstPtr head_inst = (*head_thread);
4322292SN/A
4332292SN/A        assert(head_inst != 0);
4342292SN/A
4352292SN/A        if (head_inst->seqNum < lowest_num) {
4362292SN/A            head = head_thread;
4372292SN/A            lowest_num = head_inst->seqNum;
4382292SN/A        }
4392292SN/A    }
4402292SN/A
4412292SN/A    if (first_valid) {
4422292SN/A        head = instList[0].end();
4432292SN/A    }
4442292SN/A
4452292SN/A}
4462292SN/A
4472292SN/Atemplate <class Impl>
4482292SN/Avoid
4492292SN/AROB<Impl>::updateTail()
4502292SN/A{
4512292SN/A    tail = instList[0].end();
4522292SN/A    bool first_valid = true;
4532292SN/A
4546221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
4556221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
4562292SN/A
4573867Sbinkertn@umich.edu    while (threads != end) {
4586221Snate@binkert.org        ThreadID tid = *threads++;
4592292SN/A
4602292SN/A        if (instList[tid].empty()) {
4612292SN/A            continue;
4622292SN/A        }
4632292SN/A
4642292SN/A        // If this is the first valid then assign w/out
4652292SN/A        // comparison
4662292SN/A        if (first_valid) {
4672292SN/A            tail = instList[tid].end();
4682292SN/A            tail--;
4692292SN/A            first_valid = false;
4702292SN/A            continue;
4712292SN/A        }
4722292SN/A
4732292SN/A        // Assign new tail if this thread's tail is younger
4742292SN/A        // than our current "tail high"
4752292SN/A        InstIt tail_thread = instList[tid].end();
4762292SN/A        tail_thread--;
4772292SN/A
4782292SN/A        if ((*tail_thread)->seqNum > (*tail)->seqNum) {
4792292SN/A            tail = tail_thread;
4802292SN/A        }
4812292SN/A    }
4822292SN/A}
4832292SN/A
4842292SN/A
4852292SN/Atemplate <class Impl>
4862292SN/Avoid
4876221Snate@binkert.orgROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid)
4882292SN/A{
48910164Ssleimanf@umich.edu    if (isEmpty(tid)) {
4902292SN/A        DPRINTF(ROB, "Does not need to squash due to being empty "
4912292SN/A                "[sn:%i]\n",
4922292SN/A                squash_num);
4932292SN/A
4942292SN/A        return;
4952292SN/A    }
4962292SN/A
4972292SN/A    DPRINTF(ROB, "Starting to squash within the ROB.\n");
4982292SN/A
4992292SN/A    robStatus[tid] = ROBSquashing;
5002292SN/A
5012292SN/A    doneSquashing[tid] = false;
5021060SN/A
5032877Sksewell@umich.edu    squashedSeqNum[tid] = squash_num;
5041060SN/A
5052292SN/A    if (!instList[tid].empty()) {
5062292SN/A        InstIt tail_thread = instList[tid].end();
5072292SN/A        tail_thread--;
5081060SN/A
5092292SN/A        squashIt[tid] = tail_thread;
5101060SN/A
5112292SN/A        doSquash(tid);
5121858SN/A    }
5131060SN/A}
5142877Sksewell@umich.edu
5152292SN/Atemplate <class Impl>
5162292SN/Atypename Impl::DynInstPtr
5176221Snate@binkert.orgROB<Impl>::readHeadInst(ThreadID tid)
5182292SN/A{
5192292SN/A    if (threadEntries[tid] != 0) {
5202292SN/A        InstIt head_thread = instList[tid].begin();
5211060SN/A
5222292SN/A        assert((*head_thread)->isInROB()==true);
5231858SN/A
5242292SN/A        return *head_thread;
5252292SN/A    } else {
5262292SN/A        return dummyInst;
5272292SN/A    }
5281858SN/A}
5292877Sksewell@umich.edu
5302292SN/Atemplate <class Impl>
5312292SN/Atypename Impl::DynInstPtr
5326221Snate@binkert.orgROB<Impl>::readTailInst(ThreadID tid)
5332292SN/A{
5342292SN/A    InstIt tail_thread = instList[tid].end();
5352292SN/A    tail_thread--;
5362292SN/A
5372292SN/A    return *tail_thread;
5382292SN/A}
5392292SN/A
5407897Shestness@cs.utexas.edutemplate <class Impl>
5417897Shestness@cs.utexas.eduvoid
5427897Shestness@cs.utexas.eduROB<Impl>::regStats()
5437897Shestness@cs.utexas.edu{
5447897Shestness@cs.utexas.edu    using namespace Stats;
5457897Shestness@cs.utexas.edu    robReads
5467897Shestness@cs.utexas.edu        .name(name() + ".rob_reads")
5477897Shestness@cs.utexas.edu        .desc("The number of ROB reads");
5487897Shestness@cs.utexas.edu
5497897Shestness@cs.utexas.edu    robWrites
5507897Shestness@cs.utexas.edu        .name(name() + ".rob_writes")
5517897Shestness@cs.utexas.edu        .desc("The number of ROB writes");
5527897Shestness@cs.utexas.edu}
5537897Shestness@cs.utexas.edu
5548822Snilay@cs.wisc.edutemplate <class Impl>
5558822Snilay@cs.wisc.edutypename Impl::DynInstPtr
5568822Snilay@cs.wisc.eduROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
5578822Snilay@cs.wisc.edu{
5588822Snilay@cs.wisc.edu    for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) {
5598822Snilay@cs.wisc.edu        if ((*it)->seqNum == squash_inst) {
5608822Snilay@cs.wisc.edu            return *it;
5618822Snilay@cs.wisc.edu        }
5628822Snilay@cs.wisc.edu    }
5638822Snilay@cs.wisc.edu    return NULL;
5648822Snilay@cs.wisc.edu}
5659944Smatt.horsnell@ARM.com
5669944Smatt.horsnell@ARM.com#endif//__CPU_O3_ROB_IMPL_HH__
567