rob.hh revision 8822
11897Sstever@eecs.umich.edu/* 24130Ssaidi@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 31897Sstever@eecs.umich.edu * All rights reserved. 41897Sstever@eecs.umich.edu * 51897Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 61897Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 71897Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 81897Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 91897Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 101897Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 111897Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 121897Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 131897Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 141897Sstever@eecs.umich.edu * this software without specific prior written permission. 151897Sstever@eecs.umich.edu * 161897Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171897Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181897Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191897Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201897Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211897Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221897Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231897Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241897Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251897Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261897Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271897Sstever@eecs.umich.edu * 281897Sstever@eecs.umich.edu * Authors: Kevin Lim 291897Sstever@eecs.umich.edu * Korey Sewell 301897Sstever@eecs.umich.edu */ 311897Sstever@eecs.umich.edu 321897Sstever@eecs.umich.edu#ifndef __CPU_O3_ROB_HH__ 331897Sstever@eecs.umich.edu#define __CPU_O3_ROB_HH__ 344961Ssaidi@eecs.umich.edu 351897Sstever@eecs.umich.edu#include <string> 361897Sstever@eecs.umich.edu#include <utility> 371897Sstever@eecs.umich.edu#include <vector> 381897Sstever@eecs.umich.edu 397047Snate@binkert.org#include "arch/registers.hh" 407047Snate@binkert.org#include "base/types.hh" 417047Snate@binkert.org#include "config/the_isa.hh" 427047Snate@binkert.org 437047Snate@binkert.org/** 447047Snate@binkert.org * ROB class. The ROB is largely what drives squashing. 457047Snate@binkert.org */ 467047Snate@binkert.orgtemplate <class Impl> 477047Snate@binkert.orgclass ROB 487735SAli.Saidi@ARM.com{ 497047Snate@binkert.org protected: 507047Snate@binkert.org typedef TheISA::RegIndex RegIndex; 517047Snate@binkert.org public: 527047Snate@binkert.org //Typedefs from the Impl. 537047Snate@binkert.org typedef typename Impl::O3CPU O3CPU; 547047Snate@binkert.org typedef typename Impl::DynInstPtr DynInstPtr; 557047Snate@binkert.org 567047Snate@binkert.org typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 577047Snate@binkert.org typedef typename std::list<DynInstPtr>::iterator InstIt; 587047Snate@binkert.org 597047Snate@binkert.org /** Possible ROB statuses. */ 607047Snate@binkert.org enum Status { 617047Snate@binkert.org Running, 621897Sstever@eecs.umich.edu Idle, 631897Sstever@eecs.umich.edu ROBSquashing 641897Sstever@eecs.umich.edu }; 651897Sstever@eecs.umich.edu 661897Sstever@eecs.umich.edu /** SMT ROB Sharing Policy */ 671897Sstever@eecs.umich.edu enum ROBPolicy{ 681897Sstever@eecs.umich.edu Dynamic, 691897Sstever@eecs.umich.edu Partitioned, 707047Snate@binkert.org Threshold 717047Snate@binkert.org }; 721897Sstever@eecs.umich.edu 731897Sstever@eecs.umich.edu private: 744961Ssaidi@eecs.umich.edu /** Per-thread ROB status. */ 754961Ssaidi@eecs.umich.edu Status robStatus[Impl::MaxThreads]; 764961Ssaidi@eecs.umich.edu 774961Ssaidi@eecs.umich.edu /** ROB resource sharing policy for SMT mode. */ 784961Ssaidi@eecs.umich.edu ROBPolicy robPolicy; 794961Ssaidi@eecs.umich.edu 804961Ssaidi@eecs.umich.edu public: 814961Ssaidi@eecs.umich.edu /** ROB constructor. 824961Ssaidi@eecs.umich.edu * @param _numEntries Number of entries in ROB. 834961Ssaidi@eecs.umich.edu * @param _squashWidth Number of instructions that can be squashed in a 844961Ssaidi@eecs.umich.edu * single cycle. 854961Ssaidi@eecs.umich.edu * @param _smtROBPolicy ROB Partitioning Scheme for SMT. 864961Ssaidi@eecs.umich.edu * @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB. 874961Ssaidi@eecs.umich.edu * @param _numThreads The number of active threads. 881897Sstever@eecs.umich.edu */ 891897Sstever@eecs.umich.edu ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 901897Sstever@eecs.umich.edu std::string smtROBPolicy, unsigned _smtROBThreshold, 911897Sstever@eecs.umich.edu ThreadID _numThreads); 921897Sstever@eecs.umich.edu 931897Sstever@eecs.umich.edu std::string name() const; 941897Sstever@eecs.umich.edu 954961Ssaidi@eecs.umich.edu /** Sets pointer to the list of active threads. 964961Ssaidi@eecs.umich.edu * @param at_ptr Pointer to the list of active threads. 977047Snate@binkert.org */ 984961Ssaidi@eecs.umich.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 994961Ssaidi@eecs.umich.edu 1004961Ssaidi@eecs.umich.edu /** Switches out the ROB. */ 1017047Snate@binkert.org void switchOut(); 1024961Ssaidi@eecs.umich.edu 1034961Ssaidi@eecs.umich.edu /** Takes over another CPU's thread. */ 1044961Ssaidi@eecs.umich.edu void takeOverFrom(); 1054961Ssaidi@eecs.umich.edu 1064961Ssaidi@eecs.umich.edu /** Function to insert an instruction into the ROB. Note that whatever 1074961Ssaidi@eecs.umich.edu * calls this function must ensure that there is enough space within the 1084961Ssaidi@eecs.umich.edu * ROB for the new instruction. 1097047Snate@binkert.org * @param inst The instruction being inserted into the ROB. 1104961Ssaidi@eecs.umich.edu */ 1114961Ssaidi@eecs.umich.edu void insertInst(DynInstPtr &inst); 1124961Ssaidi@eecs.umich.edu 1131897Sstever@eecs.umich.edu /** Returns pointer to the head instruction within the ROB. There is 1147047Snate@binkert.org * no guarantee as to the return value if the ROB is empty. 1157047Snate@binkert.org * @retval Pointer to the DynInst that is at the head of the ROB. 1167047Snate@binkert.org */ 1177047Snate@binkert.org// DynInstPtr readHeadInst(); 1187047Snate@binkert.org 1197047Snate@binkert.org /** Returns a pointer to the head instruction of a specific thread within 1207047Snate@binkert.org * the ROB. 1217047Snate@binkert.org * @return Pointer to the DynInst that is at the head of the ROB. 1227047Snate@binkert.org */ 1237047Snate@binkert.org DynInstPtr readHeadInst(ThreadID tid); 1247047Snate@binkert.org 1257047Snate@binkert.org /** Returns a pointer to the instruction with the given sequence if it is 1267047Snate@binkert.org * in the ROB. 1277047Snate@binkert.org */ 1284961Ssaidi@eecs.umich.edu DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst); 1294961Ssaidi@eecs.umich.edu 1307047Snate@binkert.org /** Returns pointer to the tail instruction within the ROB. There is 1317047Snate@binkert.org * no guarantee as to the return value if the ROB is empty. 1324961Ssaidi@eecs.umich.edu * @retval Pointer to the DynInst that is at the tail of the ROB. 1335247Sstever@gmail.com */ 1345247Sstever@gmail.com// DynInstPtr readTailInst(); 1353725Sstever@eecs.umich.edu 1367047Snate@binkert.org /** Returns a pointer to the tail instruction of a specific thread within 1377047Snate@binkert.org * the ROB. 1387047Snate@binkert.org * @return Pointer to the DynInst that is at the tail of the ROB. 1397047Snate@binkert.org */ 1407047Snate@binkert.org DynInstPtr readTailInst(ThreadID tid); 1417047Snate@binkert.org 142 /** Retires the head instruction, removing it from the ROB. */ 143// void retireHead(); 144 145 /** Retires the head instruction of a specific thread, removing it from the 146 * ROB. 147 */ 148 void retireHead(ThreadID tid); 149 150 /** Is the oldest instruction across all threads ready. */ 151// bool isHeadReady(); 152 153 /** Is the oldest instruction across a particular thread ready. */ 154 bool isHeadReady(ThreadID tid); 155 156 /** Is there any commitable head instruction across all threads ready. */ 157 bool canCommit(); 158 159 /** Re-adjust ROB partitioning. */ 160 void resetEntries(); 161 162 /** Number of entries needed For 'num_threads' amount of threads. */ 163 int entryAmount(ThreadID num_threads); 164 165 /** Returns the number of total free entries in the ROB. */ 166 unsigned numFreeEntries(); 167 168 /** Returns the number of free entries in a specific ROB paritition. */ 169 unsigned numFreeEntries(ThreadID tid); 170 171 /** Returns the maximum number of entries for a specific thread. */ 172 unsigned getMaxEntries(ThreadID tid) 173 { return maxEntries[tid]; } 174 175 /** Returns the number of entries being used by a specific thread. */ 176 unsigned getThreadEntries(ThreadID tid) 177 { return threadEntries[tid]; } 178 179 /** Returns if the ROB is full. */ 180 bool isFull() 181 { return numInstsInROB == numEntries; } 182 183 /** Returns if a specific thread's partition is full. */ 184 bool isFull(ThreadID tid) 185 { return threadEntries[tid] == numEntries; } 186 187 /** Returns if the ROB is empty. */ 188 bool isEmpty() 189 { return numInstsInROB == 0; } 190 191 /** Returns if a specific thread's partition is empty. */ 192 bool isEmpty(ThreadID tid) 193 { return threadEntries[tid] == 0; } 194 195 /** Executes the squash, marking squashed instructions. */ 196 void doSquash(ThreadID tid); 197 198 /** Squashes all instructions younger than the given sequence number for 199 * the specific thread. 200 */ 201 void squash(InstSeqNum squash_num, ThreadID tid); 202 203 /** Updates the head instruction with the new oldest instruction. */ 204 void updateHead(); 205 206 /** Updates the tail instruction with the new youngest instruction. */ 207 void updateTail(); 208 209 /** Reads the PC of the oldest head instruction. */ 210// uint64_t readHeadPC(); 211 212 /** Reads the PC of the head instruction of a specific thread. */ 213// uint64_t readHeadPC(ThreadID tid); 214 215 /** Reads the next PC of the oldest head instruction. */ 216// uint64_t readHeadNextPC(); 217 218 /** Reads the next PC of the head instruction of a specific thread. */ 219// uint64_t readHeadNextPC(ThreadID tid); 220 221 /** Reads the sequence number of the oldest head instruction. */ 222// InstSeqNum readHeadSeqNum(); 223 224 /** Reads the sequence number of the head instruction of a specific thread. 225 */ 226// InstSeqNum readHeadSeqNum(ThreadID tid); 227 228 /** Reads the PC of the youngest tail instruction. */ 229// uint64_t readTailPC(); 230 231 /** Reads the PC of the tail instruction of a specific thread. */ 232// uint64_t readTailPC(ThreadID tid); 233 234 /** Reads the sequence number of the youngest tail instruction. */ 235// InstSeqNum readTailSeqNum(); 236 237 /** Reads the sequence number of tail instruction of a specific thread. */ 238// InstSeqNum readTailSeqNum(ThreadID tid); 239 240 /** Checks if the ROB is still in the process of squashing instructions. 241 * @retval Whether or not the ROB is done squashing. 242 */ 243 bool isDoneSquashing(ThreadID tid) const 244 { return doneSquashing[tid]; } 245 246 /** Checks if the ROB is still in the process of squashing instructions for 247 * any thread. 248 */ 249 bool isDoneSquashing(); 250 251 /** This is more of a debugging function than anything. Use 252 * numInstsInROB to get the instructions in the ROB unless you are 253 * double checking that variable. 254 */ 255 int countInsts(); 256 257 /** This is more of a debugging function than anything. Use 258 * threadEntries to get the instructions in the ROB unless you are 259 * double checking that variable. 260 */ 261 int countInsts(ThreadID tid); 262 263 /** Registers statistics. */ 264 void regStats(); 265 266 private: 267 /** Pointer to the CPU. */ 268 O3CPU *cpu; 269 270 /** Active Threads in CPU */ 271 std::list<ThreadID> *activeThreads; 272 273 /** Number of instructions in the ROB. */ 274 unsigned numEntries; 275 276 /** Entries Per Thread */ 277 unsigned threadEntries[Impl::MaxThreads]; 278 279 /** Max Insts a Thread Can Have in the ROB */ 280 unsigned maxEntries[Impl::MaxThreads]; 281 282 /** ROB List of Instructions */ 283 std::list<DynInstPtr> instList[Impl::MaxThreads]; 284 285 /** Number of instructions that can be squashed in a single cycle. */ 286 unsigned squashWidth; 287 288 public: 289 /** Iterator pointing to the instruction which is the last instruction 290 * in the ROB. This may at times be invalid (ie when the ROB is empty), 291 * however it should never be incorrect. 292 */ 293 InstIt tail; 294 295 /** Iterator pointing to the instruction which is the first instruction in 296 * in the ROB*/ 297 InstIt head; 298 299 private: 300 /** Iterator used for walking through the list of instructions when 301 * squashing. Used so that there is persistent state between cycles; 302 * when squashing, the instructions are marked as squashed but not 303 * immediately removed, meaning the tail iterator remains the same before 304 * and after a squash. 305 * This will always be set to cpu->instList.end() if it is invalid. 306 */ 307 InstIt squashIt[Impl::MaxThreads]; 308 309 public: 310 /** Number of instructions in the ROB. */ 311 int numInstsInROB; 312 313 /** Dummy instruction returned if there are no insts left. */ 314 DynInstPtr dummyInst; 315 316 private: 317 /** The sequence number of the squashed instruction. */ 318 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 319 320 /** Is the ROB done squashing. */ 321 bool doneSquashing[Impl::MaxThreads]; 322 323 /** Number of active threads. */ 324 ThreadID numThreads; 325 326 // The number of rob_reads 327 Stats::Scalar robReads; 328 // The number of rob_writes 329 Stats::Scalar robWrites; 330}; 331 332#endif //__CPU_O3_ROB_HH__ 333