rob.hh revision 13562:8fe39a3fc056
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2012 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Kevin Lim 416735Sgblack@eecs.umich.edu * Korey Sewell 426735Sgblack@eecs.umich.edu */ 436019Shines@cs.fsu.edu 446019Shines@cs.fsu.edu#ifndef __CPU_O3_ROB_HH__ 456019Shines@cs.fsu.edu#define __CPU_O3_ROB_HH__ 468229Snate@binkert.org 478229Snate@binkert.org#include <string> 486019Shines@cs.fsu.edu#include <utility> 496019Shines@cs.fsu.edu#include <vector> 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.edu#include "arch/registers.hh" 526019Shines@cs.fsu.edu#include "base/types.hh" 537362Sgblack@eecs.umich.edu#include "config/the_isa.hh" 546735Sgblack@eecs.umich.edu#include "enums/SMTQueuePolicy.hh" 556019Shines@cs.fsu.edu 567362Sgblack@eecs.umich.edustruct DerivO3CPUParams; 576735Sgblack@eecs.umich.edu 586019Shines@cs.fsu.edu/** 597362Sgblack@eecs.umich.edu * ROB class. The ROB is largely what drives squashing. 606735Sgblack@eecs.umich.edu */ 616019Shines@cs.fsu.edutemplate <class Impl> 627362Sgblack@eecs.umich.educlass ROB 636735Sgblack@eecs.umich.edu{ 646019Shines@cs.fsu.edu public: 657362Sgblack@eecs.umich.edu //Typedefs from the Impl. 666735Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 676019Shines@cs.fsu.edu typedef typename Impl::DynInstPtr DynInstPtr; 687362Sgblack@eecs.umich.edu 696735Sgblack@eecs.umich.edu typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 706019Shines@cs.fsu.edu typedef typename std::list<DynInstPtr>::iterator InstIt; 717362Sgblack@eecs.umich.edu 726735Sgblack@eecs.umich.edu /** Possible ROB statuses. */ 736019Shines@cs.fsu.edu enum Status { 747652Sminkyu.jeong@arm.com Running, 757652Sminkyu.jeong@arm.com Idle, 767652Sminkyu.jeong@arm.com ROBSquashing 778202SAli.Saidi@ARM.com }; 788202SAli.Saidi@ARM.com 798202SAli.Saidi@ARM.com private: 806735Sgblack@eecs.umich.edu /** Per-thread ROB status. */ 817362Sgblack@eecs.umich.edu Status robStatus[Impl::MaxThreads]; 826735Sgblack@eecs.umich.edu 836735Sgblack@eecs.umich.edu /** ROB resource sharing policy for SMT mode. */ 846019Shines@cs.fsu.edu SMTQueuePolicy robPolicy; 856735Sgblack@eecs.umich.edu 867400SAli.Saidi@ARM.com public: 876735Sgblack@eecs.umich.edu /** ROB constructor. 886735Sgblack@eecs.umich.edu * @param _cpu The cpu object pointer. 896735Sgblack@eecs.umich.edu * @param params The cpu params including several ROB-specific parameters. 907400SAli.Saidi@ARM.com */ 916735Sgblack@eecs.umich.edu ROB(O3CPU *_cpu, DerivO3CPUParams *params); 926735Sgblack@eecs.umich.edu 936735Sgblack@eecs.umich.edu std::string name() const; 946019Shines@cs.fsu.edu 956019Shines@cs.fsu.edu /** Sets pointer to the list of active threads. 966019Shines@cs.fsu.edu * @param at_ptr Pointer to the list of active threads. 976735Sgblack@eecs.umich.edu */ 986735Sgblack@eecs.umich.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 996735Sgblack@eecs.umich.edu 1007678Sgblack@eecs.umich.edu /** Perform sanity checks after a drain. */ 1016019Shines@cs.fsu.edu void drainSanityCheck() const; 1026735Sgblack@eecs.umich.edu 1036735Sgblack@eecs.umich.edu /** Takes over another CPU's thread. */ 1046735Sgblack@eecs.umich.edu void takeOverFrom(); 1056019Shines@cs.fsu.edu 1066735Sgblack@eecs.umich.edu /** Function to insert an instruction into the ROB. Note that whatever 1076735Sgblack@eecs.umich.edu * calls this function must ensure that there is enough space within the 1086735Sgblack@eecs.umich.edu * ROB for the new instruction. 1096735Sgblack@eecs.umich.edu * @param inst The instruction being inserted into the ROB. 1107720Sgblack@eecs.umich.edu */ 1118205SAli.Saidi@ARM.com void insertInst(const DynInstPtr &inst); 1128205SAli.Saidi@ARM.com 1138205SAli.Saidi@ARM.com /** Returns pointer to the head instruction within the ROB. There is 1146735Sgblack@eecs.umich.edu * no guarantee as to the return value if the ROB is empty. 1156735Sgblack@eecs.umich.edu * @retval Pointer to the DynInst that is at the head of the ROB. 1166735Sgblack@eecs.umich.edu */ 1176735Sgblack@eecs.umich.edu// DynInstPtr readHeadInst(); 1186735Sgblack@eecs.umich.edu 1197093Sgblack@eecs.umich.edu /** Returns a pointer to the head instruction of a specific thread within 1206735Sgblack@eecs.umich.edu * the ROB. 1216735Sgblack@eecs.umich.edu * @return Pointer to the DynInst that is at the head of the ROB. 1226735Sgblack@eecs.umich.edu */ 1237302Sgblack@eecs.umich.edu const DynInstPtr &readHeadInst(ThreadID tid); 1246735Sgblack@eecs.umich.edu 1257720Sgblack@eecs.umich.edu /** Returns a pointer to the instruction with the given sequence if it is 1266735Sgblack@eecs.umich.edu * in the ROB. 1276735Sgblack@eecs.umich.edu */ 1286735Sgblack@eecs.umich.edu DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst); 1296735Sgblack@eecs.umich.edu 1306735Sgblack@eecs.umich.edu /** Returns pointer to the tail instruction within the ROB. There is 1316735Sgblack@eecs.umich.edu * no guarantee as to the return value if the ROB is empty. 1326735Sgblack@eecs.umich.edu * @retval Pointer to the DynInst that is at the tail of the ROB. 1336735Sgblack@eecs.umich.edu */ 1346735Sgblack@eecs.umich.edu// DynInstPtr readTailInst(); 1356735Sgblack@eecs.umich.edu 1366735Sgblack@eecs.umich.edu /** Returns a pointer to the tail instruction of a specific thread within 1376735Sgblack@eecs.umich.edu * the ROB. 1386735Sgblack@eecs.umich.edu * @return Pointer to the DynInst that is at the tail of the ROB. 1396735Sgblack@eecs.umich.edu */ 1406735Sgblack@eecs.umich.edu DynInstPtr readTailInst(ThreadID tid); 1416735Sgblack@eecs.umich.edu 1426735Sgblack@eecs.umich.edu /** Retires the head instruction, removing it from the ROB. */ 1436735Sgblack@eecs.umich.edu// void retireHead(); 1446735Sgblack@eecs.umich.edu 1456735Sgblack@eecs.umich.edu /** Retires the head instruction of a specific thread, removing it from the 1467093Sgblack@eecs.umich.edu * ROB. 1477093Sgblack@eecs.umich.edu */ 1487720Sgblack@eecs.umich.edu void retireHead(ThreadID tid); 1497585SAli.Saidi@arm.com 1507720Sgblack@eecs.umich.edu /** Is the oldest instruction across all threads ready. */ 1517720Sgblack@eecs.umich.edu// bool isHeadReady(); 1527720Sgblack@eecs.umich.edu 1537720Sgblack@eecs.umich.edu /** Is the oldest instruction across a particular thread ready. */ 1547720Sgblack@eecs.umich.edu bool isHeadReady(ThreadID tid); 1557720Sgblack@eecs.umich.edu 1567720Sgblack@eecs.umich.edu /** Is there any commitable head instruction across all threads ready. */ 1576019Shines@cs.fsu.edu bool canCommit(); 1587189Sgblack@eecs.umich.edu 1597400SAli.Saidi@ARM.com /** Re-adjust ROB partitioning. */ 1607678Sgblack@eecs.umich.edu void resetEntries(); 1617400SAli.Saidi@ARM.com 1627400SAli.Saidi@ARM.com /** Number of entries needed For 'num_threads' amount of threads. */ 1637400SAli.Saidi@ARM.com int entryAmount(ThreadID num_threads); 1648205SAli.Saidi@ARM.com 1657400SAli.Saidi@ARM.com /** Returns the number of total free entries in the ROB. */ 1667400SAli.Saidi@ARM.com unsigned numFreeEntries(); 1677189Sgblack@eecs.umich.edu 1687189Sgblack@eecs.umich.edu /** Returns the number of free entries in a specific ROB paritition. */ 1697189Sgblack@eecs.umich.edu unsigned numFreeEntries(ThreadID tid); 1707678Sgblack@eecs.umich.edu 1717189Sgblack@eecs.umich.edu /** Returns the maximum number of entries for a specific thread. */ 1727640Sgblack@eecs.umich.edu unsigned getMaxEntries(ThreadID tid) 1737189Sgblack@eecs.umich.edu { return maxEntries[tid]; } 1747640Sgblack@eecs.umich.edu 1757640Sgblack@eecs.umich.edu /** Returns the number of entries being used by a specific thread. */ 1767640Sgblack@eecs.umich.edu unsigned getThreadEntries(ThreadID tid) 1777640Sgblack@eecs.umich.edu { return threadEntries[tid]; } 1787426Sgblack@eecs.umich.edu 1797426Sgblack@eecs.umich.edu /** Returns if the ROB is full. */ 1807189Sgblack@eecs.umich.edu bool isFull() 1817426Sgblack@eecs.umich.edu { return numInstsInROB == numEntries; } 1827426Sgblack@eecs.umich.edu 1837189Sgblack@eecs.umich.edu /** Returns if a specific thread's partition is full. */ 1847189Sgblack@eecs.umich.edu bool isFull(ThreadID tid) 1857189Sgblack@eecs.umich.edu { return threadEntries[tid] == numEntries; } 1867197Sgblack@eecs.umich.edu 1877678Sgblack@eecs.umich.edu /** Returns if the ROB is empty. */ 1887197Sgblack@eecs.umich.edu bool isEmpty() const 1897197Sgblack@eecs.umich.edu { return numInstsInROB == 0; } 1907197Sgblack@eecs.umich.edu 1917197Sgblack@eecs.umich.edu /** Returns if a specific thread's partition is empty. */ 1928063SAli.Saidi@ARM.com bool isEmpty(ThreadID tid) const 1937197Sgblack@eecs.umich.edu { return threadEntries[tid] == 0; } 1947197Sgblack@eecs.umich.edu 1957197Sgblack@eecs.umich.edu /** Executes the squash, marking squashed instructions. */ 1967720Sgblack@eecs.umich.edu void doSquash(ThreadID tid); 1977720Sgblack@eecs.umich.edu 1987720Sgblack@eecs.umich.edu /** Squashes all instructions younger than the given sequence number for 1997720Sgblack@eecs.umich.edu * the specific thread. 2007197Sgblack@eecs.umich.edu */ 2017197Sgblack@eecs.umich.edu void squash(InstSeqNum squash_num, ThreadID tid); 2026019Shines@cs.fsu.edu 2036019Shines@cs.fsu.edu /** Updates the head instruction with the new oldest instruction. */ 2047362Sgblack@eecs.umich.edu void updateHead(); 2057362Sgblack@eecs.umich.edu 2067678Sgblack@eecs.umich.edu /** Updates the tail instruction with the new youngest instruction. */ 2077362Sgblack@eecs.umich.edu void updateTail(); 2088205SAli.Saidi@ARM.com 2097362Sgblack@eecs.umich.edu /** Reads the PC of the oldest head instruction. */ 2107362Sgblack@eecs.umich.edu// uint64_t readHeadPC(); 2117362Sgblack@eecs.umich.edu 2127362Sgblack@eecs.umich.edu /** Reads the PC of the head instruction of a specific thread. */ 2137362Sgblack@eecs.umich.edu// uint64_t readHeadPC(ThreadID tid); 2147362Sgblack@eecs.umich.edu 2157362Sgblack@eecs.umich.edu /** Reads the next PC of the oldest head instruction. */ 2167362Sgblack@eecs.umich.edu// uint64_t readHeadNextPC(); 2177362Sgblack@eecs.umich.edu 2187362Sgblack@eecs.umich.edu /** Reads the next PC of the head instruction of a specific thread. */ 2197652Sminkyu.jeong@arm.com// uint64_t readHeadNextPC(ThreadID tid); 2207678Sgblack@eecs.umich.edu 2217652Sminkyu.jeong@arm.com /** Reads the sequence number of the oldest head instruction. */ 2227652Sminkyu.jeong@arm.com// InstSeqNum readHeadSeqNum(); 2237652Sminkyu.jeong@arm.com 2247652Sminkyu.jeong@arm.com /** Reads the sequence number of the head instruction of a specific thread. 2257652Sminkyu.jeong@arm.com */ 2267720Sgblack@eecs.umich.edu// InstSeqNum readHeadSeqNum(ThreadID tid); 2277720Sgblack@eecs.umich.edu 2287720Sgblack@eecs.umich.edu /** Reads the PC of the youngest tail instruction. */ 2297720Sgblack@eecs.umich.edu// uint64_t readTailPC(); 2307652Sminkyu.jeong@arm.com 2317652Sminkyu.jeong@arm.com /** Reads the PC of the tail instruction of a specific thread. */ 2328202SAli.Saidi@ARM.com// uint64_t readTailPC(ThreadID tid); 2338202SAli.Saidi@ARM.com 2348202SAli.Saidi@ARM.com /** Reads the sequence number of the youngest tail instruction. */ 2358202SAli.Saidi@ARM.com// InstSeqNum readTailSeqNum(); 2368202SAli.Saidi@ARM.com 2378202SAli.Saidi@ARM.com /** Reads the sequence number of tail instruction of a specific thread. */ 2388202SAli.Saidi@ARM.com// InstSeqNum readTailSeqNum(ThreadID tid); 2398202SAli.Saidi@ARM.com 2408202SAli.Saidi@ARM.com /** Checks if the ROB is still in the process of squashing instructions. 2418202SAli.Saidi@ARM.com * @retval Whether or not the ROB is done squashing. 2428202SAli.Saidi@ARM.com */ 2437678Sgblack@eecs.umich.edu bool isDoneSquashing(ThreadID tid) const 2447678Sgblack@eecs.umich.edu { return doneSquashing[tid]; } 2457678Sgblack@eecs.umich.edu 2467678Sgblack@eecs.umich.edu /** Checks if the ROB is still in the process of squashing instructions for 2477362Sgblack@eecs.umich.edu * any thread. 2486735Sgblack@eecs.umich.edu */ 2496019Shines@cs.fsu.edu bool isDoneSquashing(); 2506019Shines@cs.fsu.edu 251 /** This is more of a debugging function than anything. Use 252 * numInstsInROB to get the instructions in the ROB unless you are 253 * double checking that variable. 254 */ 255 int countInsts(); 256 257 /** This is more of a debugging function than anything. Use 258 * threadEntries to get the instructions in the ROB unless you are 259 * double checking that variable. 260 */ 261 int countInsts(ThreadID tid); 262 263 /** Registers statistics. */ 264 void regStats(); 265 266 private: 267 /** Reset the ROB state */ 268 void resetState(); 269 270 /** Pointer to the CPU. */ 271 O3CPU *cpu; 272 273 /** Active Threads in CPU */ 274 std::list<ThreadID> *activeThreads; 275 276 /** Number of instructions in the ROB. */ 277 unsigned numEntries; 278 279 /** Entries Per Thread */ 280 unsigned threadEntries[Impl::MaxThreads]; 281 282 /** Max Insts a Thread Can Have in the ROB */ 283 unsigned maxEntries[Impl::MaxThreads]; 284 285 /** ROB List of Instructions */ 286 std::list<DynInstPtr> instList[Impl::MaxThreads]; 287 288 /** Number of instructions that can be squashed in a single cycle. */ 289 unsigned squashWidth; 290 291 public: 292 /** Iterator pointing to the instruction which is the last instruction 293 * in the ROB. This may at times be invalid (ie when the ROB is empty), 294 * however it should never be incorrect. 295 */ 296 InstIt tail; 297 298 /** Iterator pointing to the instruction which is the first instruction in 299 * in the ROB*/ 300 InstIt head; 301 302 private: 303 /** Iterator used for walking through the list of instructions when 304 * squashing. Used so that there is persistent state between cycles; 305 * when squashing, the instructions are marked as squashed but not 306 * immediately removed, meaning the tail iterator remains the same before 307 * and after a squash. 308 * This will always be set to cpu->instList.end() if it is invalid. 309 */ 310 InstIt squashIt[Impl::MaxThreads]; 311 312 public: 313 /** Number of instructions in the ROB. */ 314 int numInstsInROB; 315 316 /** Dummy instruction returned if there are no insts left. */ 317 DynInstPtr dummyInst; 318 319 private: 320 /** The sequence number of the squashed instruction. */ 321 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 322 323 /** Is the ROB done squashing. */ 324 bool doneSquashing[Impl::MaxThreads]; 325 326 /** Number of active threads. */ 327 ThreadID numThreads; 328 329 // The number of rob_reads 330 Stats::Scalar robReads; 331 // The number of rob_writes 332 Stats::Scalar robWrites; 333}; 334 335#endif //__CPU_O3_ROB_HH__ 336