rob.hh revision 9954 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#ifndef __CPU_O3_ROB_HH__
45#define __CPU_O3_ROB_HH__
46
47#include <string>
48#include <utility>
49#include <vector>
50
51#include "arch/registers.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54
55struct DerivO3CPUParams;
56
57/**
58 * ROB class.  The ROB is largely what drives squashing.
59 */
60template <class Impl>
61class ROB
62{
63  protected:
64    typedef TheISA::RegIndex RegIndex;
65  public:
66    //Typedefs from the Impl.
67    typedef typename Impl::O3CPU O3CPU;
68    typedef typename Impl::DynInstPtr DynInstPtr;
69
70    typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
71    typedef typename std::list<DynInstPtr>::iterator InstIt;
72
73    /** Possible ROB statuses. */
74    enum Status {
75        Running,
76        Idle,
77        ROBSquashing
78    };
79
80    /** SMT ROB Sharing Policy */
81    enum ROBPolicy{
82        Dynamic,
83        Partitioned,
84        Threshold
85    };
86
87  private:
88    /** Per-thread ROB status. */
89    Status robStatus[Impl::MaxThreads];
90
91    /** ROB resource sharing policy for SMT mode. */
92    ROBPolicy robPolicy;
93
94  public:
95    /** ROB constructor.
96     *  @param _cpu   The cpu object pointer.
97     *  @param params The cpu params including several ROB-specific parameters.
98     */
99    ROB(O3CPU *_cpu, DerivO3CPUParams *params);
100
101    std::string name() const;
102
103    /** Sets pointer to the list of active threads.
104     *  @param at_ptr Pointer to the list of active threads.
105     */
106    void setActiveThreads(std::list<ThreadID> *at_ptr);
107
108    /** Perform sanity checks after a drain. */
109    void drainSanityCheck() const;
110
111    /** Takes over another CPU's thread. */
112    void takeOverFrom();
113
114    /** Function to insert an instruction into the ROB. Note that whatever
115     *  calls this function must ensure that there is enough space within the
116     *  ROB for the new instruction.
117     *  @param inst The instruction being inserted into the ROB.
118     */
119    void insertInst(DynInstPtr &inst);
120
121    /** Returns pointer to the head instruction within the ROB.  There is
122     *  no guarantee as to the return value if the ROB is empty.
123     *  @retval Pointer to the DynInst that is at the head of the ROB.
124     */
125//    DynInstPtr readHeadInst();
126
127    /** Returns a pointer to the head instruction of a specific thread within
128     *  the ROB.
129     *  @return Pointer to the DynInst that is at the head of the ROB.
130     */
131    DynInstPtr readHeadInst(ThreadID tid);
132
133    /** Returns a pointer to the instruction with the given sequence if it is
134     *  in the ROB.
135     */
136    DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);
137
138    /** Returns pointer to the tail instruction within the ROB.  There is
139     *  no guarantee as to the return value if the ROB is empty.
140     *  @retval Pointer to the DynInst that is at the tail of the ROB.
141     */
142//    DynInstPtr readTailInst();
143
144    /** Returns a pointer to the tail instruction of a specific thread within
145     *  the ROB.
146     *  @return Pointer to the DynInst that is at the tail of the ROB.
147     */
148    DynInstPtr readTailInst(ThreadID tid);
149
150    /** Retires the head instruction, removing it from the ROB. */
151//    void retireHead();
152
153    /** Retires the head instruction of a specific thread, removing it from the
154     *  ROB.
155     */
156    void retireHead(ThreadID tid);
157
158    /** Is the oldest instruction across all threads ready. */
159//    bool isHeadReady();
160
161    /** Is the oldest instruction across a particular thread ready. */
162    bool isHeadReady(ThreadID tid);
163
164    /** Is there any commitable head instruction across all threads ready. */
165    bool canCommit();
166
167    /** Re-adjust ROB partitioning. */
168    void resetEntries();
169
170    /** Number of entries needed For 'num_threads' amount of threads. */
171    int entryAmount(ThreadID num_threads);
172
173    /** Returns the number of total free entries in the ROB. */
174    unsigned numFreeEntries();
175
176    /** Returns the number of free entries in a specific ROB paritition. */
177    unsigned numFreeEntries(ThreadID tid);
178
179    /** Returns the maximum number of entries for a specific thread. */
180    unsigned getMaxEntries(ThreadID tid)
181    { return maxEntries[tid]; }
182
183    /** Returns the number of entries being used by a specific thread. */
184    unsigned getThreadEntries(ThreadID tid)
185    { return threadEntries[tid]; }
186
187    /** Returns if the ROB is full. */
188    bool isFull()
189    { return numInstsInROB == numEntries; }
190
191    /** Returns if a specific thread's partition is full. */
192    bool isFull(ThreadID tid)
193    { return threadEntries[tid] == numEntries; }
194
195    /** Returns if the ROB is empty. */
196    bool isEmpty() const
197    { return numInstsInROB == 0; }
198
199    /** Returns if a specific thread's partition is empty. */
200    bool isEmpty(ThreadID tid) const
201    { return threadEntries[tid] == 0; }
202
203    /** Executes the squash, marking squashed instructions. */
204    void doSquash(ThreadID tid);
205
206    /** Squashes all instructions younger than the given sequence number for
207     *  the specific thread.
208     */
209    void squash(InstSeqNum squash_num, ThreadID tid);
210
211    /** Updates the head instruction with the new oldest instruction. */
212    void updateHead();
213
214    /** Updates the tail instruction with the new youngest instruction. */
215    void updateTail();
216
217    /** Reads the PC of the oldest head instruction. */
218//    uint64_t readHeadPC();
219
220    /** Reads the PC of the head instruction of a specific thread. */
221//    uint64_t readHeadPC(ThreadID tid);
222
223    /** Reads the next PC of the oldest head instruction. */
224//    uint64_t readHeadNextPC();
225
226    /** Reads the next PC of the head instruction of a specific thread. */
227//    uint64_t readHeadNextPC(ThreadID tid);
228
229    /** Reads the sequence number of the oldest head instruction. */
230//    InstSeqNum readHeadSeqNum();
231
232    /** Reads the sequence number of the head instruction of a specific thread.
233     */
234//    InstSeqNum readHeadSeqNum(ThreadID tid);
235
236    /** Reads the PC of the youngest tail instruction. */
237//    uint64_t readTailPC();
238
239    /** Reads the PC of the tail instruction of a specific thread. */
240//    uint64_t readTailPC(ThreadID tid);
241
242    /** Reads the sequence number of the youngest tail instruction. */
243//    InstSeqNum readTailSeqNum();
244
245    /** Reads the sequence number of tail instruction of a specific thread. */
246//    InstSeqNum readTailSeqNum(ThreadID tid);
247
248    /** Checks if the ROB is still in the process of squashing instructions.
249     *  @retval Whether or not the ROB is done squashing.
250     */
251    bool isDoneSquashing(ThreadID tid) const
252    { return doneSquashing[tid]; }
253
254    /** Checks if the ROB is still in the process of squashing instructions for
255     *  any thread.
256     */
257    bool isDoneSquashing();
258
259    /** This is more of a debugging function than anything.  Use
260     *  numInstsInROB to get the instructions in the ROB unless you are
261     *  double checking that variable.
262     */
263    int countInsts();
264
265    /** This is more of a debugging function than anything.  Use
266     *  threadEntries to get the instructions in the ROB unless you are
267     *  double checking that variable.
268     */
269    int countInsts(ThreadID tid);
270
271    /** Registers statistics. */
272    void regStats();
273
274  private:
275    /** Reset the ROB state */
276    void resetState();
277
278    /** Pointer to the CPU. */
279    O3CPU *cpu;
280
281    /** Active Threads in CPU */
282    std::list<ThreadID> *activeThreads;
283
284    /** Number of instructions in the ROB. */
285    unsigned numEntries;
286
287    /** Entries Per Thread */
288    unsigned threadEntries[Impl::MaxThreads];
289
290    /** Max Insts a Thread Can Have in the ROB */
291    unsigned maxEntries[Impl::MaxThreads];
292
293    /** ROB List of Instructions */
294    std::list<DynInstPtr> instList[Impl::MaxThreads];
295
296    /** Number of instructions that can be squashed in a single cycle. */
297    unsigned squashWidth;
298
299  public:
300    /** Iterator pointing to the instruction which is the last instruction
301     *  in the ROB.  This may at times be invalid (ie when the ROB is empty),
302     *  however it should never be incorrect.
303     */
304    InstIt tail;
305
306    /** Iterator pointing to the instruction which is the first instruction in
307     *  in the ROB*/
308    InstIt head;
309
310  private:
311    /** Iterator used for walking through the list of instructions when
312     *  squashing.  Used so that there is persistent state between cycles;
313     *  when squashing, the instructions are marked as squashed but not
314     *  immediately removed, meaning the tail iterator remains the same before
315     *  and after a squash.
316     *  This will always be set to cpu->instList.end() if it is invalid.
317     */
318    InstIt squashIt[Impl::MaxThreads];
319
320  public:
321    /** Number of instructions in the ROB. */
322    int numInstsInROB;
323
324    /** Dummy instruction returned if there are no insts left. */
325    DynInstPtr dummyInst;
326
327  private:
328    /** The sequence number of the squashed instruction. */
329    InstSeqNum squashedSeqNum[Impl::MaxThreads];
330
331    /** Is the ROB done squashing. */
332    bool doneSquashing[Impl::MaxThreads];
333
334    /** Number of active threads. */
335    ThreadID numThreads;
336
337    // The number of rob_reads
338    Stats::Scalar robReads;
339    // The number of rob_writes
340    Stats::Scalar robWrites;
341};
342
343#endif //__CPU_O3_ROB_HH__
344