rob.hh revision 8230
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_ROB_HH__ 332292SN/A#define __CPU_O3_ROB_HH__ 341060SN/A 352292SN/A#include <string> 361461SN/A#include <utility> 371461SN/A#include <vector> 381060SN/A 398230Snate@binkert.org#include "arch/registers.hh" 408230Snate@binkert.org#include "base/types.hh" 416658Snate@binkert.org#include "config/the_isa.hh" 426658Snate@binkert.org 431060SN/A/** 442292SN/A * ROB class. The ROB is largely what drives squashing. 451060SN/A */ 461061SN/Atemplate <class Impl> 471060SN/Aclass ROB 481060SN/A{ 492107SN/A protected: 502107SN/A typedef TheISA::RegIndex RegIndex; 511060SN/A public: 521060SN/A //Typedefs from the Impl. 532733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 541061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 551060SN/A 562292SN/A typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 572292SN/A typedef typename std::list<DynInstPtr>::iterator InstIt; 582292SN/A 592292SN/A /** Possible ROB statuses. */ 602292SN/A enum Status { 612292SN/A Running, 622292SN/A Idle, 632329SN/A ROBSquashing 642292SN/A }; 652292SN/A 662292SN/A /** SMT ROB Sharing Policy */ 672292SN/A enum ROBPolicy{ 682292SN/A Dynamic, 692292SN/A Partitioned, 702292SN/A Threshold 712292SN/A }; 722292SN/A 732292SN/A private: 742292SN/A /** Per-thread ROB status. */ 752292SN/A Status robStatus[Impl::MaxThreads]; 762292SN/A 772292SN/A /** ROB resource sharing policy for SMT mode. */ 782292SN/A ROBPolicy robPolicy; 791060SN/A 801060SN/A public: 811060SN/A /** ROB constructor. 822292SN/A * @param _numEntries Number of entries in ROB. 832292SN/A * @param _squashWidth Number of instructions that can be squashed in a 842292SN/A * single cycle. 852292SN/A * @param _smtROBPolicy ROB Partitioning Scheme for SMT. 862292SN/A * @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB. 872292SN/A * @param _numThreads The number of active threads. 881060SN/A */ 894329Sktlim@umich.edu ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 904329Sktlim@umich.edu std::string smtROBPolicy, unsigned _smtROBThreshold, 916221Snate@binkert.org ThreadID _numThreads); 922292SN/A 932292SN/A std::string name() const; 941060SN/A 952292SN/A /** Sets pointer to the list of active threads. 962292SN/A * @param at_ptr Pointer to the list of active threads. 972292SN/A */ 986221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 992292SN/A 1002348SN/A /** Switches out the ROB. */ 1012307SN/A void switchOut(); 1022307SN/A 1032348SN/A /** Takes over another CPU's thread. */ 1042307SN/A void takeOverFrom(); 1052307SN/A 1062292SN/A /** Function to insert an instruction into the ROB. Note that whatever 1072292SN/A * calls this function must ensure that there is enough space within the 1082292SN/A * ROB for the new instruction. 1091763SN/A * @param inst The instruction being inserted into the ROB. 1101060SN/A */ 1111061SN/A void insertInst(DynInstPtr &inst); 1121060SN/A 1131060SN/A /** Returns pointer to the head instruction within the ROB. There is 1141060SN/A * no guarantee as to the return value if the ROB is empty. 1151060SN/A * @retval Pointer to the DynInst that is at the head of the ROB. 1161060SN/A */ 1172329SN/A// DynInstPtr readHeadInst(); 1181060SN/A 1192292SN/A /** Returns a pointer to the head instruction of a specific thread within 1202292SN/A * the ROB. 1212292SN/A * @return Pointer to the DynInst that is at the head of the ROB. 1222292SN/A */ 1236221Snate@binkert.org DynInstPtr readHeadInst(ThreadID tid); 1241060SN/A 1252292SN/A /** Returns pointer to the tail instruction within the ROB. There is 1262292SN/A * no guarantee as to the return value if the ROB is empty. 1272292SN/A * @retval Pointer to the DynInst that is at the tail of the ROB. 1282292SN/A */ 1292329SN/A// DynInstPtr readTailInst(); 1301060SN/A 1312292SN/A /** Returns a pointer to the tail instruction of a specific thread within 1322292SN/A * the ROB. 1332292SN/A * @return Pointer to the DynInst that is at the tail of the ROB. 1342292SN/A */ 1356221Snate@binkert.org DynInstPtr readTailInst(ThreadID tid); 1361060SN/A 1372292SN/A /** Retires the head instruction, removing it from the ROB. */ 1382329SN/A// void retireHead(); 1392107SN/A 1402292SN/A /** Retires the head instruction of a specific thread, removing it from the 1412292SN/A * ROB. 1422292SN/A */ 1436221Snate@binkert.org void retireHead(ThreadID tid); 1442292SN/A 1452292SN/A /** Is the oldest instruction across all threads ready. */ 1462329SN/A// bool isHeadReady(); 1472107SN/A 1482292SN/A /** Is the oldest instruction across a particular thread ready. */ 1496221Snate@binkert.org bool isHeadReady(ThreadID tid); 1502292SN/A 1512292SN/A /** Is there any commitable head instruction across all threads ready. */ 1522292SN/A bool canCommit(); 1532292SN/A 1542292SN/A /** Re-adjust ROB partitioning. */ 1552292SN/A void resetEntries(); 1562292SN/A 1572292SN/A /** Number of entries needed For 'num_threads' amount of threads. */ 1586221Snate@binkert.org int entryAmount(ThreadID num_threads); 1592292SN/A 1602292SN/A /** Returns the number of total free entries in the ROB. */ 1611060SN/A unsigned numFreeEntries(); 1621060SN/A 1632292SN/A /** Returns the number of free entries in a specific ROB paritition. */ 1646221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 1652292SN/A 1662292SN/A /** Returns the maximum number of entries for a specific thread. */ 1676221Snate@binkert.org unsigned getMaxEntries(ThreadID tid) 1682292SN/A { return maxEntries[tid]; } 1692292SN/A 1702292SN/A /** Returns the number of entries being used by a specific thread. */ 1716221Snate@binkert.org unsigned getThreadEntries(ThreadID tid) 1722292SN/A { return threadEntries[tid]; } 1732292SN/A 1742292SN/A /** Returns if the ROB is full. */ 1751060SN/A bool isFull() 1761060SN/A { return numInstsInROB == numEntries; } 1771060SN/A 1782292SN/A /** Returns if a specific thread's partition is full. */ 1796221Snate@binkert.org bool isFull(ThreadID tid) 1802292SN/A { return threadEntries[tid] == numEntries; } 1812292SN/A 1822292SN/A /** Returns if the ROB is empty. */ 1831060SN/A bool isEmpty() 1841060SN/A { return numInstsInROB == 0; } 1851060SN/A 1862292SN/A /** Returns if a specific thread's partition is empty. */ 1876221Snate@binkert.org bool isEmpty(ThreadID tid) 1882292SN/A { return threadEntries[tid] == 0; } 1891060SN/A 1902292SN/A /** Executes the squash, marking squashed instructions. */ 1916221Snate@binkert.org void doSquash(ThreadID tid); 1921060SN/A 1932292SN/A /** Squashes all instructions younger than the given sequence number for 1942292SN/A * the specific thread. 1952292SN/A */ 1966221Snate@binkert.org void squash(InstSeqNum squash_num, ThreadID tid); 1971060SN/A 1982292SN/A /** Updates the head instruction with the new oldest instruction. */ 1992292SN/A void updateHead(); 2001060SN/A 2012292SN/A /** Updates the tail instruction with the new youngest instruction. */ 2022292SN/A void updateTail(); 2031060SN/A 2042292SN/A /** Reads the PC of the oldest head instruction. */ 2052329SN/A// uint64_t readHeadPC(); 2061060SN/A 2072292SN/A /** Reads the PC of the head instruction of a specific thread. */ 2086221Snate@binkert.org// uint64_t readHeadPC(ThreadID tid); 2092292SN/A 2102292SN/A /** Reads the next PC of the oldest head instruction. */ 2112329SN/A// uint64_t readHeadNextPC(); 2122107SN/A 2132292SN/A /** Reads the next PC of the head instruction of a specific thread. */ 2146221Snate@binkert.org// uint64_t readHeadNextPC(ThreadID tid); 2152292SN/A 2162292SN/A /** Reads the sequence number of the oldest head instruction. */ 2172329SN/A// InstSeqNum readHeadSeqNum(); 2182107SN/A 2192292SN/A /** Reads the sequence number of the head instruction of a specific thread. 2202292SN/A */ 2216221Snate@binkert.org// InstSeqNum readHeadSeqNum(ThreadID tid); 2222292SN/A 2232292SN/A /** Reads the PC of the youngest tail instruction. */ 2242329SN/A// uint64_t readTailPC(); 2252107SN/A 2262292SN/A /** Reads the PC of the tail instruction of a specific thread. */ 2276221Snate@binkert.org// uint64_t readTailPC(ThreadID tid); 2282292SN/A 2292292SN/A /** Reads the sequence number of the youngest tail instruction. */ 2302329SN/A// InstSeqNum readTailSeqNum(); 2312107SN/A 2322292SN/A /** Reads the sequence number of tail instruction of a specific thread. */ 2336221Snate@binkert.org// InstSeqNum readTailSeqNum(ThreadID tid); 2341060SN/A 2351060SN/A /** Checks if the ROB is still in the process of squashing instructions. 2361060SN/A * @retval Whether or not the ROB is done squashing. 2371060SN/A */ 2386221Snate@binkert.org bool isDoneSquashing(ThreadID tid) const 2392292SN/A { return doneSquashing[tid]; } 2402292SN/A 2412292SN/A /** Checks if the ROB is still in the process of squashing instructions for 2422292SN/A * any thread. 2432292SN/A */ 2442292SN/A bool isDoneSquashing(); 2451060SN/A 2461060SN/A /** This is more of a debugging function than anything. Use 2471060SN/A * numInstsInROB to get the instructions in the ROB unless you are 2481060SN/A * double checking that variable. 2491060SN/A */ 2501060SN/A int countInsts(); 2511060SN/A 2522292SN/A /** This is more of a debugging function than anything. Use 2532292SN/A * threadEntries to get the instructions in the ROB unless you are 2542292SN/A * double checking that variable. 2552292SN/A */ 2566221Snate@binkert.org int countInsts(ThreadID tid); 2572292SN/A 2587897Shestness@cs.utexas.edu /** Registers statistics. */ 2597897Shestness@cs.utexas.edu void regStats(); 2607897Shestness@cs.utexas.edu 2611060SN/A private: 2621060SN/A /** Pointer to the CPU. */ 2632733Sktlim@umich.edu O3CPU *cpu; 2641060SN/A 2652292SN/A /** Active Threads in CPU */ 2666221Snate@binkert.org std::list<ThreadID> *activeThreads; 2672292SN/A 2681061SN/A /** Number of instructions in the ROB. */ 2691060SN/A unsigned numEntries; 2701060SN/A 2712292SN/A /** Entries Per Thread */ 2722292SN/A unsigned threadEntries[Impl::MaxThreads]; 2732292SN/A 2742292SN/A /** Max Insts a Thread Can Have in the ROB */ 2752292SN/A unsigned maxEntries[Impl::MaxThreads]; 2762292SN/A 2772292SN/A /** ROB List of Instructions */ 2782292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2792292SN/A 2801060SN/A /** Number of instructions that can be squashed in a single cycle. */ 2811060SN/A unsigned squashWidth; 2821060SN/A 2832292SN/A public: 2841061SN/A /** Iterator pointing to the instruction which is the last instruction 2851061SN/A * in the ROB. This may at times be invalid (ie when the ROB is empty), 2861061SN/A * however it should never be incorrect. 2871061SN/A */ 2882292SN/A InstIt tail; 2891060SN/A 2902292SN/A /** Iterator pointing to the instruction which is the first instruction in 2912292SN/A * in the ROB*/ 2922292SN/A InstIt head; 2932292SN/A 2942292SN/A private: 2951061SN/A /** Iterator used for walking through the list of instructions when 2961061SN/A * squashing. Used so that there is persistent state between cycles; 2971061SN/A * when squashing, the instructions are marked as squashed but not 2981061SN/A * immediately removed, meaning the tail iterator remains the same before 2991061SN/A * and after a squash. 3001061SN/A * This will always be set to cpu->instList.end() if it is invalid. 3011061SN/A */ 3022292SN/A InstIt squashIt[Impl::MaxThreads]; 3031060SN/A 3042292SN/A public: 3051061SN/A /** Number of instructions in the ROB. */ 3061060SN/A int numInstsInROB; 3071060SN/A 3082348SN/A /** Dummy instruction returned if there are no insts left. */ 3092292SN/A DynInstPtr dummyInst; 3102292SN/A 3112292SN/A private: 3121060SN/A /** The sequence number of the squashed instruction. */ 3132877Sksewell@umich.edu InstSeqNum squashedSeqNum[Impl::MaxThreads]; 3141060SN/A 3151060SN/A /** Is the ROB done squashing. */ 3162292SN/A bool doneSquashing[Impl::MaxThreads]; 3172292SN/A 3182292SN/A /** Number of active threads. */ 3196221Snate@binkert.org ThreadID numThreads; 3207897Shestness@cs.utexas.edu 3217897Shestness@cs.utexas.edu // The number of rob_reads 3227897Shestness@cs.utexas.edu Stats::Scalar robReads; 3237897Shestness@cs.utexas.edu // The number of rob_writes 3247897Shestness@cs.utexas.edu Stats::Scalar robWrites; 3251060SN/A}; 3261060SN/A 3272292SN/A#endif //__CPU_O3_ROB_HH__ 328