rob.hh revision 7897
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_ROB_HH__ 332292SN/A#define __CPU_O3_ROB_HH__ 341060SN/A 352292SN/A#include <string> 361461SN/A#include <utility> 371461SN/A#include <vector> 381060SN/A 396658Snate@binkert.org#include "config/the_isa.hh" 406658Snate@binkert.org 411060SN/A/** 422292SN/A * ROB class. The ROB is largely what drives squashing. 431060SN/A */ 441061SN/Atemplate <class Impl> 451060SN/Aclass ROB 461060SN/A{ 472107SN/A protected: 482107SN/A typedef TheISA::RegIndex RegIndex; 491060SN/A public: 501060SN/A //Typedefs from the Impl. 512733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 521061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 531060SN/A 542292SN/A typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 552292SN/A typedef typename std::list<DynInstPtr>::iterator InstIt; 562292SN/A 572292SN/A /** Possible ROB statuses. */ 582292SN/A enum Status { 592292SN/A Running, 602292SN/A Idle, 612329SN/A ROBSquashing 622292SN/A }; 632292SN/A 642292SN/A /** SMT ROB Sharing Policy */ 652292SN/A enum ROBPolicy{ 662292SN/A Dynamic, 672292SN/A Partitioned, 682292SN/A Threshold 692292SN/A }; 702292SN/A 712292SN/A private: 722292SN/A /** Per-thread ROB status. */ 732292SN/A Status robStatus[Impl::MaxThreads]; 742292SN/A 752292SN/A /** ROB resource sharing policy for SMT mode. */ 762292SN/A ROBPolicy robPolicy; 771060SN/A 781060SN/A public: 791060SN/A /** ROB constructor. 802292SN/A * @param _numEntries Number of entries in ROB. 812292SN/A * @param _squashWidth Number of instructions that can be squashed in a 822292SN/A * single cycle. 832292SN/A * @param _smtROBPolicy ROB Partitioning Scheme for SMT. 842292SN/A * @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB. 852292SN/A * @param _numThreads The number of active threads. 861060SN/A */ 874329Sktlim@umich.edu ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 884329Sktlim@umich.edu std::string smtROBPolicy, unsigned _smtROBThreshold, 896221Snate@binkert.org ThreadID _numThreads); 902292SN/A 912292SN/A std::string name() const; 921060SN/A 932292SN/A /** Sets pointer to the list of active threads. 942292SN/A * @param at_ptr Pointer to the list of active threads. 952292SN/A */ 966221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 972292SN/A 982348SN/A /** Switches out the ROB. */ 992307SN/A void switchOut(); 1002307SN/A 1012348SN/A /** Takes over another CPU's thread. */ 1022307SN/A void takeOverFrom(); 1032307SN/A 1042292SN/A /** Function to insert an instruction into the ROB. Note that whatever 1052292SN/A * calls this function must ensure that there is enough space within the 1062292SN/A * ROB for the new instruction. 1071763SN/A * @param inst The instruction being inserted into the ROB. 1081060SN/A */ 1091061SN/A void insertInst(DynInstPtr &inst); 1101060SN/A 1111060SN/A /** Returns pointer to the head instruction within the ROB. There is 1121060SN/A * no guarantee as to the return value if the ROB is empty. 1131060SN/A * @retval Pointer to the DynInst that is at the head of the ROB. 1141060SN/A */ 1152329SN/A// DynInstPtr readHeadInst(); 1161060SN/A 1172292SN/A /** Returns a pointer to the head instruction of a specific thread within 1182292SN/A * the ROB. 1192292SN/A * @return Pointer to the DynInst that is at the head of the ROB. 1202292SN/A */ 1216221Snate@binkert.org DynInstPtr readHeadInst(ThreadID tid); 1221060SN/A 1232292SN/A /** Returns pointer to the tail instruction within the ROB. There is 1242292SN/A * no guarantee as to the return value if the ROB is empty. 1252292SN/A * @retval Pointer to the DynInst that is at the tail of the ROB. 1262292SN/A */ 1272329SN/A// DynInstPtr readTailInst(); 1281060SN/A 1292292SN/A /** Returns a pointer to the tail instruction of a specific thread within 1302292SN/A * the ROB. 1312292SN/A * @return Pointer to the DynInst that is at the tail of the ROB. 1322292SN/A */ 1336221Snate@binkert.org DynInstPtr readTailInst(ThreadID tid); 1341060SN/A 1352292SN/A /** Retires the head instruction, removing it from the ROB. */ 1362329SN/A// void retireHead(); 1372107SN/A 1382292SN/A /** Retires the head instruction of a specific thread, removing it from the 1392292SN/A * ROB. 1402292SN/A */ 1416221Snate@binkert.org void retireHead(ThreadID tid); 1422292SN/A 1432292SN/A /** Is the oldest instruction across all threads ready. */ 1442329SN/A// bool isHeadReady(); 1452107SN/A 1462292SN/A /** Is the oldest instruction across a particular thread ready. */ 1476221Snate@binkert.org bool isHeadReady(ThreadID tid); 1482292SN/A 1492292SN/A /** Is there any commitable head instruction across all threads ready. */ 1502292SN/A bool canCommit(); 1512292SN/A 1522292SN/A /** Re-adjust ROB partitioning. */ 1532292SN/A void resetEntries(); 1542292SN/A 1552292SN/A /** Number of entries needed For 'num_threads' amount of threads. */ 1566221Snate@binkert.org int entryAmount(ThreadID num_threads); 1572292SN/A 1582292SN/A /** Returns the number of total free entries in the ROB. */ 1591060SN/A unsigned numFreeEntries(); 1601060SN/A 1612292SN/A /** Returns the number of free entries in a specific ROB paritition. */ 1626221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 1632292SN/A 1642292SN/A /** Returns the maximum number of entries for a specific thread. */ 1656221Snate@binkert.org unsigned getMaxEntries(ThreadID tid) 1662292SN/A { return maxEntries[tid]; } 1672292SN/A 1682292SN/A /** Returns the number of entries being used by a specific thread. */ 1696221Snate@binkert.org unsigned getThreadEntries(ThreadID tid) 1702292SN/A { return threadEntries[tid]; } 1712292SN/A 1722292SN/A /** Returns if the ROB is full. */ 1731060SN/A bool isFull() 1741060SN/A { return numInstsInROB == numEntries; } 1751060SN/A 1762292SN/A /** Returns if a specific thread's partition is full. */ 1776221Snate@binkert.org bool isFull(ThreadID tid) 1782292SN/A { return threadEntries[tid] == numEntries; } 1792292SN/A 1802292SN/A /** Returns if the ROB is empty. */ 1811060SN/A bool isEmpty() 1821060SN/A { return numInstsInROB == 0; } 1831060SN/A 1842292SN/A /** Returns if a specific thread's partition is empty. */ 1856221Snate@binkert.org bool isEmpty(ThreadID tid) 1862292SN/A { return threadEntries[tid] == 0; } 1871060SN/A 1882292SN/A /** Executes the squash, marking squashed instructions. */ 1896221Snate@binkert.org void doSquash(ThreadID tid); 1901060SN/A 1912292SN/A /** Squashes all instructions younger than the given sequence number for 1922292SN/A * the specific thread. 1932292SN/A */ 1946221Snate@binkert.org void squash(InstSeqNum squash_num, ThreadID tid); 1951060SN/A 1962292SN/A /** Updates the head instruction with the new oldest instruction. */ 1972292SN/A void updateHead(); 1981060SN/A 1992292SN/A /** Updates the tail instruction with the new youngest instruction. */ 2002292SN/A void updateTail(); 2011060SN/A 2022292SN/A /** Reads the PC of the oldest head instruction. */ 2032329SN/A// uint64_t readHeadPC(); 2041060SN/A 2052292SN/A /** Reads the PC of the head instruction of a specific thread. */ 2066221Snate@binkert.org// uint64_t readHeadPC(ThreadID tid); 2072292SN/A 2082292SN/A /** Reads the next PC of the oldest head instruction. */ 2092329SN/A// uint64_t readHeadNextPC(); 2102107SN/A 2112292SN/A /** Reads the next PC of the head instruction of a specific thread. */ 2126221Snate@binkert.org// uint64_t readHeadNextPC(ThreadID tid); 2132292SN/A 2142292SN/A /** Reads the sequence number of the oldest head instruction. */ 2152329SN/A// InstSeqNum readHeadSeqNum(); 2162107SN/A 2172292SN/A /** Reads the sequence number of the head instruction of a specific thread. 2182292SN/A */ 2196221Snate@binkert.org// InstSeqNum readHeadSeqNum(ThreadID tid); 2202292SN/A 2212292SN/A /** Reads the PC of the youngest tail instruction. */ 2222329SN/A// uint64_t readTailPC(); 2232107SN/A 2242292SN/A /** Reads the PC of the tail instruction of a specific thread. */ 2256221Snate@binkert.org// uint64_t readTailPC(ThreadID tid); 2262292SN/A 2272292SN/A /** Reads the sequence number of the youngest tail instruction. */ 2282329SN/A// InstSeqNum readTailSeqNum(); 2292107SN/A 2302292SN/A /** Reads the sequence number of tail instruction of a specific thread. */ 2316221Snate@binkert.org// InstSeqNum readTailSeqNum(ThreadID tid); 2321060SN/A 2331060SN/A /** Checks if the ROB is still in the process of squashing instructions. 2341060SN/A * @retval Whether or not the ROB is done squashing. 2351060SN/A */ 2366221Snate@binkert.org bool isDoneSquashing(ThreadID tid) const 2372292SN/A { return doneSquashing[tid]; } 2382292SN/A 2392292SN/A /** Checks if the ROB is still in the process of squashing instructions for 2402292SN/A * any thread. 2412292SN/A */ 2422292SN/A bool isDoneSquashing(); 2431060SN/A 2441060SN/A /** This is more of a debugging function than anything. Use 2451060SN/A * numInstsInROB to get the instructions in the ROB unless you are 2461060SN/A * double checking that variable. 2471060SN/A */ 2481060SN/A int countInsts(); 2491060SN/A 2502292SN/A /** This is more of a debugging function than anything. Use 2512292SN/A * threadEntries to get the instructions in the ROB unless you are 2522292SN/A * double checking that variable. 2532292SN/A */ 2546221Snate@binkert.org int countInsts(ThreadID tid); 2552292SN/A 2567897Shestness@cs.utexas.edu /** Registers statistics. */ 2577897Shestness@cs.utexas.edu void regStats(); 2587897Shestness@cs.utexas.edu 2591060SN/A private: 2601060SN/A /** Pointer to the CPU. */ 2612733Sktlim@umich.edu O3CPU *cpu; 2621060SN/A 2632292SN/A /** Active Threads in CPU */ 2646221Snate@binkert.org std::list<ThreadID> *activeThreads; 2652292SN/A 2661061SN/A /** Number of instructions in the ROB. */ 2671060SN/A unsigned numEntries; 2681060SN/A 2692292SN/A /** Entries Per Thread */ 2702292SN/A unsigned threadEntries[Impl::MaxThreads]; 2712292SN/A 2722292SN/A /** Max Insts a Thread Can Have in the ROB */ 2732292SN/A unsigned maxEntries[Impl::MaxThreads]; 2742292SN/A 2752292SN/A /** ROB List of Instructions */ 2762292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2772292SN/A 2781060SN/A /** Number of instructions that can be squashed in a single cycle. */ 2791060SN/A unsigned squashWidth; 2801060SN/A 2812292SN/A public: 2821061SN/A /** Iterator pointing to the instruction which is the last instruction 2831061SN/A * in the ROB. This may at times be invalid (ie when the ROB is empty), 2841061SN/A * however it should never be incorrect. 2851061SN/A */ 2862292SN/A InstIt tail; 2871060SN/A 2882292SN/A /** Iterator pointing to the instruction which is the first instruction in 2892292SN/A * in the ROB*/ 2902292SN/A InstIt head; 2912292SN/A 2922292SN/A private: 2931061SN/A /** Iterator used for walking through the list of instructions when 2941061SN/A * squashing. Used so that there is persistent state between cycles; 2951061SN/A * when squashing, the instructions are marked as squashed but not 2961061SN/A * immediately removed, meaning the tail iterator remains the same before 2971061SN/A * and after a squash. 2981061SN/A * This will always be set to cpu->instList.end() if it is invalid. 2991061SN/A */ 3002292SN/A InstIt squashIt[Impl::MaxThreads]; 3011060SN/A 3022292SN/A public: 3031061SN/A /** Number of instructions in the ROB. */ 3041060SN/A int numInstsInROB; 3051060SN/A 3062348SN/A /** Dummy instruction returned if there are no insts left. */ 3072292SN/A DynInstPtr dummyInst; 3082292SN/A 3092292SN/A private: 3101060SN/A /** The sequence number of the squashed instruction. */ 3112877Sksewell@umich.edu InstSeqNum squashedSeqNum[Impl::MaxThreads]; 3121060SN/A 3131060SN/A /** Is the ROB done squashing. */ 3142292SN/A bool doneSquashing[Impl::MaxThreads]; 3152292SN/A 3162292SN/A /** Number of active threads. */ 3176221Snate@binkert.org ThreadID numThreads; 3187897Shestness@cs.utexas.edu 3197897Shestness@cs.utexas.edu // The number of rob_reads 3207897Shestness@cs.utexas.edu Stats::Scalar robReads; 3217897Shestness@cs.utexas.edu // The number of rob_writes 3227897Shestness@cs.utexas.edu Stats::Scalar robWrites; 3231060SN/A}; 3241060SN/A 3252292SN/A#endif //__CPU_O3_ROB_HH__ 326