rob.hh revision 1763
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 312855Sgabeblack@google.com * All rights reserved. 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com * this software without specific prior written permission. 1512855Sgabeblack@google.com * 1612855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com */ 2812855Sgabeblack@google.com 2912855Sgabeblack@google.com// Todo: Probably add in support for scheduling events (more than one as 3012855Sgabeblack@google.com// well) on the case of the ROB being empty or full. Considering tracking 3112855Sgabeblack@google.com// free entries instead of insts in ROB. Differentiate between squashing 3212855Sgabeblack@google.com// all instructions after the instruction, and all instructions after *and* 3312855Sgabeblack@google.com// including that instruction. 3412855Sgabeblack@google.com 3512855Sgabeblack@google.com#ifndef __CPU_O3_CPU_ROB_HH__ 3612855Sgabeblack@google.com#define __CPU_O3_CPU_ROB_HH__ 3712855Sgabeblack@google.com 3812855Sgabeblack@google.com#include <utility> 3912855Sgabeblack@google.com#include <vector> 4012855Sgabeblack@google.com 4112855Sgabeblack@google.com/** 4212855Sgabeblack@google.com * ROB class. Uses the instruction list that exists within the CPU to 4312855Sgabeblack@google.com * represent the ROB. This class doesn't contain that list, but instead 4412855Sgabeblack@google.com * a pointer to the CPU to get access to the list. The ROB, in this first 4512855Sgabeblack@google.com * implementation, is largely what drives squashing. 4612855Sgabeblack@google.com */ 4712855Sgabeblack@google.comtemplate <class Impl> 4812855Sgabeblack@google.comclass ROB 4912855Sgabeblack@google.com{ 5012855Sgabeblack@google.com public: 5112855Sgabeblack@google.com //Typedefs from the Impl. 5212855Sgabeblack@google.com typedef typename Impl::FullCPU FullCPU; 5312855Sgabeblack@google.com typedef typename Impl::DynInstPtr DynInstPtr; 5412855Sgabeblack@google.com 5512855Sgabeblack@google.com typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo_t; 5612855Sgabeblack@google.com typedef typename list<DynInstPtr>::iterator InstIt_t; 5712855Sgabeblack@google.com 5812855Sgabeblack@google.com public: 5912855Sgabeblack@google.com /** ROB constructor. 6012855Sgabeblack@google.com * @param _numEntries Number of entries in ROB. 6112855Sgabeblack@google.com * @param _squashWidth Number of instructions that can be squashed in a 6212855Sgabeblack@google.com * single cycle. 6312855Sgabeblack@google.com */ 6412855Sgabeblack@google.com ROB(unsigned _numEntries, unsigned _squashWidth); 6512855Sgabeblack@google.com 6612855Sgabeblack@google.com /** Function to set the CPU pointer, necessary due to which object the ROB 6712855Sgabeblack@google.com * is created within. 6812855Sgabeblack@google.com * @param cpu_ptr Pointer to the implementation specific full CPU object. 6912855Sgabeblack@google.com */ 7012855Sgabeblack@google.com void setCPU(FullCPU *cpu_ptr); 7112855Sgabeblack@google.com 7212855Sgabeblack@google.com /** Function to insert an instruction into the ROB. The parameter inst is 7312855Sgabeblack@google.com * not truly required, but is useful for checking correctness. Note 7412855Sgabeblack@google.com * that whatever calls this function must ensure that there is enough 7512855Sgabeblack@google.com * space within the ROB for the new instruction. 7612855Sgabeblack@google.com * @param inst The instruction being inserted into the ROB. 7712855Sgabeblack@google.com * @todo Remove the parameter once correctness is ensured. 7812855Sgabeblack@google.com */ 7912855Sgabeblack@google.com void insertInst(DynInstPtr &inst); 8012855Sgabeblack@google.com 8112855Sgabeblack@google.com /** Returns pointer to the head instruction within the ROB. There is 8212855Sgabeblack@google.com * no guarantee as to the return value if the ROB is empty. 8312855Sgabeblack@google.com * @retval Pointer to the DynInst that is at the head of the ROB. 8412855Sgabeblack@google.com */ 8512855Sgabeblack@google.com DynInstPtr readHeadInst() { return cpu->instList.front(); } 8612855Sgabeblack@google.com 8712855Sgabeblack@google.com DynInstPtr readTailInst() { return (*tail); } 8812855Sgabeblack@google.com 8912855Sgabeblack@google.com void retireHead(); 9012855Sgabeblack@google.com 9112855Sgabeblack@google.com bool isHeadReady(); 9212855Sgabeblack@google.com 9312855Sgabeblack@google.com unsigned numFreeEntries(); 9412855Sgabeblack@google.com 9512855Sgabeblack@google.com bool isFull() 9612855Sgabeblack@google.com { return numInstsInROB == numEntries; } 9712855Sgabeblack@google.com 9812855Sgabeblack@google.com bool isEmpty() 9912855Sgabeblack@google.com { return numInstsInROB == 0; } 10012855Sgabeblack@google.com 10112855Sgabeblack@google.com void doSquash(); 10212855Sgabeblack@google.com 10312855Sgabeblack@google.com void squash(InstSeqNum squash_num); 10412855Sgabeblack@google.com 10512855Sgabeblack@google.com uint64_t readHeadPC(); 10612855Sgabeblack@google.com 10712855Sgabeblack@google.com uint64_t readHeadNextPC(); 10812855Sgabeblack@google.com 10912855Sgabeblack@google.com InstSeqNum readHeadSeqNum(); 11012855Sgabeblack@google.com 11112855Sgabeblack@google.com uint64_t readTailPC(); 11212855Sgabeblack@google.com 11312855Sgabeblack@google.com InstSeqNum readTailSeqNum(); 11412855Sgabeblack@google.com 11512855Sgabeblack@google.com /** Checks if the ROB is still in the process of squashing instructions. 11612855Sgabeblack@google.com * @retval Whether or not the ROB is done squashing. 11712855Sgabeblack@google.com */ 11812855Sgabeblack@google.com bool isDoneSquashing() const { return doneSquashing; } 11912855Sgabeblack@google.com 12012855Sgabeblack@google.com /** This is more of a debugging function than anything. Use 12112855Sgabeblack@google.com * numInstsInROB to get the instructions in the ROB unless you are 12212855Sgabeblack@google.com * double checking that variable. 12312855Sgabeblack@google.com */ 12412855Sgabeblack@google.com int countInsts(); 12512855Sgabeblack@google.com 12612855Sgabeblack@google.com private: 12712855Sgabeblack@google.com 12812855Sgabeblack@google.com /** Pointer to the CPU. */ 12912855Sgabeblack@google.com FullCPU *cpu; 13012855Sgabeblack@google.com 13112855Sgabeblack@google.com /** Number of instructions in the ROB. */ 13212855Sgabeblack@google.com unsigned numEntries; 13312855Sgabeblack@google.com 13412855Sgabeblack@google.com /** Number of instructions that can be squashed in a single cycle. */ 13512855Sgabeblack@google.com unsigned squashWidth; 13612855Sgabeblack@google.com 13712855Sgabeblack@google.com /** Iterator pointing to the instruction which is the last instruction 13812855Sgabeblack@google.com * in the ROB. This may at times be invalid (ie when the ROB is empty), 13912855Sgabeblack@google.com * however it should never be incorrect. 14012855Sgabeblack@google.com */ 14112855Sgabeblack@google.com InstIt_t tail; 14212855Sgabeblack@google.com 14312855Sgabeblack@google.com /** Iterator used for walking through the list of instructions when 14412855Sgabeblack@google.com * squashing. Used so that there is persistent state between cycles; 14512855Sgabeblack@google.com * when squashing, the instructions are marked as squashed but not 14612855Sgabeblack@google.com * immediately removed, meaning the tail iterator remains the same before 14712855Sgabeblack@google.com * and after a squash. 14812855Sgabeblack@google.com * This will always be set to cpu->instList.end() if it is invalid. 14912855Sgabeblack@google.com */ 15012855Sgabeblack@google.com InstIt_t squashIt; 15112855Sgabeblack@google.com 15212855Sgabeblack@google.com /** Number of instructions in the ROB. */ 15312855Sgabeblack@google.com int numInstsInROB; 15412855Sgabeblack@google.com 15512855Sgabeblack@google.com /** The sequence number of the squashed instruction. */ 15612855Sgabeblack@google.com InstSeqNum squashedSeqNum; 15712855Sgabeblack@google.com 15812855Sgabeblack@google.com /** Is the ROB done squashing. */ 15912855Sgabeblack@google.com bool doneSquashing; 16012855Sgabeblack@google.com}; 16112855Sgabeblack@google.com 16212855Sgabeblack@google.com#endif //__CPU_O3_CPU_ROB_HH__ 16312855Sgabeblack@google.com