rob.hh revision 1689
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29// Todo: Probably add in support for scheduling events (more than one as 30// well) on the case of the ROB being empty or full. Considering tracking 31// free entries instead of insts in ROB. Differentiate between squashing 32// all instructions after the instruction, and all instructions after *and* 33// including that instruction. 34 35#ifndef __CPU_BETA_CPU_ROB_HH__ 36#define __CPU_BETA_CPU_ROB_HH__ 37 38#include <utility> 39#include <vector> 40 41/** 42 * ROB class. Uses the instruction list that exists within the CPU to 43 * represent the ROB. This class doesn't contain that list, but instead 44 * a pointer to the CPU to get access to the list. The ROB, in this first 45 * implementation, is largely what drives squashing. 46 */ 47template <class Impl> 48class ROB 49{ 50 public: 51 //Typedefs from the Impl. 52 typedef typename Impl::FullCPU FullCPU; 53 typedef typename Impl::DynInstPtr DynInstPtr; 54 55 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo_t; 56 typedef typename list<DynInstPtr>::iterator InstIt_t; 57 58 public: 59 /** ROB constructor. 60 * @params _numEntries Number of entries in ROB. 61 * @params _squashWidth Number of instructions that can be squashed in a 62 * single cycle. 63 */ 64 ROB(unsigned _numEntries, unsigned _squashWidth); 65 66 /** Function to set the CPU pointer, necessary due to which object the ROB 67 * is created within. 68 * @params cpu_ptr Pointer to the implementation specific full CPU object. 69 */ 70 void setCPU(FullCPU *cpu_ptr); 71 72 /** Function to insert an instruction into the ROB. The parameter inst is 73 * not truly required, but is useful for checking correctness. Note 74 * that whatever calls this function must ensure that there is enough 75 * space within the ROB for the new instruction. 76 * @params inst The instruction being inserted into the ROB. 77 * @todo Remove the parameter once correctness is ensured. 78 */ 79 void insertInst(DynInstPtr &inst); 80 81 /** Returns pointer to the head instruction within the ROB. There is 82 * no guarantee as to the return value if the ROB is empty. 83 * @retval Pointer to the DynInst that is at the head of the ROB. 84 */ 85 DynInstPtr readHeadInst() { return cpu->instList.front(); } 86 87 DynInstPtr readTailInst() { return (*tail); } 88 89 void retireHead(); 90 91 bool isHeadReady(); 92 93 unsigned numFreeEntries(); 94 95 bool isFull() 96 { return numInstsInROB == numEntries; } 97 98 bool isEmpty() 99 { return numInstsInROB == 0; } 100 101 void doSquash(); 102 103 void squash(InstSeqNum squash_num); 104 105 uint64_t readHeadPC(); 106 107 uint64_t readHeadNextPC(); 108 109 InstSeqNum readHeadSeqNum(); 110 111 uint64_t readTailPC(); 112 113 InstSeqNum readTailSeqNum(); 114 115 /** Checks if the ROB is still in the process of squashing instructions. 116 * @retval Whether or not the ROB is done squashing. 117 */ 118 bool isDoneSquashing() const { return doneSquashing; } 119 120 /** This is more of a debugging function than anything. Use 121 * numInstsInROB to get the instructions in the ROB unless you are 122 * double checking that variable. 123 */ 124 int countInsts(); 125 126 private: 127 128 /** Pointer to the CPU. */ 129 FullCPU *cpu; 130 131 /** Number of instructions in the ROB. */ 132 unsigned numEntries; 133 134 /** Number of instructions that can be squashed in a single cycle. */ 135 unsigned squashWidth; 136 137 /** Iterator pointing to the instruction which is the last instruction 138 * in the ROB. This may at times be invalid (ie when the ROB is empty), 139 * however it should never be incorrect. 140 */ 141 InstIt_t tail; 142 143 /** Iterator used for walking through the list of instructions when 144 * squashing. Used so that there is persistent state between cycles; 145 * when squashing, the instructions are marked as squashed but not 146 * immediately removed, meaning the tail iterator remains the same before 147 * and after a squash. 148 * This will always be set to cpu->instList.end() if it is invalid. 149 */ 150 InstIt_t squashIt; 151 152 /** Number of instructions in the ROB. */ 153 int numInstsInROB; 154 155 /** The sequence number of the squashed instruction. */ 156 InstSeqNum squashedSeqNum; 157 158 /** Is the ROB done squashing. */ 159 bool doneSquashing; 160}; 161 162#endif //__CPU_BETA_CPU_ROB_HH__ 163