rob.hh revision 13562
11689SN/A/* 21689SN/A * Copyright (c) 2012 ARM Limited 31689SN/A * All rights reserved 41689SN/A * 51689SN/A * The license below extends only to copyright in the software and shall 61689SN/A * not be construed as granting a license to any other intellectual 71689SN/A * property including but not limited to intellectual property relating 81689SN/A * to a hardware implementation of the functionality of the software 91689SN/A * licensed hereunder. You may use the software subject to the license 101689SN/A * terms below provided that you ensure that this notice is replicated 111689SN/A * unmodified and in its entirety in all distributions of the software, 121689SN/A * modified or unmodified, in source code or in binary form. 131689SN/A * 141689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371755SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381755SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391060SN/A * 401461SN/A * Authors: Kevin Lim 411461SN/A * Korey Sewell 421060SN/A */ 431060SN/A 441060SN/A#ifndef __CPU_O3_ROB_HH__ 451061SN/A#define __CPU_O3_ROB_HH__ 461061SN/A 471061SN/A#include <string> 481060SN/A#include <utility> 491061SN/A#include <vector> 501060SN/A 511060SN/A#include "arch/registers.hh" 522107SN/A#include "base/types.hh" 532107SN/A#include "config/the_isa.hh" 541060SN/A#include "enums/SMTQueuePolicy.hh" 551060SN/A 561060SN/Astruct DerivO3CPUParams; 571061SN/A 581060SN/A/** 591461SN/A * ROB class. The ROB is largely what drives squashing. 601061SN/A */ 611060SN/Atemplate <class Impl> 621060SN/Aclass ROB 631060SN/A{ 641763SN/A public: 651763SN/A //Typedefs from the Impl. 661060SN/A typedef typename Impl::O3CPU O3CPU; 671060SN/A typedef typename Impl::DynInstPtr DynInstPtr; 681060SN/A 691060SN/A typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 701060SN/A typedef typename std::list<DynInstPtr>::iterator InstIt; 711060SN/A 721763SN/A /** Possible ROB statuses. */ 731060SN/A enum Status { 741060SN/A Running, 751060SN/A Idle, 761060SN/A ROBSquashing 771060SN/A }; 781060SN/A 791060SN/A private: 801763SN/A /** Per-thread ROB status. */ 811060SN/A Status robStatus[Impl::MaxThreads]; 821060SN/A 831061SN/A /** ROB resource sharing policy for SMT mode. */ 841060SN/A SMTQueuePolicy robPolicy; 851060SN/A 861060SN/A public: 871060SN/A /** ROB constructor. 881060SN/A * @param _cpu The cpu object pointer. 891061SN/A * @param params The cpu params including several ROB-specific parameters. 901060SN/A */ 911061SN/A ROB(O3CPU *_cpu, DerivO3CPUParams *params); 921060SN/A 931060SN/A std::string name() const; 941060SN/A 951060SN/A /** Sets pointer to the list of active threads. 961060SN/A * @param at_ptr Pointer to the list of active threads. 971060SN/A */ 981060SN/A void setActiveThreads(std::list<ThreadID> *at_ptr); 991060SN/A 1001060SN/A /** Perform sanity checks after a drain. */ 1011060SN/A void drainSanityCheck() const; 1021060SN/A 1031060SN/A /** Takes over another CPU's thread. */ 1041060SN/A void takeOverFrom(); 1051060SN/A 1061060SN/A /** Function to insert an instruction into the ROB. Note that whatever 1071060SN/A * calls this function must ensure that there is enough space within the 1081060SN/A * ROB for the new instruction. 1091060SN/A * @param inst The instruction being inserted into the ROB. 1101060SN/A */ 1111060SN/A void insertInst(const DynInstPtr &inst); 1121060SN/A 1131060SN/A /** Returns pointer to the head instruction within the ROB. There is 1141060SN/A * no guarantee as to the return value if the ROB is empty. 1151060SN/A * @retval Pointer to the DynInst that is at the head of the ROB. 1161060SN/A */ 1171060SN/A// DynInstPtr readHeadInst(); 1181060SN/A 1191060SN/A /** Returns a pointer to the head instruction of a specific thread within 1201060SN/A * the ROB. 1211060SN/A * @return Pointer to the DynInst that is at the head of the ROB. 1221060SN/A */ 1231060SN/A const DynInstPtr &readHeadInst(ThreadID tid); 1241060SN/A 1251060SN/A /** Returns a pointer to the instruction with the given sequence if it is 1261060SN/A * in the ROB. 1271060SN/A */ 1281060SN/A DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst); 1291060SN/A 1301060SN/A /** Returns pointer to the tail instruction within the ROB. There is 1311060SN/A * no guarantee as to the return value if the ROB is empty. 1321060SN/A * @retval Pointer to the DynInst that is at the tail of the ROB. 1331060SN/A */ 1341060SN/A// DynInstPtr readTailInst(); 1351061SN/A 1361060SN/A /** Returns a pointer to the tail instruction of a specific thread within 1371060SN/A * the ROB. 1381060SN/A * @return Pointer to the DynInst that is at the tail of the ROB. 1391060SN/A */ 1401060SN/A DynInstPtr readTailInst(ThreadID tid); 1411061SN/A 1421061SN/A /** Retires the head instruction, removing it from the ROB. */ 1431061SN/A// void retireHead(); 1441061SN/A 1451061SN/A /** Retires the head instruction of a specific thread, removing it from the 1461060SN/A * ROB. 1471061SN/A */ 1481061SN/A void retireHead(ThreadID tid); 1491061SN/A 1501061SN/A /** Is the oldest instruction across all threads ready. */ 1511061SN/A// bool isHeadReady(); 1521061SN/A 1531061SN/A /** Is the oldest instruction across a particular thread ready. */ 1541061SN/A bool isHeadReady(ThreadID tid); 1551060SN/A 1561061SN/A /** Is there any commitable head instruction across all threads ready. */ 1571060SN/A bool canCommit(); 1581060SN/A 1591060SN/A /** Re-adjust ROB partitioning. */ 1601060SN/A void resetEntries(); 1611060SN/A 1621060SN/A /** Number of entries needed For 'num_threads' amount of threads. */ 1631060SN/A int entryAmount(ThreadID num_threads); 1641060SN/A 1651060SN/A /** Returns the number of total free entries in the ROB. */ 1661755SN/A unsigned numFreeEntries(); 167 168 /** Returns the number of free entries in a specific ROB paritition. */ 169 unsigned numFreeEntries(ThreadID tid); 170 171 /** Returns the maximum number of entries for a specific thread. */ 172 unsigned getMaxEntries(ThreadID tid) 173 { return maxEntries[tid]; } 174 175 /** Returns the number of entries being used by a specific thread. */ 176 unsigned getThreadEntries(ThreadID tid) 177 { return threadEntries[tid]; } 178 179 /** Returns if the ROB is full. */ 180 bool isFull() 181 { return numInstsInROB == numEntries; } 182 183 /** Returns if a specific thread's partition is full. */ 184 bool isFull(ThreadID tid) 185 { return threadEntries[tid] == numEntries; } 186 187 /** Returns if the ROB is empty. */ 188 bool isEmpty() const 189 { return numInstsInROB == 0; } 190 191 /** Returns if a specific thread's partition is empty. */ 192 bool isEmpty(ThreadID tid) const 193 { return threadEntries[tid] == 0; } 194 195 /** Executes the squash, marking squashed instructions. */ 196 void doSquash(ThreadID tid); 197 198 /** Squashes all instructions younger than the given sequence number for 199 * the specific thread. 200 */ 201 void squash(InstSeqNum squash_num, ThreadID tid); 202 203 /** Updates the head instruction with the new oldest instruction. */ 204 void updateHead(); 205 206 /** Updates the tail instruction with the new youngest instruction. */ 207 void updateTail(); 208 209 /** Reads the PC of the oldest head instruction. */ 210// uint64_t readHeadPC(); 211 212 /** Reads the PC of the head instruction of a specific thread. */ 213// uint64_t readHeadPC(ThreadID tid); 214 215 /** Reads the next PC of the oldest head instruction. */ 216// uint64_t readHeadNextPC(); 217 218 /** Reads the next PC of the head instruction of a specific thread. */ 219// uint64_t readHeadNextPC(ThreadID tid); 220 221 /** Reads the sequence number of the oldest head instruction. */ 222// InstSeqNum readHeadSeqNum(); 223 224 /** Reads the sequence number of the head instruction of a specific thread. 225 */ 226// InstSeqNum readHeadSeqNum(ThreadID tid); 227 228 /** Reads the PC of the youngest tail instruction. */ 229// uint64_t readTailPC(); 230 231 /** Reads the PC of the tail instruction of a specific thread. */ 232// uint64_t readTailPC(ThreadID tid); 233 234 /** Reads the sequence number of the youngest tail instruction. */ 235// InstSeqNum readTailSeqNum(); 236 237 /** Reads the sequence number of tail instruction of a specific thread. */ 238// InstSeqNum readTailSeqNum(ThreadID tid); 239 240 /** Checks if the ROB is still in the process of squashing instructions. 241 * @retval Whether or not the ROB is done squashing. 242 */ 243 bool isDoneSquashing(ThreadID tid) const 244 { return doneSquashing[tid]; } 245 246 /** Checks if the ROB is still in the process of squashing instructions for 247 * any thread. 248 */ 249 bool isDoneSquashing(); 250 251 /** This is more of a debugging function than anything. Use 252 * numInstsInROB to get the instructions in the ROB unless you are 253 * double checking that variable. 254 */ 255 int countInsts(); 256 257 /** This is more of a debugging function than anything. Use 258 * threadEntries to get the instructions in the ROB unless you are 259 * double checking that variable. 260 */ 261 int countInsts(ThreadID tid); 262 263 /** Registers statistics. */ 264 void regStats(); 265 266 private: 267 /** Reset the ROB state */ 268 void resetState(); 269 270 /** Pointer to the CPU. */ 271 O3CPU *cpu; 272 273 /** Active Threads in CPU */ 274 std::list<ThreadID> *activeThreads; 275 276 /** Number of instructions in the ROB. */ 277 unsigned numEntries; 278 279 /** Entries Per Thread */ 280 unsigned threadEntries[Impl::MaxThreads]; 281 282 /** Max Insts a Thread Can Have in the ROB */ 283 unsigned maxEntries[Impl::MaxThreads]; 284 285 /** ROB List of Instructions */ 286 std::list<DynInstPtr> instList[Impl::MaxThreads]; 287 288 /** Number of instructions that can be squashed in a single cycle. */ 289 unsigned squashWidth; 290 291 public: 292 /** Iterator pointing to the instruction which is the last instruction 293 * in the ROB. This may at times be invalid (ie when the ROB is empty), 294 * however it should never be incorrect. 295 */ 296 InstIt tail; 297 298 /** Iterator pointing to the instruction which is the first instruction in 299 * in the ROB*/ 300 InstIt head; 301 302 private: 303 /** Iterator used for walking through the list of instructions when 304 * squashing. Used so that there is persistent state between cycles; 305 * when squashing, the instructions are marked as squashed but not 306 * immediately removed, meaning the tail iterator remains the same before 307 * and after a squash. 308 * This will always be set to cpu->instList.end() if it is invalid. 309 */ 310 InstIt squashIt[Impl::MaxThreads]; 311 312 public: 313 /** Number of instructions in the ROB. */ 314 int numInstsInROB; 315 316 /** Dummy instruction returned if there are no insts left. */ 317 DynInstPtr dummyInst; 318 319 private: 320 /** The sequence number of the squashed instruction. */ 321 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 322 323 /** Is the ROB done squashing. */ 324 bool doneSquashing[Impl::MaxThreads]; 325 326 /** Number of active threads. */ 327 ThreadID numThreads; 328 329 // The number of rob_reads 330 Stats::Scalar robReads; 331 // The number of rob_writes 332 Stats::Scalar robWrites; 333}; 334 335#endif //__CPU_O3_ROB_HH__ 336