rob.hh revision 13429
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412831Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_ROB_HH__ 452292SN/A#define __CPU_O3_ROB_HH__ 461060SN/A 472292SN/A#include <string> 481461SN/A#include <utility> 491461SN/A#include <vector> 501060SN/A 518230Snate@binkert.org#include "arch/registers.hh" 528230Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 546658Snate@binkert.org 559954SFaissal.Sleiman@arm.comstruct DerivO3CPUParams; 569954SFaissal.Sleiman@arm.com 571060SN/A/** 582292SN/A * ROB class. The ROB is largely what drives squashing. 591060SN/A */ 601061SN/Atemplate <class Impl> 611060SN/Aclass ROB 621060SN/A{ 631060SN/A public: 641060SN/A //Typedefs from the Impl. 652733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 661061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 671060SN/A 682292SN/A typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 692292SN/A typedef typename std::list<DynInstPtr>::iterator InstIt; 702292SN/A 712292SN/A /** Possible ROB statuses. */ 722292SN/A enum Status { 732292SN/A Running, 742292SN/A Idle, 752329SN/A ROBSquashing 762292SN/A }; 772292SN/A 782292SN/A /** SMT ROB Sharing Policy */ 792292SN/A enum ROBPolicy{ 802292SN/A Dynamic, 812292SN/A Partitioned, 822292SN/A Threshold 832292SN/A }; 842292SN/A 852292SN/A private: 862292SN/A /** Per-thread ROB status. */ 872292SN/A Status robStatus[Impl::MaxThreads]; 882292SN/A 892292SN/A /** ROB resource sharing policy for SMT mode. */ 902292SN/A ROBPolicy robPolicy; 911060SN/A 921060SN/A public: 931060SN/A /** ROB constructor. 949954SFaissal.Sleiman@arm.com * @param _cpu The cpu object pointer. 959954SFaissal.Sleiman@arm.com * @param params The cpu params including several ROB-specific parameters. 961060SN/A */ 979954SFaissal.Sleiman@arm.com ROB(O3CPU *_cpu, DerivO3CPUParams *params); 982292SN/A 992292SN/A std::string name() const; 1001060SN/A 1012292SN/A /** Sets pointer to the list of active threads. 1022292SN/A * @param at_ptr Pointer to the list of active threads. 1032292SN/A */ 1046221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1052292SN/A 1069444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 1079444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1082307SN/A 1092348SN/A /** Takes over another CPU's thread. */ 1102307SN/A void takeOverFrom(); 1112307SN/A 1122292SN/A /** Function to insert an instruction into the ROB. Note that whatever 1132292SN/A * calls this function must ensure that there is enough space within the 1142292SN/A * ROB for the new instruction. 1151763SN/A * @param inst The instruction being inserted into the ROB. 1161060SN/A */ 11713429Srekai.gonzalezalberquilla@arm.com void insertInst(const DynInstPtr &inst); 1181060SN/A 1191060SN/A /** Returns pointer to the head instruction within the ROB. There is 1201060SN/A * no guarantee as to the return value if the ROB is empty. 1211060SN/A * @retval Pointer to the DynInst that is at the head of the ROB. 1221060SN/A */ 1232329SN/A// DynInstPtr readHeadInst(); 1241060SN/A 1252292SN/A /** Returns a pointer to the head instruction of a specific thread within 1262292SN/A * the ROB. 1272292SN/A * @return Pointer to the DynInst that is at the head of the ROB. 1282292SN/A */ 12913429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &readHeadInst(ThreadID tid); 1301060SN/A 1318822Snilay@cs.wisc.edu /** Returns a pointer to the instruction with the given sequence if it is 1328822Snilay@cs.wisc.edu * in the ROB. 1338822Snilay@cs.wisc.edu */ 1348822Snilay@cs.wisc.edu DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst); 1358822Snilay@cs.wisc.edu 1362292SN/A /** Returns pointer to the tail instruction within the ROB. There is 1372292SN/A * no guarantee as to the return value if the ROB is empty. 1382292SN/A * @retval Pointer to the DynInst that is at the tail of the ROB. 1392292SN/A */ 1402329SN/A// DynInstPtr readTailInst(); 1411060SN/A 1422292SN/A /** Returns a pointer to the tail instruction of a specific thread within 1432292SN/A * the ROB. 1442292SN/A * @return Pointer to the DynInst that is at the tail of the ROB. 1452292SN/A */ 1466221Snate@binkert.org DynInstPtr readTailInst(ThreadID tid); 1471060SN/A 1482292SN/A /** Retires the head instruction, removing it from the ROB. */ 1492329SN/A// void retireHead(); 1502107SN/A 1512292SN/A /** Retires the head instruction of a specific thread, removing it from the 1522292SN/A * ROB. 1532292SN/A */ 1546221Snate@binkert.org void retireHead(ThreadID tid); 1552292SN/A 1562292SN/A /** Is the oldest instruction across all threads ready. */ 1572329SN/A// bool isHeadReady(); 1582107SN/A 1592292SN/A /** Is the oldest instruction across a particular thread ready. */ 1606221Snate@binkert.org bool isHeadReady(ThreadID tid); 1612292SN/A 1622292SN/A /** Is there any commitable head instruction across all threads ready. */ 1632292SN/A bool canCommit(); 1642292SN/A 1652292SN/A /** Re-adjust ROB partitioning. */ 1662292SN/A void resetEntries(); 1672292SN/A 1682292SN/A /** Number of entries needed For 'num_threads' amount of threads. */ 1696221Snate@binkert.org int entryAmount(ThreadID num_threads); 1702292SN/A 1712292SN/A /** Returns the number of total free entries in the ROB. */ 1721060SN/A unsigned numFreeEntries(); 1731060SN/A 1742292SN/A /** Returns the number of free entries in a specific ROB paritition. */ 1756221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 1762292SN/A 1772292SN/A /** Returns the maximum number of entries for a specific thread. */ 1786221Snate@binkert.org unsigned getMaxEntries(ThreadID tid) 1792292SN/A { return maxEntries[tid]; } 1802292SN/A 1812292SN/A /** Returns the number of entries being used by a specific thread. */ 1826221Snate@binkert.org unsigned getThreadEntries(ThreadID tid) 1832292SN/A { return threadEntries[tid]; } 1842292SN/A 1852292SN/A /** Returns if the ROB is full. */ 1861060SN/A bool isFull() 1871060SN/A { return numInstsInROB == numEntries; } 1881060SN/A 1892292SN/A /** Returns if a specific thread's partition is full. */ 1906221Snate@binkert.org bool isFull(ThreadID tid) 1912292SN/A { return threadEntries[tid] == numEntries; } 1922292SN/A 1932292SN/A /** Returns if the ROB is empty. */ 1949444SAndreas.Sandberg@ARM.com bool isEmpty() const 1951060SN/A { return numInstsInROB == 0; } 1961060SN/A 1972292SN/A /** Returns if a specific thread's partition is empty. */ 1989444SAndreas.Sandberg@ARM.com bool isEmpty(ThreadID tid) const 1992292SN/A { return threadEntries[tid] == 0; } 2001060SN/A 2012292SN/A /** Executes the squash, marking squashed instructions. */ 2026221Snate@binkert.org void doSquash(ThreadID tid); 2031060SN/A 2042292SN/A /** Squashes all instructions younger than the given sequence number for 2052292SN/A * the specific thread. 2062292SN/A */ 2076221Snate@binkert.org void squash(InstSeqNum squash_num, ThreadID tid); 2081060SN/A 2092292SN/A /** Updates the head instruction with the new oldest instruction. */ 2102292SN/A void updateHead(); 2111060SN/A 2122292SN/A /** Updates the tail instruction with the new youngest instruction. */ 2132292SN/A void updateTail(); 2141060SN/A 2152292SN/A /** Reads the PC of the oldest head instruction. */ 2162329SN/A// uint64_t readHeadPC(); 2171060SN/A 2182292SN/A /** Reads the PC of the head instruction of a specific thread. */ 2196221Snate@binkert.org// uint64_t readHeadPC(ThreadID tid); 2202292SN/A 2212292SN/A /** Reads the next PC of the oldest head instruction. */ 2222329SN/A// uint64_t readHeadNextPC(); 2232107SN/A 2242292SN/A /** Reads the next PC of the head instruction of a specific thread. */ 2256221Snate@binkert.org// uint64_t readHeadNextPC(ThreadID tid); 2262292SN/A 2272292SN/A /** Reads the sequence number of the oldest head instruction. */ 2282329SN/A// InstSeqNum readHeadSeqNum(); 2292107SN/A 2302292SN/A /** Reads the sequence number of the head instruction of a specific thread. 2312292SN/A */ 2326221Snate@binkert.org// InstSeqNum readHeadSeqNum(ThreadID tid); 2332292SN/A 2342292SN/A /** Reads the PC of the youngest tail instruction. */ 2352329SN/A// uint64_t readTailPC(); 2362107SN/A 2372292SN/A /** Reads the PC of the tail instruction of a specific thread. */ 2386221Snate@binkert.org// uint64_t readTailPC(ThreadID tid); 2392292SN/A 2402292SN/A /** Reads the sequence number of the youngest tail instruction. */ 2412329SN/A// InstSeqNum readTailSeqNum(); 2422107SN/A 2432292SN/A /** Reads the sequence number of tail instruction of a specific thread. */ 2446221Snate@binkert.org// InstSeqNum readTailSeqNum(ThreadID tid); 2451060SN/A 2461060SN/A /** Checks if the ROB is still in the process of squashing instructions. 2471060SN/A * @retval Whether or not the ROB is done squashing. 2481060SN/A */ 2496221Snate@binkert.org bool isDoneSquashing(ThreadID tid) const 2502292SN/A { return doneSquashing[tid]; } 2512292SN/A 2522292SN/A /** Checks if the ROB is still in the process of squashing instructions for 2532292SN/A * any thread. 2542292SN/A */ 2552292SN/A bool isDoneSquashing(); 2561060SN/A 2571060SN/A /** This is more of a debugging function than anything. Use 2581060SN/A * numInstsInROB to get the instructions in the ROB unless you are 2591060SN/A * double checking that variable. 2601060SN/A */ 2611060SN/A int countInsts(); 2621060SN/A 2632292SN/A /** This is more of a debugging function than anything. Use 2642292SN/A * threadEntries to get the instructions in the ROB unless you are 2652292SN/A * double checking that variable. 2662292SN/A */ 2676221Snate@binkert.org int countInsts(ThreadID tid); 2682292SN/A 2697897Shestness@cs.utexas.edu /** Registers statistics. */ 2707897Shestness@cs.utexas.edu void regStats(); 2717897Shestness@cs.utexas.edu 2721060SN/A private: 2739444SAndreas.Sandberg@ARM.com /** Reset the ROB state */ 2749444SAndreas.Sandberg@ARM.com void resetState(); 2759444SAndreas.Sandberg@ARM.com 2761060SN/A /** Pointer to the CPU. */ 2772733Sktlim@umich.edu O3CPU *cpu; 2781060SN/A 2792292SN/A /** Active Threads in CPU */ 2806221Snate@binkert.org std::list<ThreadID> *activeThreads; 2812292SN/A 2821061SN/A /** Number of instructions in the ROB. */ 2831060SN/A unsigned numEntries; 2841060SN/A 2852292SN/A /** Entries Per Thread */ 2862292SN/A unsigned threadEntries[Impl::MaxThreads]; 2872292SN/A 2882292SN/A /** Max Insts a Thread Can Have in the ROB */ 2892292SN/A unsigned maxEntries[Impl::MaxThreads]; 2902292SN/A 2912292SN/A /** ROB List of Instructions */ 2922292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2932292SN/A 2941060SN/A /** Number of instructions that can be squashed in a single cycle. */ 2951060SN/A unsigned squashWidth; 2961060SN/A 2972292SN/A public: 2981061SN/A /** Iterator pointing to the instruction which is the last instruction 2991061SN/A * in the ROB. This may at times be invalid (ie when the ROB is empty), 3001061SN/A * however it should never be incorrect. 3011061SN/A */ 3022292SN/A InstIt tail; 3031060SN/A 3042292SN/A /** Iterator pointing to the instruction which is the first instruction in 3052292SN/A * in the ROB*/ 3062292SN/A InstIt head; 3072292SN/A 3082292SN/A private: 3091061SN/A /** Iterator used for walking through the list of instructions when 3101061SN/A * squashing. Used so that there is persistent state between cycles; 3111061SN/A * when squashing, the instructions are marked as squashed but not 3121061SN/A * immediately removed, meaning the tail iterator remains the same before 3131061SN/A * and after a squash. 3141061SN/A * This will always be set to cpu->instList.end() if it is invalid. 3151061SN/A */ 3162292SN/A InstIt squashIt[Impl::MaxThreads]; 3171060SN/A 3182292SN/A public: 3191061SN/A /** Number of instructions in the ROB. */ 3201060SN/A int numInstsInROB; 3211060SN/A 3222348SN/A /** Dummy instruction returned if there are no insts left. */ 3232292SN/A DynInstPtr dummyInst; 3242292SN/A 3252292SN/A private: 3261060SN/A /** The sequence number of the squashed instruction. */ 3272877Sksewell@umich.edu InstSeqNum squashedSeqNum[Impl::MaxThreads]; 3281060SN/A 3291060SN/A /** Is the ROB done squashing. */ 3302292SN/A bool doneSquashing[Impl::MaxThreads]; 3312292SN/A 3322292SN/A /** Number of active threads. */ 3336221Snate@binkert.org ThreadID numThreads; 3347897Shestness@cs.utexas.edu 3357897Shestness@cs.utexas.edu // The number of rob_reads 3367897Shestness@cs.utexas.edu Stats::Scalar robReads; 3377897Shestness@cs.utexas.edu // The number of rob_writes 3387897Shestness@cs.utexas.edu Stats::Scalar robWrites; 3391060SN/A}; 3401060SN/A 3412292SN/A#endif //__CPU_O3_ROB_HH__ 342