rename_map.hh revision 13601:f5c84915eb7f 
1/*
2 * Copyright (c) 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Steve Reinhardt
43 */
44
45#ifndef __CPU_O3_RENAME_MAP_HH__
46#define __CPU_O3_RENAME_MAP_HH__
47
48#include <iostream>
49#include <utility>
50#include <vector>
51
52#include "arch/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/o3/free_list.hh"
55#include "cpu/o3/regfile.hh"
56#include "cpu/reg_class.hh"
57#include "enums/VecRegRenameMode.hh"
58
59/**
60 * Register rename map for a single class of registers (e.g., integer
61 * or floating point).  Because the register class is implicitly
62 * determined by the rename map instance being accessed, all
63 * architectural register index parameters and values in this class
64 * are relative (e.g., %fp2 is just index 2).
65 */
66class SimpleRenameMap
67{
68  private:
69    using Arch2PhysMap = std::vector<PhysRegIdPtr>;
70    /** The acutal arch-to-phys register map */
71    Arch2PhysMap map;
72  public:
73    using iterator = Arch2PhysMap::iterator;
74    using const_iterator = Arch2PhysMap::const_iterator;
75  private:
76
77    /**
78     * Pointer to the free list from which new physical registers
79     * should be allocated in rename()
80     */
81    SimpleFreeList *freeList;
82
83    /**
84     * The architectural index of the zero register. This register is
85     * mapped but read-only, so we ignore attempts to rename it via
86     * the rename() method.  If there is no such register for this map
87     * table, it should be set to an invalid index so that it never
88     * matches.
89     */
90    RegId zeroReg;
91
92  public:
93
94    SimpleRenameMap();
95
96    ~SimpleRenameMap() {};
97
98    /**
99     * Because we have an array of rename maps (one per thread) in the CPU,
100     * it's awkward to initialize this object via the constructor.
101     * Instead, this method is used for initialization.
102     */
103    void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg);
104
105    /**
106     * Pair of a physical register and a physical register.  Used to
107     * return the physical register that a logical register has been
108     * renamed to, and the previous physical register that the same
109     * logical register was previously mapped to.
110     */
111    typedef std::pair<PhysRegIdPtr, PhysRegIdPtr> RenameInfo;
112
113    /**
114     * Tell rename map to get a new free physical register to remap
115     * the specified architectural register.
116     * @param arch_reg The architectural register to remap.
117     * @return A RenameInfo pair indicating both the new and previous
118     * physical registers.
119     */
120    RenameInfo rename(const RegId& arch_reg);
121
122    /**
123     * Look up the physical register mapped to an architectural register.
124     * @param arch_reg The architectural register to look up.
125     * @return The physical register it is currently mapped to.
126     */
127    PhysRegIdPtr lookup(const RegId& arch_reg) const
128    {
129        assert(arch_reg.flatIndex() <= map.size());
130        return map[arch_reg.flatIndex()];
131    }
132
133    /**
134     * Update rename map with a specific mapping.  Generally used to
135     * roll back to old mappings on a squash.
136     * @param arch_reg The architectural register to remap.
137     * @param phys_reg The physical register to remap it to.
138     */
139    void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
140    {
141        assert(arch_reg.flatIndex() <= map.size());
142        map[arch_reg.flatIndex()] = phys_reg;
143    }
144
145    /** Return the number of free entries on the associated free list. */
146    unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
147
148    /** Forward begin/cbegin to the map. */
149    /** @{ */
150    iterator begin() { return map.begin(); }
151    const_iterator begin() const { return map.begin(); }
152    const_iterator cbegin() const { return map.cbegin(); }
153    /** @} */
154
155    /** Forward end/cend to the map. */
156    /** @{ */
157    iterator end() { return map.end(); }
158    const_iterator end() const { return map.end(); }
159    const_iterator cend() const { return map.cend(); }
160    /** @} */
161};
162
163/**
164 * Unified register rename map for all classes of registers.  Wraps a
165 * set of class-specific rename maps.  Methods that do not specify a
166 * register class (e.g., rename()) take register ids,
167 * while methods that do specify a register class (e.g., renameInt())
168 * take register indices.
169 */
170class UnifiedRenameMap
171{
172  private:
173    static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
174    using VecReg = TheISA::VecReg;
175
176    /** The integer register rename map */
177    SimpleRenameMap intMap;
178
179    /** The floating-point register rename map */
180    SimpleRenameMap floatMap;
181
182    /** The condition-code register rename map */
183    SimpleRenameMap ccMap;
184
185    /** The vector register rename map */
186    SimpleRenameMap vecMap;
187
188    /** The vector element register rename map */
189    SimpleRenameMap vecElemMap;
190
191    using VecMode = Enums::VecRegRenameMode;
192    VecMode vecMode;
193
194    /**
195     * The register file object is used only to get PhysRegIdPtr
196     * on MiscRegs, as they are stored in it.
197     */
198    PhysRegFile *regFile;
199
200  public:
201
202    typedef SimpleRenameMap::RenameInfo RenameInfo;
203
204    /** Default constructor.  init() must be called prior to use. */
205    UnifiedRenameMap() : regFile(nullptr) {};
206
207    /** Destructor. */
208    ~UnifiedRenameMap() {};
209
210    /** Initializes rename map with given parameters. */
211    void init(PhysRegFile *_regFile,
212              RegIndex _intZeroReg,
213              RegIndex _floatZeroReg,
214              UnifiedFreeList *freeList,
215              VecMode _mode);
216
217    /**
218     * Tell rename map to get a new free physical register to remap
219     * the specified architectural register. This version takes a
220     * RegId and reads the  appropriate class-specific rename table.
221     * @param arch_reg The architectural register id to remap.
222     * @return A RenameInfo pair indicating both the new and previous
223     * physical registers.
224     */
225    RenameInfo rename(const RegId& arch_reg)
226    {
227        switch (arch_reg.classValue()) {
228          case IntRegClass:
229            return intMap.rename(arch_reg);
230          case FloatRegClass:
231            return floatMap.rename(arch_reg);
232          case VecRegClass:
233            assert(vecMode == Enums::Full);
234            return vecMap.rename(arch_reg);
235          case VecElemClass:
236            assert(vecMode == Enums::Elem);
237            return vecElemMap.rename(arch_reg);
238          case CCRegClass:
239            return ccMap.rename(arch_reg);
240          case MiscRegClass:
241            {
242            // misc regs aren't really renamed, just remapped
243            PhysRegIdPtr phys_reg = lookup(arch_reg);
244            // Set the new register to the previous one to keep the same
245            // mapping throughout the execution.
246            return RenameInfo(phys_reg, phys_reg);
247            }
248
249          default:
250            panic("rename rename(): unknown reg class %s\n",
251                  arch_reg.className());
252        }
253    }
254
255    /**
256     * Look up the physical register mapped to an architectural register.
257     * This version takes a flattened architectural register id
258     * and calls the appropriate class-specific rename table.
259     * @param arch_reg The architectural register to look up.
260     * @return The physical register it is currently mapped to.
261     */
262    PhysRegIdPtr lookup(const RegId& arch_reg) const
263    {
264        switch (arch_reg.classValue()) {
265          case IntRegClass:
266            return intMap.lookup(arch_reg);
267
268          case FloatRegClass:
269            return  floatMap.lookup(arch_reg);
270
271          case VecRegClass:
272            assert(vecMode == Enums::Full);
273            return  vecMap.lookup(arch_reg);
274
275          case VecElemClass:
276            assert(vecMode == Enums::Elem);
277            return  vecElemMap.lookup(arch_reg);
278
279          case CCRegClass:
280            return ccMap.lookup(arch_reg);
281
282          case MiscRegClass:
283            // misc regs aren't really renamed, they keep the same
284            // mapping throughout the execution.
285            return regFile->getMiscRegId(arch_reg.flatIndex());
286
287          default:
288            panic("rename lookup(): unknown reg class %s\n",
289                  arch_reg.className());
290        }
291    }
292
293    /**
294     * Update rename map with a specific mapping.  Generally used to
295     * roll back to old mappings on a squash.  This version takes a
296     * flattened architectural register id and calls the
297     * appropriate class-specific rename table.
298     * @param arch_reg The architectural register to remap.
299     * @param phys_reg The physical register to remap it to.
300     */
301    void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
302    {
303        switch (arch_reg.classValue()) {
304          case IntRegClass:
305            assert(phys_reg->isIntPhysReg());
306            return intMap.setEntry(arch_reg, phys_reg);
307
308          case FloatRegClass:
309            assert(phys_reg->isFloatPhysReg());
310            return floatMap.setEntry(arch_reg, phys_reg);
311
312          case VecRegClass:
313            assert(phys_reg->isVectorPhysReg());
314            assert(vecMode == Enums::Full);
315            return vecMap.setEntry(arch_reg, phys_reg);
316
317          case VecElemClass:
318            assert(phys_reg->isVectorPhysElem());
319            assert(vecMode == Enums::Elem);
320            return vecElemMap.setEntry(arch_reg, phys_reg);
321
322          case CCRegClass:
323            assert(phys_reg->isCCPhysReg());
324            return ccMap.setEntry(arch_reg, phys_reg);
325
326          case MiscRegClass:
327            // Misc registers do not actually rename, so don't change
328            // their mappings.  We end up here when a commit or squash
329            // tries to update or undo a hardwired misc reg nmapping,
330            // which should always be setting it to what it already is.
331            assert(phys_reg == lookup(arch_reg));
332            return;
333
334          default:
335            panic("rename setEntry(): unknown reg class %s\n",
336                  arch_reg.className());
337        }
338    }
339
340    /**
341     * Return the minimum number of free entries across all of the
342     * register classes.  The minimum is used so we guarantee that
343     * this number of entries is available regardless of which class
344     * of registers is requested.
345     */
346    unsigned numFreeEntries() const
347    {
348        return std::min(
349                std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()),
350                vecMode == Enums::Full ? vecMap.numFreeEntries()
351                                    : vecElemMap.numFreeEntries());
352    }
353
354    unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
355    unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
356    unsigned numFreeVecEntries() const
357    {
358        return vecMode == Enums::Full
359                ? vecMap.numFreeEntries()
360                : vecElemMap.numFreeEntries();
361    }
362    unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }
363
364    /**
365     * Return whether there are enough registers to serve the request.
366     */
367    bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
368                    uint32_t vecElemRegs, uint32_t ccRegs) const
369    {
370        return intRegs <= intMap.numFreeEntries() &&
371            floatRegs <= floatMap.numFreeEntries() &&
372            vectorRegs <= vecMap.numFreeEntries() &&
373            vecElemRegs <= vecElemMap.numFreeEntries() &&
374            ccRegs <= ccMap.numFreeEntries();
375    }
376    /**
377     * Set vector mode to Full or Elem.
378     * Ignore 'silent' modifications.
379     *
380     * @param newVecMode new vector renaming mode
381     */
382    void switchMode(VecMode newVecMode);
383
384    /**
385     * Switch freeList of registers from Full to Elem or vicevers
386     * depending on vecMode (vector renaming mode).
387     */
388    void switchFreeList(UnifiedFreeList* freeList);
389
390};
391
392#endif //__CPU_O3_RENAME_MAP_HH__
393