rename_map.cc revision 12857 
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "cpu/o3/rename_map.hh"
45
46#include <vector>
47
48#include "cpu/reg_class.hh"
49#include "debug/Rename.hh"
50
51using namespace std;
52
53/**** SimpleRenameMap methods ****/
54
55SimpleRenameMap::SimpleRenameMap()
56    : freeList(NULL), zeroReg(IntRegClass,0)
57{
58}
59
60
61void
62SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
63                      RegIndex _zeroReg)
64{
65    assert(freeList == NULL);
66    assert(map.empty());
67
68    map.resize(size);
69    freeList = _freeList;
70    zeroReg = RegId(IntRegClass, _zeroReg);
71}
72
73SimpleRenameMap::RenameInfo
74SimpleRenameMap::rename(const RegId& arch_reg)
75{
76    PhysRegIdPtr renamed_reg;
77    // Record the current physical register that is renamed to the
78    // requested architected register.
79    PhysRegIdPtr prev_reg = map[arch_reg.index()];
80
81    // If it's not referencing the zero register, then rename the
82    // register.
83    if (arch_reg != zeroReg) {
84        renamed_reg = freeList->getReg();
85
86        map[arch_reg.index()] = renamed_reg;
87    } else {
88        // Otherwise return the zero register so nothing bad happens.
89        assert(prev_reg->isZeroReg());
90        renamed_reg = prev_reg;
91    }
92
93    DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
94            " %d (%d)\n",
95            arch_reg, renamed_reg->index(), renamed_reg->flatIndex(),
96            prev_reg->index(), prev_reg->flatIndex());
97
98    return RenameInfo(renamed_reg, prev_reg);
99}
100
101
102/**** UnifiedRenameMap methods ****/
103
104void
105UnifiedRenameMap::init(PhysRegFile *_regFile,
106                       RegIndex _intZeroReg,
107                       RegIndex _floatZeroReg,
108                       UnifiedFreeList *freeList,
109                       VecMode _mode)
110{
111    regFile = _regFile;
112    vecMode = _mode;
113
114    intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
115
116    floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
117
118    vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
119
120    vecElemMap.init(TheISA::NumVecRegs * NVecElems,
121            &(freeList->vecElemList), (RegIndex)-1);
122
123    ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
124
125}
126
127void
128UnifiedRenameMap::switchMode(VecMode newVecMode, UnifiedFreeList* freeList)
129{
130    if (newVecMode == Enums::Elem && vecMode == Enums::Full) {
131        /* Switch to vector element rename mode. */
132        /* The free list should currently be tracking full registers. */
133        panic_if(freeList->hasFreeVecElems(),
134                "The free list is already tracking Vec elems");
135        panic_if(freeList->numFreeVecRegs() !=
136                regFile->numVecPhysRegs() - TheISA::NumVecRegs,
137                "The free list has lost vector registers");
138        /* Split the mapping of each arch reg. */
139        int reg = 0;
140        for (auto &e: vecMap) {
141            PhysRegFile::IdRange range = this->regFile->getRegElemIds(e);
142            uint32_t i;
143            for (i = 0; range.first != range.second; i++, range.first++) {
144                vecElemMap.setEntry(RegId(VecElemClass, reg, i),
145                                    &(*range.first));
146            }
147            panic_if(i != NVecElems,
148                "Wrong name of elems: expecting %u, got %d\n",
149                TheISA::NumVecElemPerVecReg, i);
150            reg++;
151        }
152        /* Split the free regs. */
153        while (freeList->hasFreeVecRegs()) {
154            auto vr = freeList->getVecReg();
155            auto range = this->regFile->getRegElemIds(vr);
156            freeList->addRegs(range.first, range.second);
157        }
158        vecMode = Enums::Elem;
159    } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) {
160        /* Switch to full vector register rename mode. */
161        /* The free list should currently be tracking register elems. */
162        panic_if(freeList->hasFreeVecRegs(),
163                "The free list is already tracking full Vec");
164        panic_if(freeList->numFreeVecRegs() !=
165                regFile->numVecElemPhysRegs() - TheISA::NumFloatRegs,
166                "The free list has lost vector register elements");
167        /* To rebuild the arch regs we take the easy road:
168         *  1.- Stitch the elems together into vectors.
169         *  2.- Replace the contents of the register file with the vectors
170         *  3.- Set the remaining registers as free
171         */
172        TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
173        for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
174            VecReg dst = new_RF[i].as<TheISA::VecElem>();
175            for (uint32_t l = 0; l < NVecElems; l++) {
176                RegId s_rid(VecElemClass, i, l);
177                PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
178                dst[l] = regFile->readVecElem(s_prid);
179            }
180        }
181
182        for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
183            PhysRegId pregId(VecRegClass, i, 0);
184            regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
185        }
186
187        auto range = regFile->getRegIds(VecRegClass);
188        freeList->addRegs(range.first + TheISA::NumVecRegs, range.second);
189
190        /* We remove the elems from the free list. */
191        while (freeList->hasFreeVecElems())
192            freeList->getVecElem();
193        vecMode = Enums::Full;
194    }
195}
196