rename_map.cc revision 12104:edd63f9c6184
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Kevin Lim 30 */ 31 32#include "cpu/o3/rename_map.hh" 33 34#include <vector> 35 36#include "debug/Rename.hh" 37 38using namespace std; 39 40/**** SimpleRenameMap methods ****/ 41 42SimpleRenameMap::SimpleRenameMap() 43 : freeList(NULL), zeroReg(0) 44{ 45} 46 47 48void 49SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 50 RegIndex _zeroReg) 51{ 52 assert(freeList == NULL); 53 assert(map.empty()); 54 55 map.resize(size); 56 freeList = _freeList; 57 zeroReg = _zeroReg; 58} 59 60SimpleRenameMap::RenameInfo 61SimpleRenameMap::rename(RegIndex arch_reg) 62{ 63 PhysRegIndex renamed_reg; 64 65 // Record the current physical register that is renamed to the 66 // requested architected register. 67 PhysRegIndex prev_reg = map[arch_reg]; 68 69 // If it's not referencing the zero register, then rename the 70 // register. 71 if (arch_reg != zeroReg) { 72 renamed_reg = freeList->getReg(); 73 74 map[arch_reg] = renamed_reg; 75 } else { 76 // Otherwise return the zero register so nothing bad happens. 77 assert(prev_reg == zeroReg); 78 renamed_reg = zeroReg; 79 } 80 81 DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n", 82 arch_reg, renamed_reg, prev_reg); 83 84 return RenameInfo(renamed_reg, prev_reg); 85} 86 87 88/**** UnifiedRenameMap methods ****/ 89 90void 91UnifiedRenameMap::init(PhysRegFile *_regFile, 92 RegIndex _intZeroReg, 93 RegIndex _floatZeroReg, 94 UnifiedFreeList *freeList) 95{ 96 regFile = _regFile; 97 98 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 99 100 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 101 102 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 103} 104 105 106UnifiedRenameMap::RenameInfo 107UnifiedRenameMap::rename(RegId arch_reg) 108{ 109 switch (arch_reg.regClass) { 110 case IntRegClass: 111 return renameInt(arch_reg.regIdx); 112 113 case FloatRegClass: 114 return renameFloat(arch_reg.regIdx); 115 116 case CCRegClass: 117 return renameCC(arch_reg.regIdx); 118 119 case MiscRegClass: 120 return renameMisc(arch_reg.regIdx); 121 122 default: 123 panic("rename rename(): unknown reg class %s\n", 124 RegClassStrings[arch_reg.regClass]); 125 } 126} 127 128 129PhysRegIndex 130UnifiedRenameMap::lookup(RegId arch_reg) const 131{ 132 switch (arch_reg.regClass) { 133 case IntRegClass: 134 return lookupInt(arch_reg.regIdx); 135 136 case FloatRegClass: 137 return lookupFloat(arch_reg.regIdx); 138 139 case CCRegClass: 140 return lookupCC(arch_reg.regIdx); 141 142 case MiscRegClass: 143 return lookupMisc(arch_reg.regIdx); 144 145 default: 146 panic("rename lookup(): unknown reg class %s\n", 147 RegClassStrings[arch_reg.regClass]); 148 } 149} 150 151void 152UnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIndex phys_reg) 153{ 154 switch (arch_reg.regClass) { 155 case IntRegClass: 156 return setIntEntry(arch_reg.regIdx, phys_reg); 157 158 case FloatRegClass: 159 return setFloatEntry(arch_reg.regIdx, phys_reg); 160 161 case CCRegClass: 162 return setCCEntry(arch_reg.regIdx, phys_reg); 163 164 case MiscRegClass: 165 // Misc registers do not actually rename, so don't change 166 // their mappings. We end up here when a commit or squash 167 // tries to update or undo a hardwired misc reg nmapping, 168 // which should always be setting it to what it already is. 169 assert(phys_reg == lookupMisc(arch_reg.regIdx)); 170 return; 171 172 default: 173 panic("rename setEntry(): unknown reg class %s\n", 174 RegClassStrings[arch_reg.regClass]); 175 } 176} 177