rename_map.cc revision 1464
12SN/A 21762SN/A#include <vector> 32SN/A 42SN/A#include "cpu/beta_cpu/rename_map.hh" 52SN/A 62SN/Ausing namespace std; 72SN/A 82SN/A// Todo: Consider making functions inline. Avoid having things that are 92SN/A// using the zero register or misc registers from adding on the registers 102SN/A// to the free list. Possibly remove the direct communication between 112SN/A// this and the freelist. Considering making inline bool functions that 122SN/A// determine if the register is a logical int, logical fp, physical int, 132SN/A// physical fp, etc. 142SN/A 152SN/ASimpleRenameMap::SimpleRenameMap(unsigned _numLogicalIntRegs, 162SN/A unsigned _numPhysicalIntRegs, 172SN/A unsigned _numLogicalFloatRegs, 182SN/A unsigned _numPhysicalFloatRegs, 192SN/A unsigned _numMiscRegs, 202SN/A RegIndex _intZeroReg, 212SN/A RegIndex _floatZeroReg) 222SN/A : numLogicalIntRegs(_numLogicalIntRegs), 232SN/A numPhysicalIntRegs(_numPhysicalIntRegs), 242SN/A numLogicalFloatRegs(_numLogicalFloatRegs), 252SN/A numPhysicalFloatRegs(_numPhysicalFloatRegs), 262SN/A numMiscRegs(_numMiscRegs), 272665Ssaidi@eecs.umich.edu intZeroReg(_intZeroReg), 282665Ssaidi@eecs.umich.edu floatZeroReg(_floatZeroReg) 292665Ssaidi@eecs.umich.edu{ 302665Ssaidi@eecs.umich.edu DPRINTF(Rename, "Rename: Creating rename map. Phys: %i / %i, Float: " 312SN/A "%i / %i.\n", numLogicalIntRegs, numPhysicalIntRegs, 322SN/A numLogicalFloatRegs, numPhysicalFloatRegs); 332SN/A 342SN/A numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs; 352SN/A 362984Sgblack@eecs.umich.edu numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs; 372171SN/A 382984Sgblack@eecs.umich.edu //Create the rename maps, and their scoreboards. 39146SN/A intRenameMap = new RenameEntry[numLogicalIntRegs]; 40146SN/A floatRenameMap = new RenameEntry[numLogicalRegs]; 41146SN/A 422680Sktlim@umich.edu // Should combine this into one scoreboard. 432SN/A intScoreboard.resize(numPhysicalIntRegs); 442SN/A floatScoreboard.resize(numPhysicalRegs); 452SN/A miscScoreboard.resize(numPhysicalRegs + numMiscRegs); 464088Sbinkertn@umich.edu 475569Snate@binkert.org // Initialize the entries in the integer rename map to point to the 483838Shsul@eecs.umich.edu // physical registers of the same index, and consider each register 493838Shsul@eecs.umich.edu // ready until the first rename occurs. 503838Shsul@eecs.umich.edu for (RegIndex index = 0; index < numLogicalIntRegs; ++index) 513838Shsul@eecs.umich.edu { 525569Snate@binkert.org intRenameMap[index].physical_reg = index; 53860SN/A intScoreboard[index] = 1; 543838Shsul@eecs.umich.edu } 553838Shsul@eecs.umich.edu 56860SN/A // Initialize the rest of the physical registers (the ones that don't 57860SN/A // directly map to a logical register) as unready. 585569Snate@binkert.org for (PhysRegIndex index = numLogicalIntRegs; 591147SN/A index < numPhysicalIntRegs; 605034Smilesck@eecs.umich.edu ++index) 615358Sgblack@eecs.umich.edu { 623838Shsul@eecs.umich.edu intScoreboard[index] = 0; 635004Sgblack@eecs.umich.edu } 645004Sgblack@eecs.umich.edu 654957Sacolyte@umich.edu int float_reg_idx = numPhysicalIntRegs; 663838Shsul@eecs.umich.edu 672SN/A // Initialize the entries in the floating point rename map to point to 683838Shsul@eecs.umich.edu // the physical registers of the same index, and consider each register 693838Shsul@eecs.umich.edu // ready until the first rename occurs. 703838Shsul@eecs.umich.edu // Although the index refers purely to architected registers, because 713838Shsul@eecs.umich.edu // the floating reg indices come after the integer reg indices, they 723838Shsul@eecs.umich.edu // may exceed the size of a normal RegIndex (short). 732SN/A for (PhysRegIndex index = numLogicalIntRegs; 746022Sgblack@eecs.umich.edu index < numLogicalRegs; ++index) 756022Sgblack@eecs.umich.edu { 766022Sgblack@eecs.umich.edu floatRenameMap[index].physical_reg = float_reg_idx++; 776022Sgblack@eecs.umich.edu } 786022Sgblack@eecs.umich.edu 796022Sgblack@eecs.umich.edu for (PhysRegIndex index = numPhysicalIntRegs; 806022Sgblack@eecs.umich.edu index < numPhysicalIntRegs + numLogicalFloatRegs; ++index) 816022Sgblack@eecs.umich.edu { 826022Sgblack@eecs.umich.edu floatScoreboard[index] = 1; 836022Sgblack@eecs.umich.edu } 846022Sgblack@eecs.umich.edu 856022Sgblack@eecs.umich.edu // Initialize the rest of the physical registers (the ones that don't 866022Sgblack@eecs.umich.edu // directly map to a logical register) as unready. 876022Sgblack@eecs.umich.edu for (PhysRegIndex index = numPhysicalIntRegs + numLogicalFloatRegs; 886022Sgblack@eecs.umich.edu index < numPhysicalRegs; 896022Sgblack@eecs.umich.edu ++index) 906022Sgblack@eecs.umich.edu { 916022Sgblack@eecs.umich.edu floatScoreboard[index] = 0; 926022Sgblack@eecs.umich.edu } 936022Sgblack@eecs.umich.edu 946022Sgblack@eecs.umich.edu // Initialize the entries in the misc register scoreboard to be ready. 956022Sgblack@eecs.umich.edu for (PhysRegIndex index = numPhysicalRegs; 966022Sgblack@eecs.umich.edu index < numPhysicalRegs + numMiscRegs; ++index) 976022Sgblack@eecs.umich.edu { 986022Sgblack@eecs.umich.edu miscScoreboard[index] = 1; 996022Sgblack@eecs.umich.edu } 1006022Sgblack@eecs.umich.edu} 1016022Sgblack@eecs.umich.edu 1026022Sgblack@eecs.umich.eduSimpleRenameMap::~SimpleRenameMap() 1036022Sgblack@eecs.umich.edu{ 1046022Sgblack@eecs.umich.edu // Delete the rename maps as they were allocated with new. 1056022Sgblack@eecs.umich.edu delete [] intRenameMap; 1066022Sgblack@eecs.umich.edu delete [] floatRenameMap; 1076022Sgblack@eecs.umich.edu} 1086022Sgblack@eecs.umich.edu 1096022Sgblack@eecs.umich.eduvoid 1106022Sgblack@eecs.umich.eduSimpleRenameMap::setFreeList(SimpleFreeList *fl_ptr) 1116022Sgblack@eecs.umich.edu{ 1126022Sgblack@eecs.umich.edu //Setup the interface to the freelist. 1136022Sgblack@eecs.umich.edu freeList = fl_ptr; 1146022Sgblack@eecs.umich.edu} 1156022Sgblack@eecs.umich.edu 1166022Sgblack@eecs.umich.edu 1176022Sgblack@eecs.umich.edu// Don't allow this stage to fault; force that check to the rename stage. 1186022Sgblack@eecs.umich.edu// Simply ask to rename a logical register and get back a new physical 1196022Sgblack@eecs.umich.edu// register index. 1206022Sgblack@eecs.umich.eduSimpleRenameMap::RenameInfo 1216022Sgblack@eecs.umich.eduSimpleRenameMap::rename(RegIndex arch_reg) 1226022Sgblack@eecs.umich.edu{ 1236022Sgblack@eecs.umich.edu PhysRegIndex renamed_reg; 1246022Sgblack@eecs.umich.edu PhysRegIndex prev_reg; 1256022Sgblack@eecs.umich.edu 1266022Sgblack@eecs.umich.edu if (arch_reg < numLogicalIntRegs) { 1276022Sgblack@eecs.umich.edu 1286022Sgblack@eecs.umich.edu // Record the current physical register that is renamed to the 1296022Sgblack@eecs.umich.edu // requested architected register. 1306022Sgblack@eecs.umich.edu prev_reg = intRenameMap[arch_reg].physical_reg; 1316022Sgblack@eecs.umich.edu 1326022Sgblack@eecs.umich.edu // If it's not referencing the zero register, then mark the register 1336022Sgblack@eecs.umich.edu // as not ready. 1346022Sgblack@eecs.umich.edu if (arch_reg != intZeroReg) { 1356022Sgblack@eecs.umich.edu // Get a free physical register to rename to. 1366022Sgblack@eecs.umich.edu renamed_reg = freeList->getIntReg(); 1376022Sgblack@eecs.umich.edu 1386022Sgblack@eecs.umich.edu // Update the integer rename map. 1396022Sgblack@eecs.umich.edu intRenameMap[arch_reg].physical_reg = renamed_reg; 1406022Sgblack@eecs.umich.edu 1416022Sgblack@eecs.umich.edu assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs); 1426022Sgblack@eecs.umich.edu 1436022Sgblack@eecs.umich.edu // Mark register as not ready. 1446022Sgblack@eecs.umich.edu intScoreboard[renamed_reg] = false; 1456022Sgblack@eecs.umich.edu } else { 1466022Sgblack@eecs.umich.edu // Otherwise return the zero register so nothing bad happens. 1476022Sgblack@eecs.umich.edu renamed_reg = intZeroReg; 1486022Sgblack@eecs.umich.edu } 1496022Sgblack@eecs.umich.edu } else if (arch_reg < numLogicalRegs) { 1506022Sgblack@eecs.umich.edu // Subtract off the base offset for floating point registers. 1516022Sgblack@eecs.umich.edu// arch_reg = arch_reg - numLogicalIntRegs; 1526022Sgblack@eecs.umich.edu 1536022Sgblack@eecs.umich.edu // Record the current physical register that is renamed to the 1546022Sgblack@eecs.umich.edu // requested architected register. 1556022Sgblack@eecs.umich.edu prev_reg = floatRenameMap[arch_reg].physical_reg; 1566022Sgblack@eecs.umich.edu 1576022Sgblack@eecs.umich.edu // If it's not referencing the zero register, then mark the register 1583838Shsul@eecs.umich.edu // as not ready. 1595004Sgblack@eecs.umich.edu if (arch_reg != floatZeroReg) { 1604967Sacolyte@umich.edu // Get a free floating point register to rename to. 1613838Shsul@eecs.umich.edu renamed_reg = freeList->getFloatReg(); 1623838Shsul@eecs.umich.edu 1635004Sgblack@eecs.umich.edu // Update the floating point rename map. 1642SN/A floatRenameMap[arch_reg].physical_reg = renamed_reg; 1655004Sgblack@eecs.umich.edu 1665004Sgblack@eecs.umich.edu assert(renamed_reg < numPhysicalRegs && 1675004Sgblack@eecs.umich.edu renamed_reg >= numPhysicalIntRegs); 1685004Sgblack@eecs.umich.edu 1695004Sgblack@eecs.umich.edu // Mark register as not ready. 1705004Sgblack@eecs.umich.edu floatScoreboard[renamed_reg] = false; 1715004Sgblack@eecs.umich.edu } else { 1725004Sgblack@eecs.umich.edu // Otherwise return the zero register so nothing bad happens. 1735004Sgblack@eecs.umich.edu renamed_reg = floatZeroReg; 1745004Sgblack@eecs.umich.edu } 1755004Sgblack@eecs.umich.edu } else { 1764962Sacolyte@umich.edu // Subtract off the base offset for miscellaneous registers. 1774962Sacolyte@umich.edu arch_reg = arch_reg - numLogicalRegs; 1784962Sacolyte@umich.edu 1794967Sacolyte@umich.edu // No renaming happens to the misc. registers. They are simply the 1804957Sacolyte@umich.edu // registers that come after all the physical registers; thus 1814957Sacolyte@umich.edu // take the base architected register and add the physical registers 1824957Sacolyte@umich.edu // to it. 1834957Sacolyte@umich.edu renamed_reg = arch_reg + numPhysicalRegs; 1845004Sgblack@eecs.umich.edu 1855004Sgblack@eecs.umich.edu // Set the previous register to the same register; mainly it must be 1865004Sgblack@eecs.umich.edu // known that the prev reg was outside the range of normal registers 1875004Sgblack@eecs.umich.edu // so the free list can avoid adding it. 1884957Sacolyte@umich.edu prev_reg = renamed_reg; 1894957Sacolyte@umich.edu 1904957Sacolyte@umich.edu assert(renamed_reg < numPhysicalRegs + numMiscRegs); 1914957Sacolyte@umich.edu 1921413SN/A miscScoreboard[renamed_reg] = false; 1931413SN/A } 1942SN/A 1952SN/A return RenameInfo(renamed_reg, prev_reg); 1963838Shsul@eecs.umich.edu} 1973838Shsul@eecs.umich.edu 1983838Shsul@eecs.umich.edu//Perhaps give this a pair as a return value, of the physical register 1993838Shsul@eecs.umich.edu//and whether or not it's ready. 2002SN/APhysRegIndex 2013838Shsul@eecs.umich.eduSimpleRenameMap::lookup(RegIndex arch_reg) 2025532Ssaidi@eecs.umich.edu{ 2033838Shsul@eecs.umich.edu if (arch_reg < numLogicalIntRegs) { 2045569Snate@binkert.org return intRenameMap[arch_reg].physical_reg; 2055569Snate@binkert.org } else if (arch_reg < numLogicalRegs) { 2063838Shsul@eecs.umich.edu // Subtract off the base FP offset. 2075569Snate@binkert.org// arch_reg = arch_reg - numLogicalIntRegs; 2085569Snate@binkert.org 2095569Snate@binkert.org return floatRenameMap[arch_reg].physical_reg; 2105569Snate@binkert.org } else { 2115569Snate@binkert.org // Subtract off the misc registers offset. 2125569Snate@binkert.org arch_reg = arch_reg - numLogicalRegs; 2135569Snate@binkert.org 2145569Snate@binkert.org // Misc. regs don't rename, so simply add the base arch reg to 2153838Shsul@eecs.umich.edu // the number of physical registers. 2163838Shsul@eecs.umich.edu return numPhysicalRegs + arch_reg; 2176025Snate@binkert.org } 2183838Shsul@eecs.umich.edu} 2193838Shsul@eecs.umich.edu 2203838Shsul@eecs.umich.edubool 2213838Shsul@eecs.umich.eduSimpleRenameMap::isReady(PhysRegIndex phys_reg) 2223838Shsul@eecs.umich.edu{ 2235736Snate@binkert.org if (phys_reg < numPhysicalIntRegs) { 2243838Shsul@eecs.umich.edu return intScoreboard[phys_reg]; 2255569Snate@binkert.org } else if (phys_reg < numPhysicalRegs) { 2265569Snate@binkert.org 2273838Shsul@eecs.umich.edu // Subtract off the base FP offset. 228924SN/A// phys_reg = phys_reg - numPhysicalIntRegs; 2295532Ssaidi@eecs.umich.edu 2305532Ssaidi@eecs.umich.edu return floatScoreboard[phys_reg]; 2315532Ssaidi@eecs.umich.edu } else { 2325532Ssaidi@eecs.umich.edu // Subtract off the misc registers offset. 2335532Ssaidi@eecs.umich.edu// phys_reg = phys_reg - numPhysicalRegs; 2345532Ssaidi@eecs.umich.edu 2352SN/A return miscScoreboard[phys_reg]; 2363838Shsul@eecs.umich.edu } 2373838Shsul@eecs.umich.edu} 2382SN/A 2392SN/A// In this implementation the miscellaneous registers do not actually rename, 2403838Shsul@eecs.umich.edu// so this function does not allow you to try to change their mappings. 2413838Shsul@eecs.umich.eduvoid 2425004Sgblack@eecs.umich.eduSimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg) 2433838Shsul@eecs.umich.edu{ 2444957Sacolyte@umich.edu if (arch_reg < numLogicalIntRegs) { 2453838Shsul@eecs.umich.edu DPRINTF(Rename, "Rename Map: Integer register %i being set to %i.\n", 2463838Shsul@eecs.umich.edu (int)arch_reg, renamed_reg); 2473838Shsul@eecs.umich.edu 2483838Shsul@eecs.umich.edu intRenameMap[arch_reg].physical_reg = renamed_reg; 2493838Shsul@eecs.umich.edu } else { 2503838Shsul@eecs.umich.edu assert(arch_reg < (numLogicalIntRegs + numLogicalFloatRegs)); 2513838Shsul@eecs.umich.edu 2523838Shsul@eecs.umich.edu DPRINTF(Rename, "Rename Map: Float register %i being set to %i.\n", 2533838Shsul@eecs.umich.edu (int)arch_reg - numLogicalIntRegs, renamed_reg); 2543838Shsul@eecs.umich.edu 2553838Shsul@eecs.umich.edu floatRenameMap[arch_reg].physical_reg = renamed_reg; 2563838Shsul@eecs.umich.edu } 2573838Shsul@eecs.umich.edu} 2583838Shsul@eecs.umich.edu 2593838Shsul@eecs.umich.eduvoid 2603838Shsul@eecs.umich.eduSimpleRenameMap::squash(vector<RegIndex> freed_regs, 2613838Shsul@eecs.umich.edu vector<UnmapInfo> unmaps) 2623838Shsul@eecs.umich.edu{ 2633838Shsul@eecs.umich.edu panic("Not sure this function should be called."); 2643838Shsul@eecs.umich.edu 2653838Shsul@eecs.umich.edu // Not sure the rename map should be able to access the free list 2665004Sgblack@eecs.umich.edu // like this. 2673838Shsul@eecs.umich.edu while (!freed_regs.empty()) { 2685004Sgblack@eecs.umich.edu RegIndex free_register = freed_regs.back(); 2693838Shsul@eecs.umich.edu 2703838Shsul@eecs.umich.edu if (free_register < numPhysicalIntRegs) { 2713838Shsul@eecs.umich.edu freeList->addIntReg(free_register); 2723838Shsul@eecs.umich.edu } else { 2733838Shsul@eecs.umich.edu // Subtract off the base FP dependence tag. 2743838Shsul@eecs.umich.edu free_register = free_register - numPhysicalIntRegs; 2753838Shsul@eecs.umich.edu freeList->addFloatReg(free_register); 2763838Shsul@eecs.umich.edu } 2773838Shsul@eecs.umich.edu 2783838Shsul@eecs.umich.edu freed_regs.pop_back(); 2793838Shsul@eecs.umich.edu } 2805004Sgblack@eecs.umich.edu 2814957Sacolyte@umich.edu // Take unmap info and roll back the rename map. 2823838Shsul@eecs.umich.edu} 2833838Shsul@eecs.umich.edu 2843838Shsul@eecs.umich.eduvoid 2853838Shsul@eecs.umich.eduSimpleRenameMap::markAsReady(PhysRegIndex ready_reg) 2863838Shsul@eecs.umich.edu{ 2873838Shsul@eecs.umich.edu DPRINTF(Rename, "Rename map: Marking register %i as ready.\n", 2883838Shsul@eecs.umich.edu (int)ready_reg); 2894957Sacolyte@umich.edu 2903838Shsul@eecs.umich.edu if (ready_reg < numPhysicalIntRegs) { 2913838Shsul@eecs.umich.edu assert(ready_reg >= 0); 2923838Shsul@eecs.umich.edu 2933838Shsul@eecs.umich.edu intScoreboard[ready_reg] = 1; 2945004Sgblack@eecs.umich.edu } else if (ready_reg < numPhysicalRegs) { 2955004Sgblack@eecs.umich.edu 2963838Shsul@eecs.umich.edu // Subtract off the base FP offset. 2973838Shsul@eecs.umich.edu// ready_reg = ready_reg - numPhysicalIntRegs; 2983838Shsul@eecs.umich.edu 2993838Shsul@eecs.umich.edu floatScoreboard[ready_reg] = 1; 3003838Shsul@eecs.umich.edu } else { 3013838Shsul@eecs.umich.edu //Subtract off the misc registers offset. 3025004Sgblack@eecs.umich.edu// ready_reg = ready_reg - numPhysicalRegs; 3035569Snate@binkert.org 3045569Snate@binkert.org miscScoreboard[ready_reg] = 1; 3055004Sgblack@eecs.umich.edu } 3063838Shsul@eecs.umich.edu} 3073453Sgblack@eecs.umich.edu 3083453Sgblack@eecs.umich.eduint 3093838Shsul@eecs.umich.eduSimpleRenameMap::numFreeEntries() 3102SN/A{ 3113838Shsul@eecs.umich.edu int free_int_regs = freeList->numFreeIntRegs(); 3123838Shsul@eecs.umich.edu int free_float_regs = freeList->numFreeFloatRegs(); 3133838Shsul@eecs.umich.edu 3144957Sacolyte@umich.edu if (free_int_regs < free_float_regs) { 3153838Shsul@eecs.umich.edu return free_int_regs; 3162SN/A } else { 3173838Shsul@eecs.umich.edu return free_float_regs; 3183838Shsul@eecs.umich.edu } 3193838Shsul@eecs.umich.edu} 3202SN/A