rename_map.cc revision 13843
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2016-2017,2019 ARM Limited 36657Snate@binkert.org * All rights reserved 46657Snate@binkert.org * 56657Snate@binkert.org * The license below extends only to copyright in the software and shall 66657Snate@binkert.org * not be construed as granting a license to any other intellectual 76657Snate@binkert.org * property including but not limited to intellectual property relating 86657Snate@binkert.org * to a hardware implementation of the functionality of the software 96657Snate@binkert.org * licensed hereunder. You may use the software subject to the license 106657Snate@binkert.org * terms below provided that you ensure that this notice is replicated 116657Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 126657Snate@binkert.org * modified or unmodified, in source code or in binary form. 136657Snate@binkert.org * 146657Snate@binkert.org * Copyright (c) 2004-2005 The Regents of The University of Michigan 156657Snate@binkert.org * Copyright (c) 2013 Advanced Micro Devices, Inc. 166657Snate@binkert.org * All rights reserved. 176657Snate@binkert.org * 186657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 196657Snate@binkert.org * modification, are permitted provided that the following conditions are 206657Snate@binkert.org * met: redistributions of source code must retain the above copyright 216657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 226657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 236657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 246657Snate@binkert.org * documentation and/or other materials provided with the distribution; 256657Snate@binkert.org * neither the name of the copyright holders nor the names of its 266657Snate@binkert.org * contributors may be used to endorse or promote products derived from 276657Snate@binkert.org * this software without specific prior written permission. 286657Snate@binkert.org * 296657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#include "cpu/o3/rename_map.hh" 45 46#include <vector> 47 48#include "cpu/reg_class.hh" 49#include "debug/Rename.hh" 50 51using namespace std; 52 53/**** SimpleRenameMap methods ****/ 54 55SimpleRenameMap::SimpleRenameMap() 56 : freeList(NULL), zeroReg(IntRegClass,0) 57{ 58} 59 60 61void 62SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 63 RegIndex _zeroReg) 64{ 65 assert(freeList == NULL); 66 assert(map.empty()); 67 68 map.resize(size); 69 freeList = _freeList; 70 zeroReg = RegId(IntRegClass, _zeroReg); 71} 72 73SimpleRenameMap::RenameInfo 74SimpleRenameMap::rename(const RegId& arch_reg) 75{ 76 PhysRegIdPtr renamed_reg; 77 // Record the current physical register that is renamed to the 78 // requested architected register. 79 PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()]; 80 81 // If it's not referencing the zero register, then rename the 82 // register. 83 if (arch_reg != zeroReg) { 84 renamed_reg = freeList->getReg(); 85 86 map[arch_reg.flatIndex()] = renamed_reg; 87 } else { 88 // Otherwise return the zero register so nothing bad happens. 89 assert(prev_reg->isZeroReg()); 90 renamed_reg = prev_reg; 91 } 92 93 DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" 94 " %d (%d)\n", 95 arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(), 96 prev_reg->flatIndex(), prev_reg->flatIndex()); 97 98 return RenameInfo(renamed_reg, prev_reg); 99} 100 101 102/**** UnifiedRenameMap methods ****/ 103 104void 105UnifiedRenameMap::init(PhysRegFile *_regFile, 106 RegIndex _intZeroReg, 107 RegIndex _floatZeroReg, 108 UnifiedFreeList *freeList, 109 VecMode _mode) 110{ 111 regFile = _regFile; 112 vecMode = _mode; 113 114 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 115 116 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 117 118 vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1); 119 120 vecElemMap.init(TheISA::NumVecRegs * NVecElems, 121 &(freeList->vecElemList), (RegIndex)-1); 122 123 predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1); 124 125 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 126 127} 128 129void 130UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList) 131{ 132 if (vecMode == Enums::Elem) { 133 134 /* The free list should currently be tracking full registers. */ 135 panic_if(freeList->hasFreeVecElems(), 136 "The free list is already tracking Vec elems"); 137 panic_if(freeList->numFreeVecRegs() != 138 regFile->numVecPhysRegs() - TheISA::NumVecRegs, 139 "The free list has lost vector registers"); 140 141 /* Split the free regs. */ 142 while (freeList->hasFreeVecRegs()) { 143 auto vr = freeList->getVecReg(); 144 auto range = this->regFile->getRegElemIds(vr); 145 freeList->addRegs(range.first, range.second); 146 } 147 148 } else if (vecMode == Enums::Full) { 149 150 /* The free list should currently be tracking register elems. */ 151 panic_if(freeList->hasFreeVecRegs(), 152 "The free list is already tracking full Vec"); 153 panic_if(freeList->numFreeVecElems() != 154 regFile->numVecElemPhysRegs() - 155 TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg, 156 "The free list has lost vector register elements"); 157 158 auto range = regFile->getRegIds(VecRegClass); 159 freeList->addRegs(range.first + TheISA::NumVecRegs, range.second); 160 161 /* We remove the elems from the free list. */ 162 while (freeList->hasFreeVecElems()) 163 freeList->getVecElem(); 164 } 165} 166 167void 168UnifiedRenameMap::switchMode(VecMode newVecMode) 169{ 170 if (newVecMode == Enums::Elem && vecMode == Enums::Full) { 171 172 /* Switch to vector element rename mode. */ 173 vecMode = Enums::Elem; 174 175 /* Split the mapping of each arch reg. */ 176 int vec_idx = 0; 177 for (auto &vec: vecMap) { 178 PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec); 179 auto idx = 0; 180 for (auto phys_elem = range.first; 181 phys_elem < range.second; idx++, phys_elem++) { 182 183 setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem)); 184 } 185 vec_idx++; 186 } 187 188 } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) { 189 190 /* Switch to full vector register rename mode. */ 191 vecMode = Enums::Full; 192 193 /* To rebuild the arch regs we take the easy road: 194 * 1.- Stitch the elems together into vectors. 195 * 2.- Replace the contents of the register file with the vectors 196 * 3.- Set the remaining registers as free 197 */ 198 TheISA::VecRegContainer new_RF[TheISA::NumVecRegs]; 199 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) { 200 VecReg dst = new_RF[i].as<TheISA::VecElem>(); 201 for (uint32_t l = 0; l < NVecElems; l++) { 202 RegId s_rid(VecElemClass, i, l); 203 PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid); 204 dst[l] = regFile->readVecElem(s_prid); 205 } 206 } 207 208 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) { 209 PhysRegId pregId(VecRegClass, i, 0); 210 regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]); 211 } 212 213 } 214} 215