rename_map.cc revision 11793 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 */
31
32#include "cpu/o3/rename_map.hh"
33
34#include <vector>
35
36#include "debug/Rename.hh"
37
38using namespace std;
39
40/**** SimpleRenameMap methods ****/
41
42SimpleRenameMap::SimpleRenameMap()
43    : freeList(NULL), zeroReg(0)
44{
45}
46
47
48void
49SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
50                      RegIndex _zeroReg)
51{
52    assert(freeList == NULL);
53    assert(map.empty());
54
55    map.resize(size);
56    freeList = _freeList;
57    zeroReg = _zeroReg;
58}
59
60SimpleRenameMap::RenameInfo
61SimpleRenameMap::rename(RegIndex arch_reg)
62{
63    PhysRegIndex renamed_reg;
64
65    // Record the current physical register that is renamed to the
66    // requested architected register.
67    PhysRegIndex prev_reg = map[arch_reg];
68
69    // If it's not referencing the zero register, then rename the
70    // register.
71    if (arch_reg != zeroReg) {
72        renamed_reg = freeList->getReg();
73
74        map[arch_reg] = renamed_reg;
75    } else {
76        // Otherwise return the zero register so nothing bad happens.
77        assert(prev_reg == zeroReg);
78        renamed_reg = zeroReg;
79    }
80
81    DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
82            arch_reg, renamed_reg, prev_reg);
83
84    return RenameInfo(renamed_reg, prev_reg);
85}
86
87
88/**** UnifiedRenameMap methods ****/
89
90void
91UnifiedRenameMap::init(PhysRegFile *_regFile,
92                       RegIndex _intZeroReg,
93                       RegIndex _floatZeroReg,
94                       UnifiedFreeList *freeList)
95{
96    regFile = _regFile;
97
98    intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
99
100    floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
101
102    ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
103}
104
105
106UnifiedRenameMap::RenameInfo
107UnifiedRenameMap::rename(RegIndex arch_reg)
108{
109    RegIndex rel_arch_reg;
110
111    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
112      case IntRegClass:
113        return renameInt(rel_arch_reg);
114
115      case FloatRegClass:
116        return renameFloat(rel_arch_reg);
117
118      case CCRegClass:
119        return renameCC(rel_arch_reg);
120
121      case MiscRegClass:
122        return renameMisc(rel_arch_reg);
123
124      default:
125        panic("rename rename(): unknown reg class %s\n",
126              RegClassStrings[regIdxToClass(arch_reg)]);
127    }
128}
129
130
131PhysRegIndex
132UnifiedRenameMap::lookup(RegIndex arch_reg) const
133{
134    RegIndex rel_arch_reg;
135
136    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
137      case IntRegClass:
138        return lookupInt(rel_arch_reg);
139
140      case FloatRegClass:
141        return lookupFloat(rel_arch_reg);
142
143      case CCRegClass:
144        return lookupCC(rel_arch_reg);
145
146      case MiscRegClass:
147        return lookupMisc(rel_arch_reg);
148
149      default:
150        panic("rename lookup(): unknown reg class %s\n",
151              RegClassStrings[regIdxToClass(arch_reg)]);
152    }
153}
154
155void
156UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
157{
158    RegIndex rel_arch_reg;
159
160    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
161      case IntRegClass:
162        return setIntEntry(rel_arch_reg, phys_reg);
163
164      case FloatRegClass:
165        return setFloatEntry(rel_arch_reg, phys_reg);
166
167      case CCRegClass:
168        return setCCEntry(rel_arch_reg, phys_reg);
169
170      case MiscRegClass:
171        // Misc registers do not actually rename, so don't change
172        // their mappings.  We end up here when a commit or squash
173        // tries to update or undo a hardwired misc reg nmapping,
174        // which should always be setting it to what it already is.
175        assert(phys_reg == lookupMisc(rel_arch_reg));
176        return;
177
178      default:
179        panic("rename setEntry(): unknown reg class %s\n",
180              RegClassStrings[regIdxToClass(arch_reg)]);
181    }
182}
183