rename_impl.hh revision 9920:028e4da64b42
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#include <list> 46 47#include "arch/isa_traits.hh" 48#include "arch/registers.hh" 49#include "config/the_isa.hh" 50#include "cpu/o3/rename.hh" 51#include "cpu/reg_class.hh" 52#include "debug/Activity.hh" 53#include "debug/Rename.hh" 54#include "debug/O3PipeView.hh" 55#include "params/DerivO3CPU.hh" 56 57using namespace std; 58 59template <class Impl> 60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 61 : cpu(_cpu), 62 iewToRenameDelay(params->iewToRenameDelay), 63 decodeToRenameDelay(params->decodeToRenameDelay), 64 commitToRenameDelay(params->commitToRenameDelay), 65 renameWidth(params->renameWidth), 66 commitWidth(params->commitWidth), 67 numThreads(params->numThreads), 68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 69 + params->numPhysCCRegs) 70{ 71 // @todo: Make into a parameter. 72 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 73} 74 75template <class Impl> 76std::string 77DefaultRename<Impl>::name() const 78{ 79 return cpu->name() + ".rename"; 80} 81 82template <class Impl> 83void 84DefaultRename<Impl>::regStats() 85{ 86 renameSquashCycles 87 .name(name() + ".SquashCycles") 88 .desc("Number of cycles rename is squashing") 89 .prereq(renameSquashCycles); 90 renameIdleCycles 91 .name(name() + ".IdleCycles") 92 .desc("Number of cycles rename is idle") 93 .prereq(renameIdleCycles); 94 renameBlockCycles 95 .name(name() + ".BlockCycles") 96 .desc("Number of cycles rename is blocking") 97 .prereq(renameBlockCycles); 98 renameSerializeStallCycles 99 .name(name() + ".serializeStallCycles") 100 .desc("count of cycles rename stalled for serializing inst") 101 .flags(Stats::total); 102 renameRunCycles 103 .name(name() + ".RunCycles") 104 .desc("Number of cycles rename is running") 105 .prereq(renameIdleCycles); 106 renameUnblockCycles 107 .name(name() + ".UnblockCycles") 108 .desc("Number of cycles rename is unblocking") 109 .prereq(renameUnblockCycles); 110 renameRenamedInsts 111 .name(name() + ".RenamedInsts") 112 .desc("Number of instructions processed by rename") 113 .prereq(renameRenamedInsts); 114 renameSquashedInsts 115 .name(name() + ".SquashedInsts") 116 .desc("Number of squashed instructions processed by rename") 117 .prereq(renameSquashedInsts); 118 renameROBFullEvents 119 .name(name() + ".ROBFullEvents") 120 .desc("Number of times rename has blocked due to ROB full") 121 .prereq(renameROBFullEvents); 122 renameIQFullEvents 123 .name(name() + ".IQFullEvents") 124 .desc("Number of times rename has blocked due to IQ full") 125 .prereq(renameIQFullEvents); 126 renameLSQFullEvents 127 .name(name() + ".LSQFullEvents") 128 .desc("Number of times rename has blocked due to LSQ full") 129 .prereq(renameLSQFullEvents); 130 renameFullRegistersEvents 131 .name(name() + ".FullRegisterEvents") 132 .desc("Number of times there has been no free registers") 133 .prereq(renameFullRegistersEvents); 134 renameRenamedOperands 135 .name(name() + ".RenamedOperands") 136 .desc("Number of destination operands rename has renamed") 137 .prereq(renameRenamedOperands); 138 renameRenameLookups 139 .name(name() + ".RenameLookups") 140 .desc("Number of register rename lookups that rename has made") 141 .prereq(renameRenameLookups); 142 renameCommittedMaps 143 .name(name() + ".CommittedMaps") 144 .desc("Number of HB maps that are committed") 145 .prereq(renameCommittedMaps); 146 renameUndoneMaps 147 .name(name() + ".UndoneMaps") 148 .desc("Number of HB maps that are undone due to squashing") 149 .prereq(renameUndoneMaps); 150 renamedSerializing 151 .name(name() + ".serializingInsts") 152 .desc("count of serializing insts renamed") 153 .flags(Stats::total) 154 ; 155 renamedTempSerializing 156 .name(name() + ".tempSerializingInsts") 157 .desc("count of temporary serializing insts renamed") 158 .flags(Stats::total) 159 ; 160 renameSkidInsts 161 .name(name() + ".skidInsts") 162 .desc("count of insts added to the skid buffer") 163 .flags(Stats::total) 164 ; 165 intRenameLookups 166 .name(name() + ".int_rename_lookups") 167 .desc("Number of integer rename lookups") 168 .prereq(intRenameLookups); 169 fpRenameLookups 170 .name(name() + ".fp_rename_lookups") 171 .desc("Number of floating rename lookups") 172 .prereq(fpRenameLookups); 173} 174 175template <class Impl> 176void 177DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 178{ 179 timeBuffer = tb_ptr; 180 181 // Setup wire to read information from time buffer, from IEW stage. 182 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 183 184 // Setup wire to read infromation from time buffer, from commit stage. 185 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 186 187 // Setup wire to write information to previous stages. 188 toDecode = timeBuffer->getWire(0); 189} 190 191template <class Impl> 192void 193DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 194{ 195 renameQueue = rq_ptr; 196 197 // Setup wire to write information to future stages. 198 toIEW = renameQueue->getWire(0); 199} 200 201template <class Impl> 202void 203DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 204{ 205 decodeQueue = dq_ptr; 206 207 // Setup wire to get information from decode. 208 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 209} 210 211template <class Impl> 212void 213DefaultRename<Impl>::startupStage() 214{ 215 resetStage(); 216} 217 218template <class Impl> 219void 220DefaultRename<Impl>::resetStage() 221{ 222 _status = Inactive; 223 224 resumeSerialize = false; 225 resumeUnblocking = false; 226 227 // Grab the number of free entries directly from the stages. 228 for (ThreadID tid = 0; tid < numThreads; tid++) { 229 renameStatus[tid] = Idle; 230 231 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 232 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 233 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 234 emptyROB[tid] = true; 235 236 stalls[tid].iew = false; 237 stalls[tid].commit = false; 238 serializeInst[tid] = NULL; 239 240 instsInProgress[tid] = 0; 241 242 serializeOnNextInst[tid] = false; 243 } 244} 245 246template<class Impl> 247void 248DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 249{ 250 activeThreads = at_ptr; 251} 252 253 254template <class Impl> 255void 256DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 257{ 258 for (ThreadID tid = 0; tid < numThreads; tid++) 259 renameMap[tid] = &rm_ptr[tid]; 260} 261 262template <class Impl> 263void 264DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 265{ 266 freeList = fl_ptr; 267} 268 269template<class Impl> 270void 271DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 272{ 273 scoreboard = _scoreboard; 274} 275 276template <class Impl> 277bool 278DefaultRename<Impl>::isDrained() const 279{ 280 for (ThreadID tid = 0; tid < numThreads; tid++) { 281 if (instsInProgress[tid] != 0 || 282 !historyBuffer[tid].empty() || 283 !skidBuffer[tid].empty() || 284 !insts[tid].empty()) 285 return false; 286 } 287 return true; 288} 289 290template <class Impl> 291void 292DefaultRename<Impl>::takeOverFrom() 293{ 294 resetStage(); 295} 296 297template <class Impl> 298void 299DefaultRename<Impl>::drainSanityCheck() const 300{ 301 for (ThreadID tid = 0; tid < numThreads; tid++) { 302 assert(historyBuffer[tid].empty()); 303 assert(insts[tid].empty()); 304 assert(skidBuffer[tid].empty()); 305 assert(instsInProgress[tid] == 0); 306 } 307} 308 309template <class Impl> 310void 311DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 312{ 313 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 314 315 // Clear the stall signal if rename was blocked or unblocking before. 316 // If it still needs to block, the blocking should happen the next 317 // cycle and there should be space to hold everything due to the squash. 318 if (renameStatus[tid] == Blocked || 319 renameStatus[tid] == Unblocking) { 320 toDecode->renameUnblock[tid] = 1; 321 322 resumeSerialize = false; 323 serializeInst[tid] = NULL; 324 } else if (renameStatus[tid] == SerializeStall) { 325 if (serializeInst[tid]->seqNum <= squash_seq_num) { 326 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 327 resumeSerialize = true; 328 assert(serializeInst[tid]); 329 } else { 330 resumeSerialize = false; 331 toDecode->renameUnblock[tid] = 1; 332 333 serializeInst[tid] = NULL; 334 } 335 } 336 337 // Set the status to Squashing. 338 renameStatus[tid] = Squashing; 339 340 // Squash any instructions from decode. 341 unsigned squashCount = 0; 342 343 for (int i=0; i<fromDecode->size; i++) { 344 if (fromDecode->insts[i]->threadNumber == tid && 345 fromDecode->insts[i]->seqNum > squash_seq_num) { 346 fromDecode->insts[i]->setSquashed(); 347 wroteToTimeBuffer = true; 348 squashCount++; 349 } 350 351 } 352 353 // Clear the instruction list and skid buffer in case they have any 354 // insts in them. 355 insts[tid].clear(); 356 357 // Clear the skid buffer in case it has any data in it. 358 skidBuffer[tid].clear(); 359 360 doSquash(squash_seq_num, tid); 361} 362 363template <class Impl> 364void 365DefaultRename<Impl>::tick() 366{ 367 wroteToTimeBuffer = false; 368 369 blockThisCycle = false; 370 371 bool status_change = false; 372 373 toIEWIndex = 0; 374 375 sortInsts(); 376 377 list<ThreadID>::iterator threads = activeThreads->begin(); 378 list<ThreadID>::iterator end = activeThreads->end(); 379 380 // Check stall and squash signals. 381 while (threads != end) { 382 ThreadID tid = *threads++; 383 384 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 385 386 status_change = checkSignalsAndUpdate(tid) || status_change; 387 388 rename(status_change, tid); 389 } 390 391 if (status_change) { 392 updateStatus(); 393 } 394 395 if (wroteToTimeBuffer) { 396 DPRINTF(Activity, "Activity this cycle.\n"); 397 cpu->activityThisCycle(); 398 } 399 400 threads = activeThreads->begin(); 401 402 while (threads != end) { 403 ThreadID tid = *threads++; 404 405 // If we committed this cycle then doneSeqNum will be > 0 406 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 407 !fromCommit->commitInfo[tid].squash && 408 renameStatus[tid] != Squashing) { 409 410 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 411 tid); 412 } 413 } 414 415 // @todo: make into updateProgress function 416 for (ThreadID tid = 0; tid < numThreads; tid++) { 417 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 418 419 assert(instsInProgress[tid] >=0); 420 } 421 422} 423 424template<class Impl> 425void 426DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 427{ 428 // If status is Running or idle, 429 // call renameInsts() 430 // If status is Unblocking, 431 // buffer any instructions coming from decode 432 // continue trying to empty skid buffer 433 // check if stall conditions have passed 434 435 if (renameStatus[tid] == Blocked) { 436 ++renameBlockCycles; 437 } else if (renameStatus[tid] == Squashing) { 438 ++renameSquashCycles; 439 } else if (renameStatus[tid] == SerializeStall) { 440 ++renameSerializeStallCycles; 441 // If we are currently in SerializeStall and resumeSerialize 442 // was set, then that means that we are resuming serializing 443 // this cycle. Tell the previous stages to block. 444 if (resumeSerialize) { 445 resumeSerialize = false; 446 block(tid); 447 toDecode->renameUnblock[tid] = false; 448 } 449 } else if (renameStatus[tid] == Unblocking) { 450 if (resumeUnblocking) { 451 block(tid); 452 resumeUnblocking = false; 453 toDecode->renameUnblock[tid] = false; 454 } 455 } 456 457 if (renameStatus[tid] == Running || 458 renameStatus[tid] == Idle) { 459 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 460 "stage.\n", tid); 461 462 renameInsts(tid); 463 } else if (renameStatus[tid] == Unblocking) { 464 renameInsts(tid); 465 466 if (validInsts()) { 467 // Add the current inputs to the skid buffer so they can be 468 // reprocessed when this stage unblocks. 469 skidInsert(tid); 470 } 471 472 // If we switched over to blocking, then there's a potential for 473 // an overall status change. 474 status_change = unblock(tid) || status_change || blockThisCycle; 475 } 476} 477 478template <class Impl> 479void 480DefaultRename<Impl>::renameInsts(ThreadID tid) 481{ 482 // Instructions can be either in the skid buffer or the queue of 483 // instructions coming from decode, depending on the status. 484 int insts_available = renameStatus[tid] == Unblocking ? 485 skidBuffer[tid].size() : insts[tid].size(); 486 487 // Check the decode queue to see if instructions are available. 488 // If there are no available instructions to rename, then do nothing. 489 if (insts_available == 0) { 490 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 491 tid); 492 // Should I change status to idle? 493 ++renameIdleCycles; 494 return; 495 } else if (renameStatus[tid] == Unblocking) { 496 ++renameUnblockCycles; 497 } else if (renameStatus[tid] == Running) { 498 ++renameRunCycles; 499 } 500 501 DynInstPtr inst; 502 503 // Will have to do a different calculation for the number of free 504 // entries. 505 int free_rob_entries = calcFreeROBEntries(tid); 506 int free_iq_entries = calcFreeIQEntries(tid); 507 int free_lsq_entries = calcFreeLSQEntries(tid); 508 int min_free_entries = free_rob_entries; 509 510 FullSource source = ROB; 511 512 if (free_iq_entries < min_free_entries) { 513 min_free_entries = free_iq_entries; 514 source = IQ; 515 } 516 517 if (free_lsq_entries < min_free_entries) { 518 min_free_entries = free_lsq_entries; 519 source = LSQ; 520 } 521 522 // Check if there's any space left. 523 if (min_free_entries <= 0) { 524 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 525 "entries.\n" 526 "ROB has %i free entries.\n" 527 "IQ has %i free entries.\n" 528 "LSQ has %i free entries.\n", 529 tid, 530 free_rob_entries, 531 free_iq_entries, 532 free_lsq_entries); 533 534 blockThisCycle = true; 535 536 block(tid); 537 538 incrFullStat(source); 539 540 return; 541 } else if (min_free_entries < insts_available) { 542 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 543 "%i insts available, but only %i insts can be " 544 "renamed due to ROB/IQ/LSQ limits.\n", 545 tid, insts_available, min_free_entries); 546 547 insts_available = min_free_entries; 548 549 blockThisCycle = true; 550 551 incrFullStat(source); 552 } 553 554 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 555 skidBuffer[tid] : insts[tid]; 556 557 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 558 "send iew.\n", tid, insts_available); 559 560 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 561 "dispatched to IQ last cycle.\n", 562 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 563 564 // Handle serializing the next instruction if necessary. 565 if (serializeOnNextInst[tid]) { 566 if (emptyROB[tid] && instsInProgress[tid] == 0) { 567 // ROB already empty; no need to serialize. 568 serializeOnNextInst[tid] = false; 569 } else if (!insts_to_rename.empty()) { 570 insts_to_rename.front()->setSerializeBefore(); 571 } 572 } 573 574 int renamed_insts = 0; 575 576 while (insts_available > 0 && toIEWIndex < renameWidth) { 577 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 578 579 assert(!insts_to_rename.empty()); 580 581 inst = insts_to_rename.front(); 582 583 insts_to_rename.pop_front(); 584 585 if (renameStatus[tid] == Unblocking) { 586 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 587 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 588 } 589 590 if (inst->isSquashed()) { 591 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 592 "squashed, skipping.\n", tid, inst->seqNum, 593 inst->pcState()); 594 595 ++renameSquashedInsts; 596 597 // Decrement how many instructions are available. 598 --insts_available; 599 600 continue; 601 } 602 603 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 604 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 605 606 // Check here to make sure there are enough destination registers 607 // to rename to. Otherwise block. 608 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 609 DPRINTF(Rename, "Blocking due to lack of free " 610 "physical registers to rename to.\n"); 611 blockThisCycle = true; 612 insts_to_rename.push_front(inst); 613 ++renameFullRegistersEvents; 614 615 break; 616 } 617 618 // Handle serializeAfter/serializeBefore instructions. 619 // serializeAfter marks the next instruction as serializeBefore. 620 // serializeBefore makes the instruction wait in rename until the ROB 621 // is empty. 622 623 // In this model, IPR accesses are serialize before 624 // instructions, and store conditionals are serialize after 625 // instructions. This is mainly due to lack of support for 626 // out-of-order operations of either of those classes of 627 // instructions. 628 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 629 !inst->isSerializeHandled()) { 630 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 631 632 if (!inst->isTempSerializeBefore()) { 633 renamedSerializing++; 634 inst->setSerializeHandled(); 635 } else { 636 renamedTempSerializing++; 637 } 638 639 // Change status over to SerializeStall so that other stages know 640 // what this is blocked on. 641 renameStatus[tid] = SerializeStall; 642 643 serializeInst[tid] = inst; 644 645 blockThisCycle = true; 646 647 break; 648 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 649 !inst->isSerializeHandled()) { 650 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 651 652 renamedSerializing++; 653 654 inst->setSerializeHandled(); 655 656 serializeAfter(insts_to_rename, tid); 657 } 658 659 renameSrcRegs(inst, inst->threadNumber); 660 661 renameDestRegs(inst, inst->threadNumber); 662 663 ++renamed_insts; 664 665 666 // Put instruction in rename queue. 667 toIEW->insts[toIEWIndex] = inst; 668 ++(toIEW->size); 669 670 // Increment which instruction we're on. 671 ++toIEWIndex; 672 673 // Decrement how many instructions are available. 674 --insts_available; 675 } 676 677 instsInProgress[tid] += renamed_insts; 678 renameRenamedInsts += renamed_insts; 679 680 // If we wrote to the time buffer, record this. 681 if (toIEWIndex) { 682 wroteToTimeBuffer = true; 683 } 684 685 // Check if there's any instructions left that haven't yet been renamed. 686 // If so then block. 687 if (insts_available) { 688 blockThisCycle = true; 689 } 690 691 if (blockThisCycle) { 692 block(tid); 693 toDecode->renameUnblock[tid] = false; 694 } 695} 696 697template<class Impl> 698void 699DefaultRename<Impl>::skidInsert(ThreadID tid) 700{ 701 DynInstPtr inst = NULL; 702 703 while (!insts[tid].empty()) { 704 inst = insts[tid].front(); 705 706 insts[tid].pop_front(); 707 708 assert(tid == inst->threadNumber); 709 710 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 711 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 712 713 ++renameSkidInsts; 714 715 skidBuffer[tid].push_back(inst); 716 } 717 718 if (skidBuffer[tid].size() > skidBufferMax) 719 { 720 typename InstQueue::iterator it; 721 warn("Skidbuffer contents:\n"); 722 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 723 { 724 warn("[tid:%u]: %s [sn:%i].\n", tid, 725 (*it)->staticInst->disassemble(inst->instAddr()), 726 (*it)->seqNum); 727 } 728 panic("Skidbuffer Exceeded Max Size"); 729 } 730} 731 732template <class Impl> 733void 734DefaultRename<Impl>::sortInsts() 735{ 736 int insts_from_decode = fromDecode->size; 737 for (int i = 0; i < insts_from_decode; ++i) { 738 DynInstPtr inst = fromDecode->insts[i]; 739 insts[inst->threadNumber].push_back(inst); 740#if TRACING_ON 741 if (DTRACE(O3PipeView)) { 742 inst->renameTick = curTick() - inst->fetchTick; 743 } 744#endif 745 } 746} 747 748template<class Impl> 749bool 750DefaultRename<Impl>::skidsEmpty() 751{ 752 list<ThreadID>::iterator threads = activeThreads->begin(); 753 list<ThreadID>::iterator end = activeThreads->end(); 754 755 while (threads != end) { 756 ThreadID tid = *threads++; 757 758 if (!skidBuffer[tid].empty()) 759 return false; 760 } 761 762 return true; 763} 764 765template<class Impl> 766void 767DefaultRename<Impl>::updateStatus() 768{ 769 bool any_unblocking = false; 770 771 list<ThreadID>::iterator threads = activeThreads->begin(); 772 list<ThreadID>::iterator end = activeThreads->end(); 773 774 while (threads != end) { 775 ThreadID tid = *threads++; 776 777 if (renameStatus[tid] == Unblocking) { 778 any_unblocking = true; 779 break; 780 } 781 } 782 783 // Rename will have activity if it's unblocking. 784 if (any_unblocking) { 785 if (_status == Inactive) { 786 _status = Active; 787 788 DPRINTF(Activity, "Activating stage.\n"); 789 790 cpu->activateStage(O3CPU::RenameIdx); 791 } 792 } else { 793 // If it's not unblocking, then rename will not have any internal 794 // activity. Switch it to inactive. 795 if (_status == Active) { 796 _status = Inactive; 797 DPRINTF(Activity, "Deactivating stage.\n"); 798 799 cpu->deactivateStage(O3CPU::RenameIdx); 800 } 801 } 802} 803 804template <class Impl> 805bool 806DefaultRename<Impl>::block(ThreadID tid) 807{ 808 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 809 810 // Add the current inputs onto the skid buffer, so they can be 811 // reprocessed when this stage unblocks. 812 skidInsert(tid); 813 814 // Only signal backwards to block if the previous stages do not think 815 // rename is already blocked. 816 if (renameStatus[tid] != Blocked) { 817 // If resumeUnblocking is set, we unblocked during the squash, 818 // but now we're have unblocking status. We need to tell earlier 819 // stages to block. 820 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 821 toDecode->renameBlock[tid] = true; 822 toDecode->renameUnblock[tid] = false; 823 wroteToTimeBuffer = true; 824 } 825 826 // Rename can not go from SerializeStall to Blocked, otherwise 827 // it would not know to complete the serialize stall. 828 if (renameStatus[tid] != SerializeStall) { 829 // Set status to Blocked. 830 renameStatus[tid] = Blocked; 831 return true; 832 } 833 } 834 835 return false; 836} 837 838template <class Impl> 839bool 840DefaultRename<Impl>::unblock(ThreadID tid) 841{ 842 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 843 844 // Rename is done unblocking if the skid buffer is empty. 845 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 846 847 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 848 849 toDecode->renameUnblock[tid] = true; 850 wroteToTimeBuffer = true; 851 852 renameStatus[tid] = Running; 853 return true; 854 } 855 856 return false; 857} 858 859template <class Impl> 860void 861DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 862{ 863 typename std::list<RenameHistory>::iterator hb_it = 864 historyBuffer[tid].begin(); 865 866 // After a syscall squashes everything, the history buffer may be empty 867 // but the ROB may still be squashing instructions. 868 if (historyBuffer[tid].empty()) { 869 return; 870 } 871 872 // Go through the most recent instructions, undoing the mappings 873 // they did and freeing up the registers. 874 while (!historyBuffer[tid].empty() && 875 hb_it->instSeqNum > squashed_seq_num) { 876 assert(hb_it != historyBuffer[tid].end()); 877 878 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 879 "number %i.\n", tid, hb_it->instSeqNum); 880 881 // Undo the rename mapping only if it was really a change. 882 // Special regs that are not really renamed (like misc regs 883 // and the zero reg) can be recognized because the new mapping 884 // is the same as the old one. While it would be merely a 885 // waste of time to update the rename table, we definitely 886 // don't want to put these on the free list. 887 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 888 // Tell the rename map to set the architected register to the 889 // previous physical register that it was renamed to. 890 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 891 892 // Put the renamed physical register back on the free list. 893 freeList->addReg(hb_it->newPhysReg); 894 } 895 896 historyBuffer[tid].erase(hb_it++); 897 898 ++renameUndoneMaps; 899 } 900} 901 902template<class Impl> 903void 904DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 905{ 906 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 907 "history buffer %u (size=%i), until [sn:%lli].\n", 908 tid, tid, historyBuffer[tid].size(), inst_seq_num); 909 910 typename std::list<RenameHistory>::iterator hb_it = 911 historyBuffer[tid].end(); 912 913 --hb_it; 914 915 if (historyBuffer[tid].empty()) { 916 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 917 return; 918 } else if (hb_it->instSeqNum > inst_seq_num) { 919 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 920 "that a syscall happened recently.\n", tid); 921 return; 922 } 923 924 // Commit all the renames up until (and including) the committed sequence 925 // number. Some or even all of the committed instructions may not have 926 // rename histories if they did not have destination registers that were 927 // renamed. 928 while (!historyBuffer[tid].empty() && 929 hb_it != historyBuffer[tid].end() && 930 hb_it->instSeqNum <= inst_seq_num) { 931 932 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 933 "[sn:%lli].\n", 934 tid, hb_it->prevPhysReg, hb_it->instSeqNum); 935 936 // Don't free special phys regs like misc and zero regs, which 937 // can be recognized because the new mapping is the same as 938 // the old one. 939 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 940 freeList->addReg(hb_it->prevPhysReg); 941 } 942 943 ++renameCommittedMaps; 944 945 historyBuffer[tid].erase(hb_it--); 946 } 947} 948 949template <class Impl> 950inline void 951DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 952{ 953 ThreadContext *tc = inst->tcBase(); 954 RenameMap *map = renameMap[tid]; 955 unsigned num_src_regs = inst->numSrcRegs(); 956 957 // Get the architectual register numbers from the source and 958 // operands, and redirect them to the right physical register. 959 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 960 RegIndex src_reg = inst->srcRegIdx(src_idx); 961 RegIndex rel_src_reg; 962 RegIndex flat_rel_src_reg; 963 PhysRegIndex renamed_reg; 964 965 switch (regIdxToClass(src_reg, &rel_src_reg)) { 966 case IntRegClass: 967 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 968 renamed_reg = map->lookupInt(flat_rel_src_reg); 969 intRenameLookups++; 970 break; 971 972 case FloatRegClass: 973 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 974 renamed_reg = map->lookupFloat(flat_rel_src_reg); 975 fpRenameLookups++; 976 break; 977 978 case CCRegClass: 979 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 980 renamed_reg = map->lookupCC(flat_rel_src_reg); 981 break; 982 983 case MiscRegClass: 984 // misc regs don't get flattened 985 flat_rel_src_reg = rel_src_reg; 986 renamed_reg = map->lookupMisc(flat_rel_src_reg); 987 break; 988 989 default: 990 panic("Reg index is out of bound: %d.", src_reg); 991 } 992 993 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 994 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 995 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); 996 997 inst->renameSrcReg(src_idx, renamed_reg); 998 999 // See if the register is ready or not. 1000 if (scoreboard->getReg(renamed_reg)) { 1001 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1002 tid, renamed_reg); 1003 1004 inst->markSrcRegReady(src_idx); 1005 } else { 1006 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1007 tid, renamed_reg); 1008 } 1009 1010 ++renameRenameLookups; 1011 } 1012} 1013 1014template <class Impl> 1015inline void 1016DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1017{ 1018 ThreadContext *tc = inst->tcBase(); 1019 RenameMap *map = renameMap[tid]; 1020 unsigned num_dest_regs = inst->numDestRegs(); 1021 1022 // Rename the destination registers. 1023 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1024 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1025 RegIndex rel_dest_reg; 1026 RegIndex flat_rel_dest_reg; 1027 RegIndex flat_uni_dest_reg; 1028 typename RenameMap::RenameInfo rename_result; 1029 1030 switch (regIdxToClass(dest_reg, &rel_dest_reg)) { 1031 case IntRegClass: 1032 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 1033 rename_result = map->renameInt(flat_rel_dest_reg); 1034 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping 1035 break; 1036 1037 case FloatRegClass: 1038 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1039 rename_result = map->renameFloat(flat_rel_dest_reg); 1040 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 1041 break; 1042 1043 case CCRegClass: 1044 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 1045 rename_result = map->renameCC(flat_rel_dest_reg); 1046 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 1047 break; 1048 1049 case MiscRegClass: 1050 // misc regs don't get flattened 1051 flat_rel_dest_reg = rel_dest_reg; 1052 rename_result = map->renameMisc(flat_rel_dest_reg); 1053 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 1054 break; 1055 1056 default: 1057 panic("Reg index is out of bound: %d.", dest_reg); 1058 } 1059 1060 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1061 1062 // Mark Scoreboard entry as not ready 1063 scoreboard->unsetReg(rename_result.first); 1064 1065 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1066 "reg %i.\n", tid, (int)flat_rel_dest_reg, 1067 (int)rename_result.first); 1068 1069 // Record the rename information so that a history can be kept. 1070 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1071 rename_result.first, 1072 rename_result.second); 1073 1074 historyBuffer[tid].push_front(hb_entry); 1075 1076 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1077 "(size=%i), [sn:%lli].\n",tid, 1078 historyBuffer[tid].size(), 1079 (*historyBuffer[tid].begin()).instSeqNum); 1080 1081 // Tell the instruction to rename the appropriate destination 1082 // register (dest_idx) to the new physical register 1083 // (rename_result.first), and record the previous physical 1084 // register that the same logical register was renamed to 1085 // (rename_result.second). 1086 inst->renameDestReg(dest_idx, 1087 rename_result.first, 1088 rename_result.second); 1089 1090 ++renameRenamedOperands; 1091 } 1092} 1093 1094template <class Impl> 1095inline int 1096DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1097{ 1098 int num_free = freeEntries[tid].robEntries - 1099 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1100 1101 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1102 1103 return num_free; 1104} 1105 1106template <class Impl> 1107inline int 1108DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1109{ 1110 int num_free = freeEntries[tid].iqEntries - 1111 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1112 1113 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1114 1115 return num_free; 1116} 1117 1118template <class Impl> 1119inline int 1120DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 1121{ 1122 int num_free = freeEntries[tid].lsqEntries - 1123 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1124 1125 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1126 1127 return num_free; 1128} 1129 1130template <class Impl> 1131unsigned 1132DefaultRename<Impl>::validInsts() 1133{ 1134 unsigned inst_count = 0; 1135 1136 for (int i=0; i<fromDecode->size; i++) { 1137 if (!fromDecode->insts[i]->isSquashed()) 1138 inst_count++; 1139 } 1140 1141 return inst_count; 1142} 1143 1144template <class Impl> 1145void 1146DefaultRename<Impl>::readStallSignals(ThreadID tid) 1147{ 1148 if (fromIEW->iewBlock[tid]) { 1149 stalls[tid].iew = true; 1150 } 1151 1152 if (fromIEW->iewUnblock[tid]) { 1153 assert(stalls[tid].iew); 1154 stalls[tid].iew = false; 1155 } 1156 1157 if (fromCommit->commitBlock[tid]) { 1158 stalls[tid].commit = true; 1159 } 1160 1161 if (fromCommit->commitUnblock[tid]) { 1162 assert(stalls[tid].commit); 1163 stalls[tid].commit = false; 1164 } 1165} 1166 1167template <class Impl> 1168bool 1169DefaultRename<Impl>::checkStall(ThreadID tid) 1170{ 1171 bool ret_val = false; 1172 1173 if (stalls[tid].iew) { 1174 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1175 ret_val = true; 1176 } else if (stalls[tid].commit) { 1177 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1178 ret_val = true; 1179 } else if (calcFreeROBEntries(tid) <= 0) { 1180 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1181 ret_val = true; 1182 } else if (calcFreeIQEntries(tid) <= 0) { 1183 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1184 ret_val = true; 1185 } else if (calcFreeLSQEntries(tid) <= 0) { 1186 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1187 ret_val = true; 1188 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1189 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1190 ret_val = true; 1191 } else if (renameStatus[tid] == SerializeStall && 1192 (!emptyROB[tid] || instsInProgress[tid])) { 1193 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1194 "empty.\n", 1195 tid); 1196 ret_val = true; 1197 } 1198 1199 return ret_val; 1200} 1201 1202template <class Impl> 1203void 1204DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1205{ 1206 if (fromIEW->iewInfo[tid].usedIQ) 1207 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1208 1209 if (fromIEW->iewInfo[tid].usedLSQ) 1210 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 1211 1212 if (fromCommit->commitInfo[tid].usedROB) { 1213 freeEntries[tid].robEntries = 1214 fromCommit->commitInfo[tid].freeROBEntries; 1215 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1216 } 1217 1218 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1219 tid, 1220 freeEntries[tid].iqEntries, 1221 freeEntries[tid].robEntries, 1222 freeEntries[tid].lsqEntries); 1223 1224 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1225 tid, instsInProgress[tid]); 1226} 1227 1228template <class Impl> 1229bool 1230DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1231{ 1232 // Check if there's a squash signal, squash if there is 1233 // Check stall signals, block if necessary. 1234 // If status was blocked 1235 // check if stall conditions have passed 1236 // if so then go to unblocking 1237 // If status was Squashing 1238 // check if squashing is not high. Switch to running this cycle. 1239 // If status was serialize stall 1240 // check if ROB is empty and no insts are in flight to the ROB 1241 1242 readFreeEntries(tid); 1243 readStallSignals(tid); 1244 1245 if (fromCommit->commitInfo[tid].squash) { 1246 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1247 "commit.\n", tid); 1248 1249 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1250 1251 return true; 1252 } 1253 1254 if (fromCommit->commitInfo[tid].robSquashing) { 1255 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1256 1257 renameStatus[tid] = Squashing; 1258 1259 return true; 1260 } 1261 1262 if (checkStall(tid)) { 1263 return block(tid); 1264 } 1265 1266 if (renameStatus[tid] == Blocked) { 1267 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1268 tid); 1269 1270 renameStatus[tid] = Unblocking; 1271 1272 unblock(tid); 1273 1274 return true; 1275 } 1276 1277 if (renameStatus[tid] == Squashing) { 1278 // Switch status to running if rename isn't being told to block or 1279 // squash this cycle. 1280 if (resumeSerialize) { 1281 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1282 tid); 1283 1284 renameStatus[tid] = SerializeStall; 1285 return true; 1286 } else if (resumeUnblocking) { 1287 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1288 tid); 1289 renameStatus[tid] = Unblocking; 1290 return true; 1291 } else { 1292 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1293 tid); 1294 1295 renameStatus[tid] = Running; 1296 return false; 1297 } 1298 } 1299 1300 if (renameStatus[tid] == SerializeStall) { 1301 // Stall ends once the ROB is free. 1302 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1303 "unblocking.\n", tid); 1304 1305 DynInstPtr serial_inst = serializeInst[tid]; 1306 1307 renameStatus[tid] = Unblocking; 1308 1309 unblock(tid); 1310 1311 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1312 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1313 1314 // Put instruction into queue here. 1315 serial_inst->clearSerializeBefore(); 1316 1317 if (!skidBuffer[tid].empty()) { 1318 skidBuffer[tid].push_front(serial_inst); 1319 } else { 1320 insts[tid].push_front(serial_inst); 1321 } 1322 1323 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1324 " Adding to front of list.\n", tid); 1325 1326 serializeInst[tid] = NULL; 1327 1328 return true; 1329 } 1330 1331 // If we've reached this point, we have not gotten any signals that 1332 // cause rename to change its status. Rename remains the same as before. 1333 return false; 1334} 1335 1336template<class Impl> 1337void 1338DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1339{ 1340 if (inst_list.empty()) { 1341 // Mark a bit to say that I must serialize on the next instruction. 1342 serializeOnNextInst[tid] = true; 1343 return; 1344 } 1345 1346 // Set the next instruction as serializing. 1347 inst_list.front()->setSerializeBefore(); 1348} 1349 1350template <class Impl> 1351inline void 1352DefaultRename<Impl>::incrFullStat(const FullSource &source) 1353{ 1354 switch (source) { 1355 case ROB: 1356 ++renameROBFullEvents; 1357 break; 1358 case IQ: 1359 ++renameIQFullEvents; 1360 break; 1361 case LSQ: 1362 ++renameLSQFullEvents; 1363 break; 1364 default: 1365 panic("Rename full stall stat should be incremented for a reason!"); 1366 break; 1367 } 1368} 1369 1370template <class Impl> 1371void 1372DefaultRename<Impl>::dumpHistory() 1373{ 1374 typename std::list<RenameHistory>::iterator buf_it; 1375 1376 for (ThreadID tid = 0; tid < numThreads; tid++) { 1377 1378 buf_it = historyBuffer[tid].begin(); 1379 1380 while (buf_it != historyBuffer[tid].end()) { 1381 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1382 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1383 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1384 1385 buf_it++; 1386 } 1387 } 1388} 1389