rename_impl.hh revision 9916:9c3a4595cce9
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#include <list> 46 47#include "arch/isa_traits.hh" 48#include "arch/registers.hh" 49#include "config/the_isa.hh" 50#include "cpu/o3/rename.hh" 51#include "cpu/reg_class.hh" 52#include "debug/Activity.hh" 53#include "debug/Rename.hh" 54#include "debug/O3PipeView.hh" 55#include "params/DerivO3CPU.hh" 56 57using namespace std; 58 59template <class Impl> 60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 61 : cpu(_cpu), 62 iewToRenameDelay(params->iewToRenameDelay), 63 decodeToRenameDelay(params->decodeToRenameDelay), 64 commitToRenameDelay(params->commitToRenameDelay), 65 renameWidth(params->renameWidth), 66 commitWidth(params->commitWidth), 67 numThreads(params->numThreads), 68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 69{ 70 // @todo: Make into a parameter. 71 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 72} 73 74template <class Impl> 75std::string 76DefaultRename<Impl>::name() const 77{ 78 return cpu->name() + ".rename"; 79} 80 81template <class Impl> 82void 83DefaultRename<Impl>::regStats() 84{ 85 renameSquashCycles 86 .name(name() + ".SquashCycles") 87 .desc("Number of cycles rename is squashing") 88 .prereq(renameSquashCycles); 89 renameIdleCycles 90 .name(name() + ".IdleCycles") 91 .desc("Number of cycles rename is idle") 92 .prereq(renameIdleCycles); 93 renameBlockCycles 94 .name(name() + ".BlockCycles") 95 .desc("Number of cycles rename is blocking") 96 .prereq(renameBlockCycles); 97 renameSerializeStallCycles 98 .name(name() + ".serializeStallCycles") 99 .desc("count of cycles rename stalled for serializing inst") 100 .flags(Stats::total); 101 renameRunCycles 102 .name(name() + ".RunCycles") 103 .desc("Number of cycles rename is running") 104 .prereq(renameIdleCycles); 105 renameUnblockCycles 106 .name(name() + ".UnblockCycles") 107 .desc("Number of cycles rename is unblocking") 108 .prereq(renameUnblockCycles); 109 renameRenamedInsts 110 .name(name() + ".RenamedInsts") 111 .desc("Number of instructions processed by rename") 112 .prereq(renameRenamedInsts); 113 renameSquashedInsts 114 .name(name() + ".SquashedInsts") 115 .desc("Number of squashed instructions processed by rename") 116 .prereq(renameSquashedInsts); 117 renameROBFullEvents 118 .name(name() + ".ROBFullEvents") 119 .desc("Number of times rename has blocked due to ROB full") 120 .prereq(renameROBFullEvents); 121 renameIQFullEvents 122 .name(name() + ".IQFullEvents") 123 .desc("Number of times rename has blocked due to IQ full") 124 .prereq(renameIQFullEvents); 125 renameLSQFullEvents 126 .name(name() + ".LSQFullEvents") 127 .desc("Number of times rename has blocked due to LSQ full") 128 .prereq(renameLSQFullEvents); 129 renameFullRegistersEvents 130 .name(name() + ".FullRegisterEvents") 131 .desc("Number of times there has been no free registers") 132 .prereq(renameFullRegistersEvents); 133 renameRenamedOperands 134 .name(name() + ".RenamedOperands") 135 .desc("Number of destination operands rename has renamed") 136 .prereq(renameRenamedOperands); 137 renameRenameLookups 138 .name(name() + ".RenameLookups") 139 .desc("Number of register rename lookups that rename has made") 140 .prereq(renameRenameLookups); 141 renameCommittedMaps 142 .name(name() + ".CommittedMaps") 143 .desc("Number of HB maps that are committed") 144 .prereq(renameCommittedMaps); 145 renameUndoneMaps 146 .name(name() + ".UndoneMaps") 147 .desc("Number of HB maps that are undone due to squashing") 148 .prereq(renameUndoneMaps); 149 renamedSerializing 150 .name(name() + ".serializingInsts") 151 .desc("count of serializing insts renamed") 152 .flags(Stats::total) 153 ; 154 renamedTempSerializing 155 .name(name() + ".tempSerializingInsts") 156 .desc("count of temporary serializing insts renamed") 157 .flags(Stats::total) 158 ; 159 renameSkidInsts 160 .name(name() + ".skidInsts") 161 .desc("count of insts added to the skid buffer") 162 .flags(Stats::total) 163 ; 164 intRenameLookups 165 .name(name() + ".int_rename_lookups") 166 .desc("Number of integer rename lookups") 167 .prereq(intRenameLookups); 168 fpRenameLookups 169 .name(name() + ".fp_rename_lookups") 170 .desc("Number of floating rename lookups") 171 .prereq(fpRenameLookups); 172} 173 174template <class Impl> 175void 176DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 177{ 178 timeBuffer = tb_ptr; 179 180 // Setup wire to read information from time buffer, from IEW stage. 181 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 182 183 // Setup wire to read infromation from time buffer, from commit stage. 184 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 185 186 // Setup wire to write information to previous stages. 187 toDecode = timeBuffer->getWire(0); 188} 189 190template <class Impl> 191void 192DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 193{ 194 renameQueue = rq_ptr; 195 196 // Setup wire to write information to future stages. 197 toIEW = renameQueue->getWire(0); 198} 199 200template <class Impl> 201void 202DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 203{ 204 decodeQueue = dq_ptr; 205 206 // Setup wire to get information from decode. 207 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 208} 209 210template <class Impl> 211void 212DefaultRename<Impl>::startupStage() 213{ 214 resetStage(); 215} 216 217template <class Impl> 218void 219DefaultRename<Impl>::resetStage() 220{ 221 _status = Inactive; 222 223 resumeSerialize = false; 224 resumeUnblocking = false; 225 226 // Grab the number of free entries directly from the stages. 227 for (ThreadID tid = 0; tid < numThreads; tid++) { 228 renameStatus[tid] = Idle; 229 230 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 231 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 232 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 233 emptyROB[tid] = true; 234 235 stalls[tid].iew = false; 236 stalls[tid].commit = false; 237 serializeInst[tid] = NULL; 238 239 instsInProgress[tid] = 0; 240 241 serializeOnNextInst[tid] = false; 242 } 243} 244 245template<class Impl> 246void 247DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 248{ 249 activeThreads = at_ptr; 250} 251 252 253template <class Impl> 254void 255DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 256{ 257 for (ThreadID tid = 0; tid < numThreads; tid++) 258 renameMap[tid] = &rm_ptr[tid]; 259} 260 261template <class Impl> 262void 263DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 264{ 265 freeList = fl_ptr; 266} 267 268template<class Impl> 269void 270DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 271{ 272 scoreboard = _scoreboard; 273} 274 275template <class Impl> 276bool 277DefaultRename<Impl>::isDrained() const 278{ 279 for (ThreadID tid = 0; tid < numThreads; tid++) { 280 if (instsInProgress[tid] != 0 || 281 !historyBuffer[tid].empty() || 282 !skidBuffer[tid].empty() || 283 !insts[tid].empty()) 284 return false; 285 } 286 return true; 287} 288 289template <class Impl> 290void 291DefaultRename<Impl>::takeOverFrom() 292{ 293 resetStage(); 294} 295 296template <class Impl> 297void 298DefaultRename<Impl>::drainSanityCheck() const 299{ 300 for (ThreadID tid = 0; tid < numThreads; tid++) { 301 assert(historyBuffer[tid].empty()); 302 assert(insts[tid].empty()); 303 assert(skidBuffer[tid].empty()); 304 assert(instsInProgress[tid] == 0); 305 } 306} 307 308template <class Impl> 309void 310DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 311{ 312 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 313 314 // Clear the stall signal if rename was blocked or unblocking before. 315 // If it still needs to block, the blocking should happen the next 316 // cycle and there should be space to hold everything due to the squash. 317 if (renameStatus[tid] == Blocked || 318 renameStatus[tid] == Unblocking) { 319 toDecode->renameUnblock[tid] = 1; 320 321 resumeSerialize = false; 322 serializeInst[tid] = NULL; 323 } else if (renameStatus[tid] == SerializeStall) { 324 if (serializeInst[tid]->seqNum <= squash_seq_num) { 325 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 326 resumeSerialize = true; 327 assert(serializeInst[tid]); 328 } else { 329 resumeSerialize = false; 330 toDecode->renameUnblock[tid] = 1; 331 332 serializeInst[tid] = NULL; 333 } 334 } 335 336 // Set the status to Squashing. 337 renameStatus[tid] = Squashing; 338 339 // Squash any instructions from decode. 340 unsigned squashCount = 0; 341 342 for (int i=0; i<fromDecode->size; i++) { 343 if (fromDecode->insts[i]->threadNumber == tid && 344 fromDecode->insts[i]->seqNum > squash_seq_num) { 345 fromDecode->insts[i]->setSquashed(); 346 wroteToTimeBuffer = true; 347 squashCount++; 348 } 349 350 } 351 352 // Clear the instruction list and skid buffer in case they have any 353 // insts in them. 354 insts[tid].clear(); 355 356 // Clear the skid buffer in case it has any data in it. 357 skidBuffer[tid].clear(); 358 359 doSquash(squash_seq_num, tid); 360} 361 362template <class Impl> 363void 364DefaultRename<Impl>::tick() 365{ 366 wroteToTimeBuffer = false; 367 368 blockThisCycle = false; 369 370 bool status_change = false; 371 372 toIEWIndex = 0; 373 374 sortInsts(); 375 376 list<ThreadID>::iterator threads = activeThreads->begin(); 377 list<ThreadID>::iterator end = activeThreads->end(); 378 379 // Check stall and squash signals. 380 while (threads != end) { 381 ThreadID tid = *threads++; 382 383 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 384 385 status_change = checkSignalsAndUpdate(tid) || status_change; 386 387 rename(status_change, tid); 388 } 389 390 if (status_change) { 391 updateStatus(); 392 } 393 394 if (wroteToTimeBuffer) { 395 DPRINTF(Activity, "Activity this cycle.\n"); 396 cpu->activityThisCycle(); 397 } 398 399 threads = activeThreads->begin(); 400 401 while (threads != end) { 402 ThreadID tid = *threads++; 403 404 // If we committed this cycle then doneSeqNum will be > 0 405 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 406 !fromCommit->commitInfo[tid].squash && 407 renameStatus[tid] != Squashing) { 408 409 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 410 tid); 411 } 412 } 413 414 // @todo: make into updateProgress function 415 for (ThreadID tid = 0; tid < numThreads; tid++) { 416 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 417 418 assert(instsInProgress[tid] >=0); 419 } 420 421} 422 423template<class Impl> 424void 425DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 426{ 427 // If status is Running or idle, 428 // call renameInsts() 429 // If status is Unblocking, 430 // buffer any instructions coming from decode 431 // continue trying to empty skid buffer 432 // check if stall conditions have passed 433 434 if (renameStatus[tid] == Blocked) { 435 ++renameBlockCycles; 436 } else if (renameStatus[tid] == Squashing) { 437 ++renameSquashCycles; 438 } else if (renameStatus[tid] == SerializeStall) { 439 ++renameSerializeStallCycles; 440 // If we are currently in SerializeStall and resumeSerialize 441 // was set, then that means that we are resuming serializing 442 // this cycle. Tell the previous stages to block. 443 if (resumeSerialize) { 444 resumeSerialize = false; 445 block(tid); 446 toDecode->renameUnblock[tid] = false; 447 } 448 } else if (renameStatus[tid] == Unblocking) { 449 if (resumeUnblocking) { 450 block(tid); 451 resumeUnblocking = false; 452 toDecode->renameUnblock[tid] = false; 453 } 454 } 455 456 if (renameStatus[tid] == Running || 457 renameStatus[tid] == Idle) { 458 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 459 "stage.\n", tid); 460 461 renameInsts(tid); 462 } else if (renameStatus[tid] == Unblocking) { 463 renameInsts(tid); 464 465 if (validInsts()) { 466 // Add the current inputs to the skid buffer so they can be 467 // reprocessed when this stage unblocks. 468 skidInsert(tid); 469 } 470 471 // If we switched over to blocking, then there's a potential for 472 // an overall status change. 473 status_change = unblock(tid) || status_change || blockThisCycle; 474 } 475} 476 477template <class Impl> 478void 479DefaultRename<Impl>::renameInsts(ThreadID tid) 480{ 481 // Instructions can be either in the skid buffer or the queue of 482 // instructions coming from decode, depending on the status. 483 int insts_available = renameStatus[tid] == Unblocking ? 484 skidBuffer[tid].size() : insts[tid].size(); 485 486 // Check the decode queue to see if instructions are available. 487 // If there are no available instructions to rename, then do nothing. 488 if (insts_available == 0) { 489 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 490 tid); 491 // Should I change status to idle? 492 ++renameIdleCycles; 493 return; 494 } else if (renameStatus[tid] == Unblocking) { 495 ++renameUnblockCycles; 496 } else if (renameStatus[tid] == Running) { 497 ++renameRunCycles; 498 } 499 500 DynInstPtr inst; 501 502 // Will have to do a different calculation for the number of free 503 // entries. 504 int free_rob_entries = calcFreeROBEntries(tid); 505 int free_iq_entries = calcFreeIQEntries(tid); 506 int free_lsq_entries = calcFreeLSQEntries(tid); 507 int min_free_entries = free_rob_entries; 508 509 FullSource source = ROB; 510 511 if (free_iq_entries < min_free_entries) { 512 min_free_entries = free_iq_entries; 513 source = IQ; 514 } 515 516 if (free_lsq_entries < min_free_entries) { 517 min_free_entries = free_lsq_entries; 518 source = LSQ; 519 } 520 521 // Check if there's any space left. 522 if (min_free_entries <= 0) { 523 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 524 "entries.\n" 525 "ROB has %i free entries.\n" 526 "IQ has %i free entries.\n" 527 "LSQ has %i free entries.\n", 528 tid, 529 free_rob_entries, 530 free_iq_entries, 531 free_lsq_entries); 532 533 blockThisCycle = true; 534 535 block(tid); 536 537 incrFullStat(source); 538 539 return; 540 } else if (min_free_entries < insts_available) { 541 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 542 "%i insts available, but only %i insts can be " 543 "renamed due to ROB/IQ/LSQ limits.\n", 544 tid, insts_available, min_free_entries); 545 546 insts_available = min_free_entries; 547 548 blockThisCycle = true; 549 550 incrFullStat(source); 551 } 552 553 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 554 skidBuffer[tid] : insts[tid]; 555 556 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 557 "send iew.\n", tid, insts_available); 558 559 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 560 "dispatched to IQ last cycle.\n", 561 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 562 563 // Handle serializing the next instruction if necessary. 564 if (serializeOnNextInst[tid]) { 565 if (emptyROB[tid] && instsInProgress[tid] == 0) { 566 // ROB already empty; no need to serialize. 567 serializeOnNextInst[tid] = false; 568 } else if (!insts_to_rename.empty()) { 569 insts_to_rename.front()->setSerializeBefore(); 570 } 571 } 572 573 int renamed_insts = 0; 574 575 while (insts_available > 0 && toIEWIndex < renameWidth) { 576 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 577 578 assert(!insts_to_rename.empty()); 579 580 inst = insts_to_rename.front(); 581 582 insts_to_rename.pop_front(); 583 584 if (renameStatus[tid] == Unblocking) { 585 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 586 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 587 } 588 589 if (inst->isSquashed()) { 590 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 591 "squashed, skipping.\n", tid, inst->seqNum, 592 inst->pcState()); 593 594 ++renameSquashedInsts; 595 596 // Decrement how many instructions are available. 597 --insts_available; 598 599 continue; 600 } 601 602 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 603 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 604 605 // Check here to make sure there are enough destination registers 606 // to rename to. Otherwise block. 607 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 608 DPRINTF(Rename, "Blocking due to lack of free " 609 "physical registers to rename to.\n"); 610 blockThisCycle = true; 611 insts_to_rename.push_front(inst); 612 ++renameFullRegistersEvents; 613 614 break; 615 } 616 617 // Handle serializeAfter/serializeBefore instructions. 618 // serializeAfter marks the next instruction as serializeBefore. 619 // serializeBefore makes the instruction wait in rename until the ROB 620 // is empty. 621 622 // In this model, IPR accesses are serialize before 623 // instructions, and store conditionals are serialize after 624 // instructions. This is mainly due to lack of support for 625 // out-of-order operations of either of those classes of 626 // instructions. 627 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 628 !inst->isSerializeHandled()) { 629 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 630 631 if (!inst->isTempSerializeBefore()) { 632 renamedSerializing++; 633 inst->setSerializeHandled(); 634 } else { 635 renamedTempSerializing++; 636 } 637 638 // Change status over to SerializeStall so that other stages know 639 // what this is blocked on. 640 renameStatus[tid] = SerializeStall; 641 642 serializeInst[tid] = inst; 643 644 blockThisCycle = true; 645 646 break; 647 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 648 !inst->isSerializeHandled()) { 649 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 650 651 renamedSerializing++; 652 653 inst->setSerializeHandled(); 654 655 serializeAfter(insts_to_rename, tid); 656 } 657 658 renameSrcRegs(inst, inst->threadNumber); 659 660 renameDestRegs(inst, inst->threadNumber); 661 662 ++renamed_insts; 663 664 665 // Put instruction in rename queue. 666 toIEW->insts[toIEWIndex] = inst; 667 ++(toIEW->size); 668 669 // Increment which instruction we're on. 670 ++toIEWIndex; 671 672 // Decrement how many instructions are available. 673 --insts_available; 674 } 675 676 instsInProgress[tid] += renamed_insts; 677 renameRenamedInsts += renamed_insts; 678 679 // If we wrote to the time buffer, record this. 680 if (toIEWIndex) { 681 wroteToTimeBuffer = true; 682 } 683 684 // Check if there's any instructions left that haven't yet been renamed. 685 // If so then block. 686 if (insts_available) { 687 blockThisCycle = true; 688 } 689 690 if (blockThisCycle) { 691 block(tid); 692 toDecode->renameUnblock[tid] = false; 693 } 694} 695 696template<class Impl> 697void 698DefaultRename<Impl>::skidInsert(ThreadID tid) 699{ 700 DynInstPtr inst = NULL; 701 702 while (!insts[tid].empty()) { 703 inst = insts[tid].front(); 704 705 insts[tid].pop_front(); 706 707 assert(tid == inst->threadNumber); 708 709 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 710 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 711 712 ++renameSkidInsts; 713 714 skidBuffer[tid].push_back(inst); 715 } 716 717 if (skidBuffer[tid].size() > skidBufferMax) 718 { 719 typename InstQueue::iterator it; 720 warn("Skidbuffer contents:\n"); 721 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 722 { 723 warn("[tid:%u]: %s [sn:%i].\n", tid, 724 (*it)->staticInst->disassemble(inst->instAddr()), 725 (*it)->seqNum); 726 } 727 panic("Skidbuffer Exceeded Max Size"); 728 } 729} 730 731template <class Impl> 732void 733DefaultRename<Impl>::sortInsts() 734{ 735 int insts_from_decode = fromDecode->size; 736 for (int i = 0; i < insts_from_decode; ++i) { 737 DynInstPtr inst = fromDecode->insts[i]; 738 insts[inst->threadNumber].push_back(inst); 739#if TRACING_ON 740 if (DTRACE(O3PipeView)) { 741 inst->renameTick = curTick() - inst->fetchTick; 742 } 743#endif 744 } 745} 746 747template<class Impl> 748bool 749DefaultRename<Impl>::skidsEmpty() 750{ 751 list<ThreadID>::iterator threads = activeThreads->begin(); 752 list<ThreadID>::iterator end = activeThreads->end(); 753 754 while (threads != end) { 755 ThreadID tid = *threads++; 756 757 if (!skidBuffer[tid].empty()) 758 return false; 759 } 760 761 return true; 762} 763 764template<class Impl> 765void 766DefaultRename<Impl>::updateStatus() 767{ 768 bool any_unblocking = false; 769 770 list<ThreadID>::iterator threads = activeThreads->begin(); 771 list<ThreadID>::iterator end = activeThreads->end(); 772 773 while (threads != end) { 774 ThreadID tid = *threads++; 775 776 if (renameStatus[tid] == Unblocking) { 777 any_unblocking = true; 778 break; 779 } 780 } 781 782 // Rename will have activity if it's unblocking. 783 if (any_unblocking) { 784 if (_status == Inactive) { 785 _status = Active; 786 787 DPRINTF(Activity, "Activating stage.\n"); 788 789 cpu->activateStage(O3CPU::RenameIdx); 790 } 791 } else { 792 // If it's not unblocking, then rename will not have any internal 793 // activity. Switch it to inactive. 794 if (_status == Active) { 795 _status = Inactive; 796 DPRINTF(Activity, "Deactivating stage.\n"); 797 798 cpu->deactivateStage(O3CPU::RenameIdx); 799 } 800 } 801} 802 803template <class Impl> 804bool 805DefaultRename<Impl>::block(ThreadID tid) 806{ 807 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 808 809 // Add the current inputs onto the skid buffer, so they can be 810 // reprocessed when this stage unblocks. 811 skidInsert(tid); 812 813 // Only signal backwards to block if the previous stages do not think 814 // rename is already blocked. 815 if (renameStatus[tid] != Blocked) { 816 // If resumeUnblocking is set, we unblocked during the squash, 817 // but now we're have unblocking status. We need to tell earlier 818 // stages to block. 819 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 820 toDecode->renameBlock[tid] = true; 821 toDecode->renameUnblock[tid] = false; 822 wroteToTimeBuffer = true; 823 } 824 825 // Rename can not go from SerializeStall to Blocked, otherwise 826 // it would not know to complete the serialize stall. 827 if (renameStatus[tid] != SerializeStall) { 828 // Set status to Blocked. 829 renameStatus[tid] = Blocked; 830 return true; 831 } 832 } 833 834 return false; 835} 836 837template <class Impl> 838bool 839DefaultRename<Impl>::unblock(ThreadID tid) 840{ 841 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 842 843 // Rename is done unblocking if the skid buffer is empty. 844 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 845 846 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 847 848 toDecode->renameUnblock[tid] = true; 849 wroteToTimeBuffer = true; 850 851 renameStatus[tid] = Running; 852 return true; 853 } 854 855 return false; 856} 857 858template <class Impl> 859void 860DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 861{ 862 typename std::list<RenameHistory>::iterator hb_it = 863 historyBuffer[tid].begin(); 864 865 // After a syscall squashes everything, the history buffer may be empty 866 // but the ROB may still be squashing instructions. 867 if (historyBuffer[tid].empty()) { 868 return; 869 } 870 871 // Go through the most recent instructions, undoing the mappings 872 // they did and freeing up the registers. 873 while (!historyBuffer[tid].empty() && 874 (*hb_it).instSeqNum > squashed_seq_num) { 875 assert(hb_it != historyBuffer[tid].end()); 876 877 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 878 "number %i.\n", tid, (*hb_it).instSeqNum); 879 880 // Tell the rename map to set the architected register to the 881 // previous physical register that it was renamed to. 882 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 883 884 // Put the renamed physical register back on the free list. 885 freeList->addReg(hb_it->newPhysReg); 886 887 historyBuffer[tid].erase(hb_it++); 888 889 ++renameUndoneMaps; 890 } 891} 892 893template<class Impl> 894void 895DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 896{ 897 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 898 "history buffer %u (size=%i), until [sn:%lli].\n", 899 tid, tid, historyBuffer[tid].size(), inst_seq_num); 900 901 typename std::list<RenameHistory>::iterator hb_it = 902 historyBuffer[tid].end(); 903 904 --hb_it; 905 906 if (historyBuffer[tid].empty()) { 907 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 908 return; 909 } else if (hb_it->instSeqNum > inst_seq_num) { 910 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 911 "that a syscall happened recently.\n", tid); 912 return; 913 } 914 915 // Commit all the renames up until (and including) the committed sequence 916 // number. Some or even all of the committed instructions may not have 917 // rename histories if they did not have destination registers that were 918 // renamed. 919 while (!historyBuffer[tid].empty() && 920 hb_it != historyBuffer[tid].end() && 921 (*hb_it).instSeqNum <= inst_seq_num) { 922 923 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 924 "[sn:%lli].\n", 925 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 926 927 freeList->addReg((*hb_it).prevPhysReg); 928 ++renameCommittedMaps; 929 930 historyBuffer[tid].erase(hb_it--); 931 } 932} 933 934template <class Impl> 935inline void 936DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 937{ 938 assert(renameMap[tid] != 0); 939 940 unsigned num_src_regs = inst->numSrcRegs(); 941 942 // Get the architectual register numbers from the source and 943 // destination operands, and redirect them to the right register. 944 // Will need to mark dependencies though. 945 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 946 RegIndex src_reg = inst->srcRegIdx(src_idx); 947 RegIndex flat_src_reg = src_reg; 948 switch (regIdxToClass(src_reg)) { 949 case IntRegClass: 950 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 951 DPRINTF(Rename, "Flattening index %d to %d.\n", 952 (int)src_reg, (int)flat_src_reg); 953 break; 954 955 case FloatRegClass: 956 src_reg = src_reg - TheISA::FP_Base_DepTag; 957 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 958 DPRINTF(Rename, "Flattening index %d to %d.\n", 959 (int)src_reg, (int)flat_src_reg); 960 flat_src_reg += TheISA::NumIntRegs; 961 break; 962 963 case MiscRegClass: 964 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 965 TheISA::NumFloatRegs + TheISA::NumIntRegs; 966 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 967 src_reg, flat_src_reg); 968 break; 969 970 default: 971 panic("Reg index is out of bound: %d.", src_reg); 972 } 973 974 // Look up the source registers to get the phys. register they've 975 // been renamed to, and set the sources to those registers. 976 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 977 978 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 979 "physical reg %i.\n", tid, (int)flat_src_reg, 980 (int)renamed_reg); 981 982 inst->renameSrcReg(src_idx, renamed_reg); 983 984 // See if the register is ready or not. 985 if (scoreboard->getReg(renamed_reg) == true) { 986 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 987 tid, renamed_reg); 988 989 inst->markSrcRegReady(src_idx); 990 } else { 991 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 992 tid, renamed_reg); 993 } 994 995 ++renameRenameLookups; 996 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 997 } 998} 999 1000template <class Impl> 1001inline void 1002DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1003{ 1004 typename RenameMap::RenameInfo rename_result; 1005 1006 unsigned num_dest_regs = inst->numDestRegs(); 1007 1008 // Rename the destination registers. 1009 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1010 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1011 RegIndex flat_dest_reg = dest_reg; 1012 switch (regIdxToClass(dest_reg)) { 1013 case IntRegClass: 1014 // Integer registers are flattened. 1015 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 1016 DPRINTF(Rename, "Flattening index %d to %d.\n", 1017 (int)dest_reg, (int)flat_dest_reg); 1018 break; 1019 1020 case FloatRegClass: 1021 dest_reg = dest_reg - TheISA::FP_Base_DepTag; 1022 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 1023 DPRINTF(Rename, "Flattening index %d to %d.\n", 1024 (int)dest_reg, (int)flat_dest_reg); 1025 flat_dest_reg += TheISA::NumIntRegs; 1026 break; 1027 1028 case MiscRegClass: 1029 // Floating point and Miscellaneous registers need their indexes 1030 // adjusted to account for the expanded number of flattened int regs. 1031 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 1032 TheISA::NumIntRegs + TheISA::NumFloatRegs; 1033 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 1034 dest_reg, flat_dest_reg); 1035 break; 1036 1037 default: 1038 panic("Reg index is out of bound: %d.", dest_reg); 1039 } 1040 1041 inst->flattenDestReg(dest_idx, flat_dest_reg); 1042 1043 // Get the physical register that the destination will be 1044 // renamed to. 1045 rename_result = renameMap[tid]->rename(flat_dest_reg); 1046 1047 //Mark Scoreboard entry as not ready 1048 scoreboard->unsetReg(rename_result.first); 1049 1050 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1051 "reg %i.\n", tid, (int)flat_dest_reg, 1052 (int)rename_result.first); 1053 1054 // Record the rename information so that a history can be kept. 1055 RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 1056 rename_result.first, 1057 rename_result.second); 1058 1059 historyBuffer[tid].push_front(hb_entry); 1060 1061 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1062 "(size=%i), [sn:%lli].\n",tid, 1063 historyBuffer[tid].size(), 1064 (*historyBuffer[tid].begin()).instSeqNum); 1065 1066 // Tell the instruction to rename the appropriate destination 1067 // register (dest_idx) to the new physical register 1068 // (rename_result.first), and record the previous physical 1069 // register that the same logical register was renamed to 1070 // (rename_result.second). 1071 inst->renameDestReg(dest_idx, 1072 rename_result.first, 1073 rename_result.second); 1074 1075 ++renameRenamedOperands; 1076 } 1077} 1078 1079template <class Impl> 1080inline int 1081DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1082{ 1083 int num_free = freeEntries[tid].robEntries - 1084 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1085 1086 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1087 1088 return num_free; 1089} 1090 1091template <class Impl> 1092inline int 1093DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1094{ 1095 int num_free = freeEntries[tid].iqEntries - 1096 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1097 1098 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1099 1100 return num_free; 1101} 1102 1103template <class Impl> 1104inline int 1105DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 1106{ 1107 int num_free = freeEntries[tid].lsqEntries - 1108 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1109 1110 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1111 1112 return num_free; 1113} 1114 1115template <class Impl> 1116unsigned 1117DefaultRename<Impl>::validInsts() 1118{ 1119 unsigned inst_count = 0; 1120 1121 for (int i=0; i<fromDecode->size; i++) { 1122 if (!fromDecode->insts[i]->isSquashed()) 1123 inst_count++; 1124 } 1125 1126 return inst_count; 1127} 1128 1129template <class Impl> 1130void 1131DefaultRename<Impl>::readStallSignals(ThreadID tid) 1132{ 1133 if (fromIEW->iewBlock[tid]) { 1134 stalls[tid].iew = true; 1135 } 1136 1137 if (fromIEW->iewUnblock[tid]) { 1138 assert(stalls[tid].iew); 1139 stalls[tid].iew = false; 1140 } 1141 1142 if (fromCommit->commitBlock[tid]) { 1143 stalls[tid].commit = true; 1144 } 1145 1146 if (fromCommit->commitUnblock[tid]) { 1147 assert(stalls[tid].commit); 1148 stalls[tid].commit = false; 1149 } 1150} 1151 1152template <class Impl> 1153bool 1154DefaultRename<Impl>::checkStall(ThreadID tid) 1155{ 1156 bool ret_val = false; 1157 1158 if (stalls[tid].iew) { 1159 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1160 ret_val = true; 1161 } else if (stalls[tid].commit) { 1162 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1163 ret_val = true; 1164 } else if (calcFreeROBEntries(tid) <= 0) { 1165 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1166 ret_val = true; 1167 } else if (calcFreeIQEntries(tid) <= 0) { 1168 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1169 ret_val = true; 1170 } else if (calcFreeLSQEntries(tid) <= 0) { 1171 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1172 ret_val = true; 1173 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1174 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1175 ret_val = true; 1176 } else if (renameStatus[tid] == SerializeStall && 1177 (!emptyROB[tid] || instsInProgress[tid])) { 1178 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1179 "empty.\n", 1180 tid); 1181 ret_val = true; 1182 } 1183 1184 return ret_val; 1185} 1186 1187template <class Impl> 1188void 1189DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1190{ 1191 if (fromIEW->iewInfo[tid].usedIQ) 1192 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1193 1194 if (fromIEW->iewInfo[tid].usedLSQ) 1195 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 1196 1197 if (fromCommit->commitInfo[tid].usedROB) { 1198 freeEntries[tid].robEntries = 1199 fromCommit->commitInfo[tid].freeROBEntries; 1200 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1201 } 1202 1203 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1204 tid, 1205 freeEntries[tid].iqEntries, 1206 freeEntries[tid].robEntries, 1207 freeEntries[tid].lsqEntries); 1208 1209 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1210 tid, instsInProgress[tid]); 1211} 1212 1213template <class Impl> 1214bool 1215DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1216{ 1217 // Check if there's a squash signal, squash if there is 1218 // Check stall signals, block if necessary. 1219 // If status was blocked 1220 // check if stall conditions have passed 1221 // if so then go to unblocking 1222 // If status was Squashing 1223 // check if squashing is not high. Switch to running this cycle. 1224 // If status was serialize stall 1225 // check if ROB is empty and no insts are in flight to the ROB 1226 1227 readFreeEntries(tid); 1228 readStallSignals(tid); 1229 1230 if (fromCommit->commitInfo[tid].squash) { 1231 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1232 "commit.\n", tid); 1233 1234 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1235 1236 return true; 1237 } 1238 1239 if (fromCommit->commitInfo[tid].robSquashing) { 1240 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1241 1242 renameStatus[tid] = Squashing; 1243 1244 return true; 1245 } 1246 1247 if (checkStall(tid)) { 1248 return block(tid); 1249 } 1250 1251 if (renameStatus[tid] == Blocked) { 1252 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1253 tid); 1254 1255 renameStatus[tid] = Unblocking; 1256 1257 unblock(tid); 1258 1259 return true; 1260 } 1261 1262 if (renameStatus[tid] == Squashing) { 1263 // Switch status to running if rename isn't being told to block or 1264 // squash this cycle. 1265 if (resumeSerialize) { 1266 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1267 tid); 1268 1269 renameStatus[tid] = SerializeStall; 1270 return true; 1271 } else if (resumeUnblocking) { 1272 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1273 tid); 1274 renameStatus[tid] = Unblocking; 1275 return true; 1276 } else { 1277 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1278 tid); 1279 1280 renameStatus[tid] = Running; 1281 return false; 1282 } 1283 } 1284 1285 if (renameStatus[tid] == SerializeStall) { 1286 // Stall ends once the ROB is free. 1287 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1288 "unblocking.\n", tid); 1289 1290 DynInstPtr serial_inst = serializeInst[tid]; 1291 1292 renameStatus[tid] = Unblocking; 1293 1294 unblock(tid); 1295 1296 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1297 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1298 1299 // Put instruction into queue here. 1300 serial_inst->clearSerializeBefore(); 1301 1302 if (!skidBuffer[tid].empty()) { 1303 skidBuffer[tid].push_front(serial_inst); 1304 } else { 1305 insts[tid].push_front(serial_inst); 1306 } 1307 1308 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1309 " Adding to front of list.\n", tid); 1310 1311 serializeInst[tid] = NULL; 1312 1313 return true; 1314 } 1315 1316 // If we've reached this point, we have not gotten any signals that 1317 // cause rename to change its status. Rename remains the same as before. 1318 return false; 1319} 1320 1321template<class Impl> 1322void 1323DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1324{ 1325 if (inst_list.empty()) { 1326 // Mark a bit to say that I must serialize on the next instruction. 1327 serializeOnNextInst[tid] = true; 1328 return; 1329 } 1330 1331 // Set the next instruction as serializing. 1332 inst_list.front()->setSerializeBefore(); 1333} 1334 1335template <class Impl> 1336inline void 1337DefaultRename<Impl>::incrFullStat(const FullSource &source) 1338{ 1339 switch (source) { 1340 case ROB: 1341 ++renameROBFullEvents; 1342 break; 1343 case IQ: 1344 ++renameIQFullEvents; 1345 break; 1346 case LSQ: 1347 ++renameLSQFullEvents; 1348 break; 1349 default: 1350 panic("Rename full stall stat should be incremented for a reason!"); 1351 break; 1352 } 1353} 1354 1355template <class Impl> 1356void 1357DefaultRename<Impl>::dumpHistory() 1358{ 1359 typename std::list<RenameHistory>::iterator buf_it; 1360 1361 for (ThreadID tid = 0; tid < numThreads; tid++) { 1362 1363 buf_it = historyBuffer[tid].begin(); 1364 1365 while (buf_it != historyBuffer[tid].end()) { 1366 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1367 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1368 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1369 1370 buf_it++; 1371 } 1372 } 1373} 1374