rename_impl.hh revision 8240
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <list> 45 46#include "arch/isa_traits.hh" 47#include "arch/registers.hh" 48#include "config/full_system.hh" 49#include "config/the_isa.hh" 50#include "cpu/o3/rename.hh" 51#include "debug/Activity.hh" 52#include "debug/Rename.hh" 53#include "params/DerivO3CPU.hh" 54 55using namespace std; 56 57template <class Impl> 58DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 59 : cpu(_cpu), 60 iewToRenameDelay(params->iewToRenameDelay), 61 decodeToRenameDelay(params->decodeToRenameDelay), 62 commitToRenameDelay(params->commitToRenameDelay), 63 renameWidth(params->renameWidth), 64 commitWidth(params->commitWidth), 65 resumeSerialize(false), 66 resumeUnblocking(false), 67 numThreads(params->numThreads), 68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 69{ 70 _status = Inactive; 71 72 for (ThreadID tid = 0; tid < numThreads; tid++) { 73 renameStatus[tid] = Idle; 74 75 freeEntries[tid].iqEntries = 0; 76 freeEntries[tid].lsqEntries = 0; 77 freeEntries[tid].robEntries = 0; 78 79 stalls[tid].iew = false; 80 stalls[tid].commit = false; 81 serializeInst[tid] = NULL; 82 83 instsInProgress[tid] = 0; 84 85 emptyROB[tid] = true; 86 87 serializeOnNextInst[tid] = false; 88 } 89 90 // @todo: Make into a parameter. 91 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 92} 93 94template <class Impl> 95std::string 96DefaultRename<Impl>::name() const 97{ 98 return cpu->name() + ".rename"; 99} 100 101template <class Impl> 102void 103DefaultRename<Impl>::regStats() 104{ 105 renameSquashCycles 106 .name(name() + ".SquashCycles") 107 .desc("Number of cycles rename is squashing") 108 .prereq(renameSquashCycles); 109 renameIdleCycles 110 .name(name() + ".IdleCycles") 111 .desc("Number of cycles rename is idle") 112 .prereq(renameIdleCycles); 113 renameBlockCycles 114 .name(name() + ".BlockCycles") 115 .desc("Number of cycles rename is blocking") 116 .prereq(renameBlockCycles); 117 renameSerializeStallCycles 118 .name(name() + ".serializeStallCycles") 119 .desc("count of cycles rename stalled for serializing inst") 120 .flags(Stats::total); 121 renameRunCycles 122 .name(name() + ".RunCycles") 123 .desc("Number of cycles rename is running") 124 .prereq(renameIdleCycles); 125 renameUnblockCycles 126 .name(name() + ".UnblockCycles") 127 .desc("Number of cycles rename is unblocking") 128 .prereq(renameUnblockCycles); 129 renameRenamedInsts 130 .name(name() + ".RenamedInsts") 131 .desc("Number of instructions processed by rename") 132 .prereq(renameRenamedInsts); 133 renameSquashedInsts 134 .name(name() + ".SquashedInsts") 135 .desc("Number of squashed instructions processed by rename") 136 .prereq(renameSquashedInsts); 137 renameROBFullEvents 138 .name(name() + ".ROBFullEvents") 139 .desc("Number of times rename has blocked due to ROB full") 140 .prereq(renameROBFullEvents); 141 renameIQFullEvents 142 .name(name() + ".IQFullEvents") 143 .desc("Number of times rename has blocked due to IQ full") 144 .prereq(renameIQFullEvents); 145 renameLSQFullEvents 146 .name(name() + ".LSQFullEvents") 147 .desc("Number of times rename has blocked due to LSQ full") 148 .prereq(renameLSQFullEvents); 149 renameFullRegistersEvents 150 .name(name() + ".FullRegisterEvents") 151 .desc("Number of times there has been no free registers") 152 .prereq(renameFullRegistersEvents); 153 renameRenamedOperands 154 .name(name() + ".RenamedOperands") 155 .desc("Number of destination operands rename has renamed") 156 .prereq(renameRenamedOperands); 157 renameRenameLookups 158 .name(name() + ".RenameLookups") 159 .desc("Number of register rename lookups that rename has made") 160 .prereq(renameRenameLookups); 161 renameCommittedMaps 162 .name(name() + ".CommittedMaps") 163 .desc("Number of HB maps that are committed") 164 .prereq(renameCommittedMaps); 165 renameUndoneMaps 166 .name(name() + ".UndoneMaps") 167 .desc("Number of HB maps that are undone due to squashing") 168 .prereq(renameUndoneMaps); 169 renamedSerializing 170 .name(name() + ".serializingInsts") 171 .desc("count of serializing insts renamed") 172 .flags(Stats::total) 173 ; 174 renamedTempSerializing 175 .name(name() + ".tempSerializingInsts") 176 .desc("count of temporary serializing insts renamed") 177 .flags(Stats::total) 178 ; 179 renameSkidInsts 180 .name(name() + ".skidInsts") 181 .desc("count of insts added to the skid buffer") 182 .flags(Stats::total) 183 ; 184 intRenameLookups 185 .name(name() + ".int_rename_lookups") 186 .desc("Number of integer rename lookups") 187 .prereq(intRenameLookups); 188 fpRenameLookups 189 .name(name() + ".fp_rename_lookups") 190 .desc("Number of floating rename lookups") 191 .prereq(fpRenameLookups); 192} 193 194template <class Impl> 195void 196DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 197{ 198 timeBuffer = tb_ptr; 199 200 // Setup wire to read information from time buffer, from IEW stage. 201 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 202 203 // Setup wire to read infromation from time buffer, from commit stage. 204 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 205 206 // Setup wire to write information to previous stages. 207 toDecode = timeBuffer->getWire(0); 208} 209 210template <class Impl> 211void 212DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 213{ 214 renameQueue = rq_ptr; 215 216 // Setup wire to write information to future stages. 217 toIEW = renameQueue->getWire(0); 218} 219 220template <class Impl> 221void 222DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 223{ 224 decodeQueue = dq_ptr; 225 226 // Setup wire to get information from decode. 227 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 228} 229 230template <class Impl> 231void 232DefaultRename<Impl>::initStage() 233{ 234 // Grab the number of free entries directly from the stages. 235 for (ThreadID tid = 0; tid < numThreads; tid++) { 236 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 237 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 238 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 239 emptyROB[tid] = true; 240 } 241} 242 243template<class Impl> 244void 245DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 246{ 247 activeThreads = at_ptr; 248} 249 250 251template <class Impl> 252void 253DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 254{ 255 for (ThreadID tid = 0; tid < numThreads; tid++) 256 renameMap[tid] = &rm_ptr[tid]; 257} 258 259template <class Impl> 260void 261DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 262{ 263 freeList = fl_ptr; 264} 265 266template<class Impl> 267void 268DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 269{ 270 scoreboard = _scoreboard; 271} 272 273template <class Impl> 274bool 275DefaultRename<Impl>::drain() 276{ 277 // Rename is ready to switch out at any time. 278 cpu->signalDrained(); 279 return true; 280} 281 282template <class Impl> 283void 284DefaultRename<Impl>::switchOut() 285{ 286 // Clear any state, fix up the rename map. 287 for (ThreadID tid = 0; tid < numThreads; tid++) { 288 typename std::list<RenameHistory>::iterator hb_it = 289 historyBuffer[tid].begin(); 290 291 while (!historyBuffer[tid].empty()) { 292 assert(hb_it != historyBuffer[tid].end()); 293 294 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 295 "number %i.\n", tid, (*hb_it).instSeqNum); 296 297 // Tell the rename map to set the architected register to the 298 // previous physical register that it was renamed to. 299 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 300 301 // Put the renamed physical register back on the free list. 302 freeList->addReg(hb_it->newPhysReg); 303 304 // Be sure to mark its register as ready if it's a misc register. 305 if (hb_it->newPhysReg >= maxPhysicalRegs) { 306 scoreboard->setReg(hb_it->newPhysReg); 307 } 308 309 historyBuffer[tid].erase(hb_it++); 310 } 311 insts[tid].clear(); 312 skidBuffer[tid].clear(); 313 } 314} 315 316template <class Impl> 317void 318DefaultRename<Impl>::takeOverFrom() 319{ 320 _status = Inactive; 321 initStage(); 322 323 // Reset all state prior to taking over from the other CPU. 324 for (ThreadID tid = 0; tid < numThreads; tid++) { 325 renameStatus[tid] = Idle; 326 327 stalls[tid].iew = false; 328 stalls[tid].commit = false; 329 serializeInst[tid] = NULL; 330 331 instsInProgress[tid] = 0; 332 333 emptyROB[tid] = true; 334 335 serializeOnNextInst[tid] = false; 336 } 337} 338 339template <class Impl> 340void 341DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 342{ 343 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 344 345 // Clear the stall signal if rename was blocked or unblocking before. 346 // If it still needs to block, the blocking should happen the next 347 // cycle and there should be space to hold everything due to the squash. 348 if (renameStatus[tid] == Blocked || 349 renameStatus[tid] == Unblocking) { 350 toDecode->renameUnblock[tid] = 1; 351 352 resumeSerialize = false; 353 serializeInst[tid] = NULL; 354 } else if (renameStatus[tid] == SerializeStall) { 355 if (serializeInst[tid]->seqNum <= squash_seq_num) { 356 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 357 resumeSerialize = true; 358 assert(serializeInst[tid]); 359 } else { 360 resumeSerialize = false; 361 toDecode->renameUnblock[tid] = 1; 362 363 serializeInst[tid] = NULL; 364 } 365 } 366 367 // Set the status to Squashing. 368 renameStatus[tid] = Squashing; 369 370 // Squash any instructions from decode. 371 unsigned squashCount = 0; 372 373 for (int i=0; i<fromDecode->size; i++) { 374 if (fromDecode->insts[i]->threadNumber == tid && 375 fromDecode->insts[i]->seqNum > squash_seq_num) { 376 fromDecode->insts[i]->setSquashed(); 377 wroteToTimeBuffer = true; 378 squashCount++; 379 } 380 381 } 382 383 // Clear the instruction list and skid buffer in case they have any 384 // insts in them. 385 insts[tid].clear(); 386 387 // Clear the skid buffer in case it has any data in it. 388 skidBuffer[tid].clear(); 389 390 doSquash(squash_seq_num, tid); 391} 392 393template <class Impl> 394void 395DefaultRename<Impl>::tick() 396{ 397 wroteToTimeBuffer = false; 398 399 blockThisCycle = false; 400 401 bool status_change = false; 402 403 toIEWIndex = 0; 404 405 sortInsts(); 406 407 list<ThreadID>::iterator threads = activeThreads->begin(); 408 list<ThreadID>::iterator end = activeThreads->end(); 409 410 // Check stall and squash signals. 411 while (threads != end) { 412 ThreadID tid = *threads++; 413 414 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 415 416 status_change = checkSignalsAndUpdate(tid) || status_change; 417 418 rename(status_change, tid); 419 } 420 421 if (status_change) { 422 updateStatus(); 423 } 424 425 if (wroteToTimeBuffer) { 426 DPRINTF(Activity, "Activity this cycle.\n"); 427 cpu->activityThisCycle(); 428 } 429 430 threads = activeThreads->begin(); 431 432 while (threads != end) { 433 ThreadID tid = *threads++; 434 435 // If we committed this cycle then doneSeqNum will be > 0 436 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 437 !fromCommit->commitInfo[tid].squash && 438 renameStatus[tid] != Squashing) { 439 440 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 441 tid); 442 } 443 } 444 445 // @todo: make into updateProgress function 446 for (ThreadID tid = 0; tid < numThreads; tid++) { 447 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 448 449 assert(instsInProgress[tid] >=0); 450 } 451 452} 453 454template<class Impl> 455void 456DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 457{ 458 // If status is Running or idle, 459 // call renameInsts() 460 // If status is Unblocking, 461 // buffer any instructions coming from decode 462 // continue trying to empty skid buffer 463 // check if stall conditions have passed 464 465 if (renameStatus[tid] == Blocked) { 466 ++renameBlockCycles; 467 } else if (renameStatus[tid] == Squashing) { 468 ++renameSquashCycles; 469 } else if (renameStatus[tid] == SerializeStall) { 470 ++renameSerializeStallCycles; 471 // If we are currently in SerializeStall and resumeSerialize 472 // was set, then that means that we are resuming serializing 473 // this cycle. Tell the previous stages to block. 474 if (resumeSerialize) { 475 resumeSerialize = false; 476 block(tid); 477 toDecode->renameUnblock[tid] = false; 478 } 479 } else if (renameStatus[tid] == Unblocking) { 480 if (resumeUnblocking) { 481 block(tid); 482 resumeUnblocking = false; 483 toDecode->renameUnblock[tid] = false; 484 } 485 } 486 487 if (renameStatus[tid] == Running || 488 renameStatus[tid] == Idle) { 489 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 490 "stage.\n", tid); 491 492 renameInsts(tid); 493 } else if (renameStatus[tid] == Unblocking) { 494 renameInsts(tid); 495 496 if (validInsts()) { 497 // Add the current inputs to the skid buffer so they can be 498 // reprocessed when this stage unblocks. 499 skidInsert(tid); 500 } 501 502 // If we switched over to blocking, then there's a potential for 503 // an overall status change. 504 status_change = unblock(tid) || status_change || blockThisCycle; 505 } 506} 507 508template <class Impl> 509void 510DefaultRename<Impl>::renameInsts(ThreadID tid) 511{ 512 // Instructions can be either in the skid buffer or the queue of 513 // instructions coming from decode, depending on the status. 514 int insts_available = renameStatus[tid] == Unblocking ? 515 skidBuffer[tid].size() : insts[tid].size(); 516 517 // Check the decode queue to see if instructions are available. 518 // If there are no available instructions to rename, then do nothing. 519 if (insts_available == 0) { 520 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 521 tid); 522 // Should I change status to idle? 523 ++renameIdleCycles; 524 return; 525 } else if (renameStatus[tid] == Unblocking) { 526 ++renameUnblockCycles; 527 } else if (renameStatus[tid] == Running) { 528 ++renameRunCycles; 529 } 530 531 DynInstPtr inst; 532 533 // Will have to do a different calculation for the number of free 534 // entries. 535 int free_rob_entries = calcFreeROBEntries(tid); 536 int free_iq_entries = calcFreeIQEntries(tid); 537 int free_lsq_entries = calcFreeLSQEntries(tid); 538 int min_free_entries = free_rob_entries; 539 540 FullSource source = ROB; 541 542 if (free_iq_entries < min_free_entries) { 543 min_free_entries = free_iq_entries; 544 source = IQ; 545 } 546 547 if (free_lsq_entries < min_free_entries) { 548 min_free_entries = free_lsq_entries; 549 source = LSQ; 550 } 551 552 // Check if there's any space left. 553 if (min_free_entries <= 0) { 554 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 555 "entries.\n" 556 "ROB has %i free entries.\n" 557 "IQ has %i free entries.\n" 558 "LSQ has %i free entries.\n", 559 tid, 560 free_rob_entries, 561 free_iq_entries, 562 free_lsq_entries); 563 564 blockThisCycle = true; 565 566 block(tid); 567 568 incrFullStat(source); 569 570 return; 571 } else if (min_free_entries < insts_available) { 572 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 573 "%i insts available, but only %i insts can be " 574 "renamed due to ROB/IQ/LSQ limits.\n", 575 tid, insts_available, min_free_entries); 576 577 insts_available = min_free_entries; 578 579 blockThisCycle = true; 580 581 incrFullStat(source); 582 } 583 584 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 585 skidBuffer[tid] : insts[tid]; 586 587 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 588 "send iew.\n", tid, insts_available); 589 590 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 591 "dispatched to IQ last cycle.\n", 592 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 593 594 // Handle serializing the next instruction if necessary. 595 if (serializeOnNextInst[tid]) { 596 if (emptyROB[tid] && instsInProgress[tid] == 0) { 597 // ROB already empty; no need to serialize. 598 serializeOnNextInst[tid] = false; 599 } else if (!insts_to_rename.empty()) { 600 insts_to_rename.front()->setSerializeBefore(); 601 } 602 } 603 604 int renamed_insts = 0; 605 606 while (insts_available > 0 && toIEWIndex < renameWidth) { 607 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 608 609 assert(!insts_to_rename.empty()); 610 611 inst = insts_to_rename.front(); 612 613 insts_to_rename.pop_front(); 614 615 if (renameStatus[tid] == Unblocking) { 616 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 617 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 618 } 619 620 if (inst->isSquashed()) { 621 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 622 "squashed, skipping.\n", tid, inst->seqNum, 623 inst->pcState()); 624 625 ++renameSquashedInsts; 626 627 // Decrement how many instructions are available. 628 --insts_available; 629 630 continue; 631 } 632 633 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 634 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 635 636 // Handle serializeAfter/serializeBefore instructions. 637 // serializeAfter marks the next instruction as serializeBefore. 638 // serializeBefore makes the instruction wait in rename until the ROB 639 // is empty. 640 641 // In this model, IPR accesses are serialize before 642 // instructions, and store conditionals are serialize after 643 // instructions. This is mainly due to lack of support for 644 // out-of-order operations of either of those classes of 645 // instructions. 646 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 647 !inst->isSerializeHandled()) { 648 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 649 650 if (!inst->isTempSerializeBefore()) { 651 renamedSerializing++; 652 inst->setSerializeHandled(); 653 } else { 654 renamedTempSerializing++; 655 } 656 657 // Change status over to SerializeStall so that other stages know 658 // what this is blocked on. 659 renameStatus[tid] = SerializeStall; 660 661 serializeInst[tid] = inst; 662 663 blockThisCycle = true; 664 665 break; 666 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 667 !inst->isSerializeHandled()) { 668 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 669 670 renamedSerializing++; 671 672 inst->setSerializeHandled(); 673 674 serializeAfter(insts_to_rename, tid); 675 } 676 677 // Check here to make sure there are enough destination registers 678 // to rename to. Otherwise block. 679 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 680 DPRINTF(Rename, "Blocking due to lack of free " 681 "physical registers to rename to.\n"); 682 blockThisCycle = true; 683 insts_to_rename.push_front(inst); 684 ++renameFullRegistersEvents; 685 686 break; 687 } 688 689 renameSrcRegs(inst, inst->threadNumber); 690 691 renameDestRegs(inst, inst->threadNumber); 692 693 ++renamed_insts; 694 695 // Put instruction in rename queue. 696 toIEW->insts[toIEWIndex] = inst; 697 ++(toIEW->size); 698 699 // Increment which instruction we're on. 700 ++toIEWIndex; 701 702 // Decrement how many instructions are available. 703 --insts_available; 704 } 705 706 instsInProgress[tid] += renamed_insts; 707 renameRenamedInsts += renamed_insts; 708 709 // If we wrote to the time buffer, record this. 710 if (toIEWIndex) { 711 wroteToTimeBuffer = true; 712 } 713 714 // Check if there's any instructions left that haven't yet been renamed. 715 // If so then block. 716 if (insts_available) { 717 blockThisCycle = true; 718 } 719 720 if (blockThisCycle) { 721 block(tid); 722 toDecode->renameUnblock[tid] = false; 723 } 724} 725 726template<class Impl> 727void 728DefaultRename<Impl>::skidInsert(ThreadID tid) 729{ 730 DynInstPtr inst = NULL; 731 732 while (!insts[tid].empty()) { 733 inst = insts[tid].front(); 734 735 insts[tid].pop_front(); 736 737 assert(tid == inst->threadNumber); 738 739 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 740 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 741 742 ++renameSkidInsts; 743 744 skidBuffer[tid].push_back(inst); 745 } 746 747 if (skidBuffer[tid].size() > skidBufferMax) 748 { 749 typename InstQueue::iterator it; 750 warn("Skidbuffer contents:\n"); 751 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 752 { 753 warn("[tid:%u]: %s [sn:%i].\n", tid, 754 (*it)->staticInst->disassemble(inst->instAddr()), 755 (*it)->seqNum); 756 } 757 panic("Skidbuffer Exceeded Max Size"); 758 } 759} 760 761template <class Impl> 762void 763DefaultRename<Impl>::sortInsts() 764{ 765 int insts_from_decode = fromDecode->size; 766#ifdef DEBUG 767 for (ThreadID tid = 0; tid < numThreads; tid++) 768 assert(insts[tid].empty()); 769#endif 770 for (int i = 0; i < insts_from_decode; ++i) { 771 DynInstPtr inst = fromDecode->insts[i]; 772 insts[inst->threadNumber].push_back(inst); 773 } 774} 775 776template<class Impl> 777bool 778DefaultRename<Impl>::skidsEmpty() 779{ 780 list<ThreadID>::iterator threads = activeThreads->begin(); 781 list<ThreadID>::iterator end = activeThreads->end(); 782 783 while (threads != end) { 784 ThreadID tid = *threads++; 785 786 if (!skidBuffer[tid].empty()) 787 return false; 788 } 789 790 return true; 791} 792 793template<class Impl> 794void 795DefaultRename<Impl>::updateStatus() 796{ 797 bool any_unblocking = false; 798 799 list<ThreadID>::iterator threads = activeThreads->begin(); 800 list<ThreadID>::iterator end = activeThreads->end(); 801 802 while (threads != end) { 803 ThreadID tid = *threads++; 804 805 if (renameStatus[tid] == Unblocking) { 806 any_unblocking = true; 807 break; 808 } 809 } 810 811 // Rename will have activity if it's unblocking. 812 if (any_unblocking) { 813 if (_status == Inactive) { 814 _status = Active; 815 816 DPRINTF(Activity, "Activating stage.\n"); 817 818 cpu->activateStage(O3CPU::RenameIdx); 819 } 820 } else { 821 // If it's not unblocking, then rename will not have any internal 822 // activity. Switch it to inactive. 823 if (_status == Active) { 824 _status = Inactive; 825 DPRINTF(Activity, "Deactivating stage.\n"); 826 827 cpu->deactivateStage(O3CPU::RenameIdx); 828 } 829 } 830} 831 832template <class Impl> 833bool 834DefaultRename<Impl>::block(ThreadID tid) 835{ 836 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 837 838 // Add the current inputs onto the skid buffer, so they can be 839 // reprocessed when this stage unblocks. 840 skidInsert(tid); 841 842 // Only signal backwards to block if the previous stages do not think 843 // rename is already blocked. 844 if (renameStatus[tid] != Blocked) { 845 // If resumeUnblocking is set, we unblocked during the squash, 846 // but now we're have unblocking status. We need to tell earlier 847 // stages to block. 848 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 849 toDecode->renameBlock[tid] = true; 850 toDecode->renameUnblock[tid] = false; 851 wroteToTimeBuffer = true; 852 } 853 854 // Rename can not go from SerializeStall to Blocked, otherwise 855 // it would not know to complete the serialize stall. 856 if (renameStatus[tid] != SerializeStall) { 857 // Set status to Blocked. 858 renameStatus[tid] = Blocked; 859 return true; 860 } 861 } 862 863 return false; 864} 865 866template <class Impl> 867bool 868DefaultRename<Impl>::unblock(ThreadID tid) 869{ 870 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 871 872 // Rename is done unblocking if the skid buffer is empty. 873 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 874 875 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 876 877 toDecode->renameUnblock[tid] = true; 878 wroteToTimeBuffer = true; 879 880 renameStatus[tid] = Running; 881 return true; 882 } 883 884 return false; 885} 886 887template <class Impl> 888void 889DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 890{ 891 typename std::list<RenameHistory>::iterator hb_it = 892 historyBuffer[tid].begin(); 893 894 // After a syscall squashes everything, the history buffer may be empty 895 // but the ROB may still be squashing instructions. 896 if (historyBuffer[tid].empty()) { 897 return; 898 } 899 900 // Go through the most recent instructions, undoing the mappings 901 // they did and freeing up the registers. 902 while (!historyBuffer[tid].empty() && 903 (*hb_it).instSeqNum > squashed_seq_num) { 904 assert(hb_it != historyBuffer[tid].end()); 905 906 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 907 "number %i.\n", tid, (*hb_it).instSeqNum); 908 909 // Tell the rename map to set the architected register to the 910 // previous physical register that it was renamed to. 911 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 912 913 // Put the renamed physical register back on the free list. 914 freeList->addReg(hb_it->newPhysReg); 915 916 // Be sure to mark its register as ready if it's a misc register. 917 if (hb_it->newPhysReg >= maxPhysicalRegs) { 918 scoreboard->setReg(hb_it->newPhysReg); 919 } 920 921 historyBuffer[tid].erase(hb_it++); 922 923 ++renameUndoneMaps; 924 } 925} 926 927template<class Impl> 928void 929DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 930{ 931 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 932 "history buffer %u (size=%i), until [sn:%lli].\n", 933 tid, tid, historyBuffer[tid].size(), inst_seq_num); 934 935 typename std::list<RenameHistory>::iterator hb_it = 936 historyBuffer[tid].end(); 937 938 --hb_it; 939 940 if (historyBuffer[tid].empty()) { 941 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 942 return; 943 } else if (hb_it->instSeqNum > inst_seq_num) { 944 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 945 "that a syscall happened recently.\n", tid); 946 return; 947 } 948 949 // Commit all the renames up until (and including) the committed sequence 950 // number. Some or even all of the committed instructions may not have 951 // rename histories if they did not have destination registers that were 952 // renamed. 953 while (!historyBuffer[tid].empty() && 954 hb_it != historyBuffer[tid].end() && 955 (*hb_it).instSeqNum <= inst_seq_num) { 956 957 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 958 "[sn:%lli].\n", 959 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 960 961 freeList->addReg((*hb_it).prevPhysReg); 962 ++renameCommittedMaps; 963 964 historyBuffer[tid].erase(hb_it--); 965 } 966} 967 968template <class Impl> 969inline void 970DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 971{ 972 assert(renameMap[tid] != 0); 973 974 unsigned num_src_regs = inst->numSrcRegs(); 975 976 // Get the architectual register numbers from the source and 977 // destination operands, and redirect them to the right register. 978 // Will need to mark dependencies though. 979 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 980 RegIndex src_reg = inst->srcRegIdx(src_idx); 981 RegIndex flat_src_reg = src_reg; 982 if (src_reg < TheISA::FP_Base_DepTag) { 983 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 984 DPRINTF(Rename, "Flattening index %d to %d.\n", 985 (int)src_reg, (int)flat_src_reg); 986 } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 987 src_reg = src_reg - TheISA::FP_Base_DepTag; 988 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 989 DPRINTF(Rename, "Flattening index %d to %d.\n", 990 (int)src_reg, (int)flat_src_reg); 991 flat_src_reg += TheISA::NumIntRegs; 992 } else if (src_reg < TheISA::Max_DepTag) { 993 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 994 TheISA::NumFloatRegs + TheISA::NumIntRegs; 995 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 996 src_reg, flat_src_reg); 997 } else { 998 panic("Reg index is out of bound: %d.", src_reg); 999 } 1000 1001 inst->flattenSrcReg(src_idx, flat_src_reg); 1002 1003 // Look up the source registers to get the phys. register they've 1004 // been renamed to, and set the sources to those registers. 1005 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 1006 1007 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 1008 "physical reg %i.\n", tid, (int)flat_src_reg, 1009 (int)renamed_reg); 1010 1011 inst->renameSrcReg(src_idx, renamed_reg); 1012 1013 // See if the register is ready or not. 1014 if (scoreboard->getReg(renamed_reg) == true) { 1015 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1016 tid, renamed_reg); 1017 1018 inst->markSrcRegReady(src_idx); 1019 } else { 1020 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1021 tid, renamed_reg); 1022 } 1023 1024 ++renameRenameLookups; 1025 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 1026 } 1027} 1028 1029template <class Impl> 1030inline void 1031DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1032{ 1033 typename RenameMap::RenameInfo rename_result; 1034 1035 unsigned num_dest_regs = inst->numDestRegs(); 1036 1037 // Rename the destination registers. 1038 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1039 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1040 RegIndex flat_dest_reg = dest_reg; 1041 if (dest_reg < TheISA::FP_Base_DepTag) { 1042 // Integer registers are flattened. 1043 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 1044 DPRINTF(Rename, "Flattening index %d to %d.\n", 1045 (int)dest_reg, (int)flat_dest_reg); 1046 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { 1047 dest_reg = dest_reg - TheISA::FP_Base_DepTag; 1048 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 1049 DPRINTF(Rename, "Flattening index %d to %d.\n", 1050 (int)dest_reg, (int)flat_dest_reg); 1051 flat_dest_reg += TheISA::NumIntRegs; 1052 } else if (dest_reg < TheISA::Max_DepTag) { 1053 // Floating point and Miscellaneous registers need their indexes 1054 // adjusted to account for the expanded number of flattened int regs. 1055 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 1056 TheISA::NumIntRegs + TheISA::NumFloatRegs; 1057 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 1058 dest_reg, flat_dest_reg); 1059 } else { 1060 panic("Reg index is out of bound: %d.", dest_reg); 1061 } 1062 1063 inst->flattenDestReg(dest_idx, flat_dest_reg); 1064 1065 // Get the physical register that the destination will be 1066 // renamed to. 1067 rename_result = renameMap[tid]->rename(flat_dest_reg); 1068 1069 //Mark Scoreboard entry as not ready 1070 if (dest_reg < TheISA::Ctrl_Base_DepTag) 1071 scoreboard->unsetReg(rename_result.first); 1072 1073 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1074 "reg %i.\n", tid, (int)flat_dest_reg, 1075 (int)rename_result.first); 1076 1077 // Record the rename information so that a history can be kept. 1078 RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 1079 rename_result.first, 1080 rename_result.second); 1081 1082 historyBuffer[tid].push_front(hb_entry); 1083 1084 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1085 "(size=%i), [sn:%lli].\n",tid, 1086 historyBuffer[tid].size(), 1087 (*historyBuffer[tid].begin()).instSeqNum); 1088 1089 // Tell the instruction to rename the appropriate destination 1090 // register (dest_idx) to the new physical register 1091 // (rename_result.first), and record the previous physical 1092 // register that the same logical register was renamed to 1093 // (rename_result.second). 1094 inst->renameDestReg(dest_idx, 1095 rename_result.first, 1096 rename_result.second); 1097 1098 ++renameRenamedOperands; 1099 } 1100} 1101 1102template <class Impl> 1103inline int 1104DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1105{ 1106 int num_free = freeEntries[tid].robEntries - 1107 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1108 1109 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1110 1111 return num_free; 1112} 1113 1114template <class Impl> 1115inline int 1116DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1117{ 1118 int num_free = freeEntries[tid].iqEntries - 1119 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1120 1121 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1122 1123 return num_free; 1124} 1125 1126template <class Impl> 1127inline int 1128DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 1129{ 1130 int num_free = freeEntries[tid].lsqEntries - 1131 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1132 1133 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1134 1135 return num_free; 1136} 1137 1138template <class Impl> 1139unsigned 1140DefaultRename<Impl>::validInsts() 1141{ 1142 unsigned inst_count = 0; 1143 1144 for (int i=0; i<fromDecode->size; i++) { 1145 if (!fromDecode->insts[i]->isSquashed()) 1146 inst_count++; 1147 } 1148 1149 return inst_count; 1150} 1151 1152template <class Impl> 1153void 1154DefaultRename<Impl>::readStallSignals(ThreadID tid) 1155{ 1156 if (fromIEW->iewBlock[tid]) { 1157 stalls[tid].iew = true; 1158 } 1159 1160 if (fromIEW->iewUnblock[tid]) { 1161 assert(stalls[tid].iew); 1162 stalls[tid].iew = false; 1163 } 1164 1165 if (fromCommit->commitBlock[tid]) { 1166 stalls[tid].commit = true; 1167 } 1168 1169 if (fromCommit->commitUnblock[tid]) { 1170 assert(stalls[tid].commit); 1171 stalls[tid].commit = false; 1172 } 1173} 1174 1175template <class Impl> 1176bool 1177DefaultRename<Impl>::checkStall(ThreadID tid) 1178{ 1179 bool ret_val = false; 1180 1181 if (stalls[tid].iew) { 1182 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1183 ret_val = true; 1184 } else if (stalls[tid].commit) { 1185 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1186 ret_val = true; 1187 } else if (calcFreeROBEntries(tid) <= 0) { 1188 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1189 ret_val = true; 1190 } else if (calcFreeIQEntries(tid) <= 0) { 1191 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1192 ret_val = true; 1193 } else if (calcFreeLSQEntries(tid) <= 0) { 1194 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1195 ret_val = true; 1196 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1197 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1198 ret_val = true; 1199 } else if (renameStatus[tid] == SerializeStall && 1200 (!emptyROB[tid] || instsInProgress[tid])) { 1201 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1202 "empty.\n", 1203 tid); 1204 ret_val = true; 1205 } 1206 1207 return ret_val; 1208} 1209 1210template <class Impl> 1211void 1212DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1213{ 1214 bool updated = false; 1215 if (fromIEW->iewInfo[tid].usedIQ) { 1216 freeEntries[tid].iqEntries = 1217 fromIEW->iewInfo[tid].freeIQEntries; 1218 updated = true; 1219 } 1220 1221 if (fromIEW->iewInfo[tid].usedLSQ) { 1222 freeEntries[tid].lsqEntries = 1223 fromIEW->iewInfo[tid].freeLSQEntries; 1224 updated = true; 1225 } 1226 1227 if (fromCommit->commitInfo[tid].usedROB) { 1228 freeEntries[tid].robEntries = 1229 fromCommit->commitInfo[tid].freeROBEntries; 1230 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1231 updated = true; 1232 } 1233 1234 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1235 tid, 1236 freeEntries[tid].iqEntries, 1237 freeEntries[tid].robEntries, 1238 freeEntries[tid].lsqEntries); 1239 1240 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1241 tid, instsInProgress[tid]); 1242} 1243 1244template <class Impl> 1245bool 1246DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1247{ 1248 // Check if there's a squash signal, squash if there is 1249 // Check stall signals, block if necessary. 1250 // If status was blocked 1251 // check if stall conditions have passed 1252 // if so then go to unblocking 1253 // If status was Squashing 1254 // check if squashing is not high. Switch to running this cycle. 1255 // If status was serialize stall 1256 // check if ROB is empty and no insts are in flight to the ROB 1257 1258 readFreeEntries(tid); 1259 readStallSignals(tid); 1260 1261 if (fromCommit->commitInfo[tid].squash) { 1262 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1263 "commit.\n", tid); 1264 1265 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1266 1267 return true; 1268 } 1269 1270 if (fromCommit->commitInfo[tid].robSquashing) { 1271 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1272 1273 renameStatus[tid] = Squashing; 1274 1275 return true; 1276 } 1277 1278 if (checkStall(tid)) { 1279 return block(tid); 1280 } 1281 1282 if (renameStatus[tid] == Blocked) { 1283 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1284 tid); 1285 1286 renameStatus[tid] = Unblocking; 1287 1288 unblock(tid); 1289 1290 return true; 1291 } 1292 1293 if (renameStatus[tid] == Squashing) { 1294 // Switch status to running if rename isn't being told to block or 1295 // squash this cycle. 1296 if (resumeSerialize) { 1297 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1298 tid); 1299 1300 renameStatus[tid] = SerializeStall; 1301 return true; 1302 } else if (resumeUnblocking) { 1303 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1304 tid); 1305 renameStatus[tid] = Unblocking; 1306 return true; 1307 } else { 1308 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1309 tid); 1310 1311 renameStatus[tid] = Running; 1312 return false; 1313 } 1314 } 1315 1316 if (renameStatus[tid] == SerializeStall) { 1317 // Stall ends once the ROB is free. 1318 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1319 "unblocking.\n", tid); 1320 1321 DynInstPtr serial_inst = serializeInst[tid]; 1322 1323 renameStatus[tid] = Unblocking; 1324 1325 unblock(tid); 1326 1327 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1328 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1329 1330 // Put instruction into queue here. 1331 serial_inst->clearSerializeBefore(); 1332 1333 if (!skidBuffer[tid].empty()) { 1334 skidBuffer[tid].push_front(serial_inst); 1335 } else { 1336 insts[tid].push_front(serial_inst); 1337 } 1338 1339 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1340 " Adding to front of list.\n", tid); 1341 1342 serializeInst[tid] = NULL; 1343 1344 return true; 1345 } 1346 1347 // If we've reached this point, we have not gotten any signals that 1348 // cause rename to change its status. Rename remains the same as before. 1349 return false; 1350} 1351 1352template<class Impl> 1353void 1354DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1355{ 1356 if (inst_list.empty()) { 1357 // Mark a bit to say that I must serialize on the next instruction. 1358 serializeOnNextInst[tid] = true; 1359 return; 1360 } 1361 1362 // Set the next instruction as serializing. 1363 inst_list.front()->setSerializeBefore(); 1364} 1365 1366template <class Impl> 1367inline void 1368DefaultRename<Impl>::incrFullStat(const FullSource &source) 1369{ 1370 switch (source) { 1371 case ROB: 1372 ++renameROBFullEvents; 1373 break; 1374 case IQ: 1375 ++renameIQFullEvents; 1376 break; 1377 case LSQ: 1378 ++renameLSQFullEvents; 1379 break; 1380 default: 1381 panic("Rename full stall stat should be incremented for a reason!"); 1382 break; 1383 } 1384} 1385 1386template <class Impl> 1387void 1388DefaultRename<Impl>::dumpHistory() 1389{ 1390 typename std::list<RenameHistory>::iterator buf_it; 1391 1392 for (ThreadID tid = 0; tid < numThreads; tid++) { 1393 1394 buf_it = historyBuffer[tid].begin(); 1395 1396 while (buf_it != historyBuffer[tid].end()) { 1397 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1398 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1399 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1400 1401 buf_it++; 1402 } 1403 } 1404} 1405