rename_impl.hh revision 6313 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include <list>
33
34#include "arch/isa_traits.hh"
35#include "arch/regfile.hh"
36#include "config/full_system.hh"
37#include "cpu/o3/rename.hh"
38#include "params/DerivO3CPU.hh"
39
40using namespace std;
41
42template <class Impl>
43DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
44    : cpu(_cpu),
45      iewToRenameDelay(params->iewToRenameDelay),
46      decodeToRenameDelay(params->decodeToRenameDelay),
47      commitToRenameDelay(params->commitToRenameDelay),
48      renameWidth(params->renameWidth),
49      commitWidth(params->commitWidth),
50      resumeSerialize(false),
51      resumeUnblocking(false),
52      numThreads(params->numThreads),
53      maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
54{
55    _status = Inactive;
56
57    for (ThreadID tid = 0; tid < numThreads; tid++) {
58        renameStatus[tid] = Idle;
59
60        freeEntries[tid].iqEntries = 0;
61        freeEntries[tid].lsqEntries = 0;
62        freeEntries[tid].robEntries = 0;
63
64        stalls[tid].iew = false;
65        stalls[tid].commit = false;
66        serializeInst[tid] = NULL;
67
68        instsInProgress[tid] = 0;
69
70        emptyROB[tid] = true;
71
72        serializeOnNextInst[tid] = false;
73    }
74
75    // @todo: Make into a parameter.
76    skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
77}
78
79template <class Impl>
80std::string
81DefaultRename<Impl>::name() const
82{
83    return cpu->name() + ".rename";
84}
85
86template <class Impl>
87void
88DefaultRename<Impl>::regStats()
89{
90    renameSquashCycles
91        .name(name() + ".RENAME:SquashCycles")
92        .desc("Number of cycles rename is squashing")
93        .prereq(renameSquashCycles);
94    renameIdleCycles
95        .name(name() + ".RENAME:IdleCycles")
96        .desc("Number of cycles rename is idle")
97        .prereq(renameIdleCycles);
98    renameBlockCycles
99        .name(name() + ".RENAME:BlockCycles")
100        .desc("Number of cycles rename is blocking")
101        .prereq(renameBlockCycles);
102    renameSerializeStallCycles
103        .name(name() + ".RENAME:serializeStallCycles")
104        .desc("count of cycles rename stalled for serializing inst")
105        .flags(Stats::total);
106    renameRunCycles
107        .name(name() + ".RENAME:RunCycles")
108        .desc("Number of cycles rename is running")
109        .prereq(renameIdleCycles);
110    renameUnblockCycles
111        .name(name() + ".RENAME:UnblockCycles")
112        .desc("Number of cycles rename is unblocking")
113        .prereq(renameUnblockCycles);
114    renameRenamedInsts
115        .name(name() + ".RENAME:RenamedInsts")
116        .desc("Number of instructions processed by rename")
117        .prereq(renameRenamedInsts);
118    renameSquashedInsts
119        .name(name() + ".RENAME:SquashedInsts")
120        .desc("Number of squashed instructions processed by rename")
121        .prereq(renameSquashedInsts);
122    renameROBFullEvents
123        .name(name() + ".RENAME:ROBFullEvents")
124        .desc("Number of times rename has blocked due to ROB full")
125        .prereq(renameROBFullEvents);
126    renameIQFullEvents
127        .name(name() + ".RENAME:IQFullEvents")
128        .desc("Number of times rename has blocked due to IQ full")
129        .prereq(renameIQFullEvents);
130    renameLSQFullEvents
131        .name(name() + ".RENAME:LSQFullEvents")
132        .desc("Number of times rename has blocked due to LSQ full")
133        .prereq(renameLSQFullEvents);
134    renameFullRegistersEvents
135        .name(name() + ".RENAME:FullRegisterEvents")
136        .desc("Number of times there has been no free registers")
137        .prereq(renameFullRegistersEvents);
138    renameRenamedOperands
139        .name(name() + ".RENAME:RenamedOperands")
140        .desc("Number of destination operands rename has renamed")
141        .prereq(renameRenamedOperands);
142    renameRenameLookups
143        .name(name() + ".RENAME:RenameLookups")
144        .desc("Number of register rename lookups that rename has made")
145        .prereq(renameRenameLookups);
146    renameCommittedMaps
147        .name(name() + ".RENAME:CommittedMaps")
148        .desc("Number of HB maps that are committed")
149        .prereq(renameCommittedMaps);
150    renameUndoneMaps
151        .name(name() + ".RENAME:UndoneMaps")
152        .desc("Number of HB maps that are undone due to squashing")
153        .prereq(renameUndoneMaps);
154    renamedSerializing
155        .name(name() + ".RENAME:serializingInsts")
156        .desc("count of serializing insts renamed")
157        .flags(Stats::total)
158        ;
159    renamedTempSerializing
160        .name(name() + ".RENAME:tempSerializingInsts")
161        .desc("count of temporary serializing insts renamed")
162        .flags(Stats::total)
163        ;
164    renameSkidInsts
165        .name(name() + ".RENAME:skidInsts")
166        .desc("count of insts added to the skid buffer")
167        .flags(Stats::total)
168        ;
169}
170
171template <class Impl>
172void
173DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
174{
175    timeBuffer = tb_ptr;
176
177    // Setup wire to read information from time buffer, from IEW stage.
178    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
179
180    // Setup wire to read infromation from time buffer, from commit stage.
181    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
182
183    // Setup wire to write information to previous stages.
184    toDecode = timeBuffer->getWire(0);
185}
186
187template <class Impl>
188void
189DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
190{
191    renameQueue = rq_ptr;
192
193    // Setup wire to write information to future stages.
194    toIEW = renameQueue->getWire(0);
195}
196
197template <class Impl>
198void
199DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
200{
201    decodeQueue = dq_ptr;
202
203    // Setup wire to get information from decode.
204    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
205}
206
207template <class Impl>
208void
209DefaultRename<Impl>::initStage()
210{
211    // Grab the number of free entries directly from the stages.
212    for (ThreadID tid = 0; tid < numThreads; tid++) {
213        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
214        freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
215        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
216        emptyROB[tid] = true;
217    }
218}
219
220template<class Impl>
221void
222DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
223{
224    activeThreads = at_ptr;
225}
226
227
228template <class Impl>
229void
230DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
231{
232    for (ThreadID tid = 0; tid < numThreads; tid++)
233        renameMap[tid] = &rm_ptr[tid];
234}
235
236template <class Impl>
237void
238DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
239{
240    freeList = fl_ptr;
241}
242
243template<class Impl>
244void
245DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
246{
247    scoreboard = _scoreboard;
248}
249
250template <class Impl>
251bool
252DefaultRename<Impl>::drain()
253{
254    // Rename is ready to switch out at any time.
255    cpu->signalDrained();
256    return true;
257}
258
259template <class Impl>
260void
261DefaultRename<Impl>::switchOut()
262{
263    // Clear any state, fix up the rename map.
264    for (ThreadID tid = 0; tid < numThreads; tid++) {
265        typename std::list<RenameHistory>::iterator hb_it =
266            historyBuffer[tid].begin();
267
268        while (!historyBuffer[tid].empty()) {
269            assert(hb_it != historyBuffer[tid].end());
270
271            DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
272                    "number %i.\n", tid, (*hb_it).instSeqNum);
273
274            // Tell the rename map to set the architected register to the
275            // previous physical register that it was renamed to.
276            renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
277
278            // Put the renamed physical register back on the free list.
279            freeList->addReg(hb_it->newPhysReg);
280
281            // Be sure to mark its register as ready if it's a misc register.
282            if (hb_it->newPhysReg >= maxPhysicalRegs) {
283                scoreboard->setReg(hb_it->newPhysReg);
284            }
285
286            historyBuffer[tid].erase(hb_it++);
287        }
288        insts[tid].clear();
289        skidBuffer[tid].clear();
290    }
291}
292
293template <class Impl>
294void
295DefaultRename<Impl>::takeOverFrom()
296{
297    _status = Inactive;
298    initStage();
299
300    // Reset all state prior to taking over from the other CPU.
301    for (ThreadID tid = 0; tid < numThreads; tid++) {
302        renameStatus[tid] = Idle;
303
304        stalls[tid].iew = false;
305        stalls[tid].commit = false;
306        serializeInst[tid] = NULL;
307
308        instsInProgress[tid] = 0;
309
310        emptyROB[tid] = true;
311
312        serializeOnNextInst[tid] = false;
313    }
314}
315
316template <class Impl>
317void
318DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
319{
320    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
321
322    // Clear the stall signal if rename was blocked or unblocking before.
323    // If it still needs to block, the blocking should happen the next
324    // cycle and there should be space to hold everything due to the squash.
325    if (renameStatus[tid] == Blocked ||
326        renameStatus[tid] == Unblocking) {
327        toDecode->renameUnblock[tid] = 1;
328
329        resumeSerialize = false;
330        serializeInst[tid] = NULL;
331    } else if (renameStatus[tid] == SerializeStall) {
332        if (serializeInst[tid]->seqNum <= squash_seq_num) {
333            DPRINTF(Rename, "Rename will resume serializing after squash\n");
334            resumeSerialize = true;
335            assert(serializeInst[tid]);
336        } else {
337            resumeSerialize = false;
338            toDecode->renameUnblock[tid] = 1;
339
340            serializeInst[tid] = NULL;
341        }
342    }
343
344    // Set the status to Squashing.
345    renameStatus[tid] = Squashing;
346
347    // Squash any instructions from decode.
348    unsigned squashCount = 0;
349
350    for (int i=0; i<fromDecode->size; i++) {
351        if (fromDecode->insts[i]->threadNumber == tid &&
352            fromDecode->insts[i]->seqNum > squash_seq_num) {
353            fromDecode->insts[i]->setSquashed();
354            wroteToTimeBuffer = true;
355            squashCount++;
356        }
357
358    }
359
360    // Clear the instruction list and skid buffer in case they have any
361    // insts in them.
362    insts[tid].clear();
363
364    // Clear the skid buffer in case it has any data in it.
365    skidBuffer[tid].clear();
366
367    doSquash(squash_seq_num, tid);
368}
369
370template <class Impl>
371void
372DefaultRename<Impl>::tick()
373{
374    wroteToTimeBuffer = false;
375
376    blockThisCycle = false;
377
378    bool status_change = false;
379
380    toIEWIndex = 0;
381
382    sortInsts();
383
384    list<ThreadID>::iterator threads = activeThreads->begin();
385    list<ThreadID>::iterator end = activeThreads->end();
386
387    // Check stall and squash signals.
388    while (threads != end) {
389        ThreadID tid = *threads++;
390
391        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
392
393        status_change = checkSignalsAndUpdate(tid) || status_change;
394
395        rename(status_change, tid);
396    }
397
398    if (status_change) {
399        updateStatus();
400    }
401
402    if (wroteToTimeBuffer) {
403        DPRINTF(Activity, "Activity this cycle.\n");
404        cpu->activityThisCycle();
405    }
406
407    threads = activeThreads->begin();
408
409    while (threads != end) {
410        ThreadID tid = *threads++;
411
412        // If we committed this cycle then doneSeqNum will be > 0
413        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
414            !fromCommit->commitInfo[tid].squash &&
415            renameStatus[tid] != Squashing) {
416
417            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
418                                  tid);
419        }
420    }
421
422    // @todo: make into updateProgress function
423    for (ThreadID tid = 0; tid < numThreads; tid++) {
424        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
425
426        assert(instsInProgress[tid] >=0);
427    }
428
429}
430
431template<class Impl>
432void
433DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
434{
435    // If status is Running or idle,
436    //     call renameInsts()
437    // If status is Unblocking,
438    //     buffer any instructions coming from decode
439    //     continue trying to empty skid buffer
440    //     check if stall conditions have passed
441
442    if (renameStatus[tid] == Blocked) {
443        ++renameBlockCycles;
444    } else if (renameStatus[tid] == Squashing) {
445        ++renameSquashCycles;
446    } else if (renameStatus[tid] == SerializeStall) {
447        ++renameSerializeStallCycles;
448        // If we are currently in SerializeStall and resumeSerialize
449        // was set, then that means that we are resuming serializing
450        // this cycle.  Tell the previous stages to block.
451        if (resumeSerialize) {
452            resumeSerialize = false;
453            block(tid);
454            toDecode->renameUnblock[tid] = false;
455        }
456    } else if (renameStatus[tid] == Unblocking) {
457        if (resumeUnblocking) {
458            block(tid);
459            resumeUnblocking = false;
460            toDecode->renameUnblock[tid] = false;
461        }
462    }
463
464    if (renameStatus[tid] == Running ||
465        renameStatus[tid] == Idle) {
466        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
467                "stage.\n", tid);
468
469        renameInsts(tid);
470    } else if (renameStatus[tid] == Unblocking) {
471        renameInsts(tid);
472
473        if (validInsts()) {
474            // Add the current inputs to the skid buffer so they can be
475            // reprocessed when this stage unblocks.
476            skidInsert(tid);
477        }
478
479        // If we switched over to blocking, then there's a potential for
480        // an overall status change.
481        status_change = unblock(tid) || status_change || blockThisCycle;
482    }
483}
484
485template <class Impl>
486void
487DefaultRename<Impl>::renameInsts(ThreadID tid)
488{
489    // Instructions can be either in the skid buffer or the queue of
490    // instructions coming from decode, depending on the status.
491    int insts_available = renameStatus[tid] == Unblocking ?
492        skidBuffer[tid].size() : insts[tid].size();
493
494    // Check the decode queue to see if instructions are available.
495    // If there are no available instructions to rename, then do nothing.
496    if (insts_available == 0) {
497        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
498                tid);
499        // Should I change status to idle?
500        ++renameIdleCycles;
501        return;
502    } else if (renameStatus[tid] == Unblocking) {
503        ++renameUnblockCycles;
504    } else if (renameStatus[tid] == Running) {
505        ++renameRunCycles;
506    }
507
508    DynInstPtr inst;
509
510    // Will have to do a different calculation for the number of free
511    // entries.
512    int free_rob_entries = calcFreeROBEntries(tid);
513    int free_iq_entries  = calcFreeIQEntries(tid);
514    int free_lsq_entries = calcFreeLSQEntries(tid);
515    int min_free_entries = free_rob_entries;
516
517    FullSource source = ROB;
518
519    if (free_iq_entries < min_free_entries) {
520        min_free_entries = free_iq_entries;
521        source = IQ;
522    }
523
524    if (free_lsq_entries < min_free_entries) {
525        min_free_entries = free_lsq_entries;
526        source = LSQ;
527    }
528
529    // Check if there's any space left.
530    if (min_free_entries <= 0) {
531        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
532                "entries.\n"
533                "ROB has %i free entries.\n"
534                "IQ has %i free entries.\n"
535                "LSQ has %i free entries.\n",
536                tid,
537                free_rob_entries,
538                free_iq_entries,
539                free_lsq_entries);
540
541        blockThisCycle = true;
542
543        block(tid);
544
545        incrFullStat(source);
546
547        return;
548    } else if (min_free_entries < insts_available) {
549        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
550                "%i insts available, but only %i insts can be "
551                "renamed due to ROB/IQ/LSQ limits.\n",
552                tid, insts_available, min_free_entries);
553
554        insts_available = min_free_entries;
555
556        blockThisCycle = true;
557
558        incrFullStat(source);
559    }
560
561    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
562        skidBuffer[tid] : insts[tid];
563
564    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
565            "send iew.\n", tid, insts_available);
566
567    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
568            "dispatched to IQ last cycle.\n",
569            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
570
571    // Handle serializing the next instruction if necessary.
572    if (serializeOnNextInst[tid]) {
573        if (emptyROB[tid] && instsInProgress[tid] == 0) {
574            // ROB already empty; no need to serialize.
575            serializeOnNextInst[tid] = false;
576        } else if (!insts_to_rename.empty()) {
577            insts_to_rename.front()->setSerializeBefore();
578        }
579    }
580
581    int renamed_insts = 0;
582
583    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
584        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
585
586        assert(!insts_to_rename.empty());
587
588        inst = insts_to_rename.front();
589
590        insts_to_rename.pop_front();
591
592        if (renameStatus[tid] == Unblocking) {
593            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
594                    "skidBuffer\n",
595                    tid, inst->seqNum, inst->readPC());
596        }
597
598        if (inst->isSquashed()) {
599            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
600                    "squashed, skipping.\n",
601                    tid, inst->seqNum, inst->readPC());
602
603            ++renameSquashedInsts;
604
605            // Decrement how many instructions are available.
606            --insts_available;
607
608            continue;
609        }
610
611        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
612                "PC %#x.\n",
613                tid, inst->seqNum, inst->readPC());
614
615        // Handle serializeAfter/serializeBefore instructions.
616        // serializeAfter marks the next instruction as serializeBefore.
617        // serializeBefore makes the instruction wait in rename until the ROB
618        // is empty.
619
620        // In this model, IPR accesses are serialize before
621        // instructions, and store conditionals are serialize after
622        // instructions.  This is mainly due to lack of support for
623        // out-of-order operations of either of those classes of
624        // instructions.
625        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
626            !inst->isSerializeHandled()) {
627            DPRINTF(Rename, "Serialize before instruction encountered.\n");
628
629            if (!inst->isTempSerializeBefore()) {
630                renamedSerializing++;
631                inst->setSerializeHandled();
632            } else {
633                renamedTempSerializing++;
634            }
635
636            // Change status over to SerializeStall so that other stages know
637            // what this is blocked on.
638            renameStatus[tid] = SerializeStall;
639
640            serializeInst[tid] = inst;
641
642            blockThisCycle = true;
643
644            break;
645        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
646                   !inst->isSerializeHandled()) {
647            DPRINTF(Rename, "Serialize after instruction encountered.\n");
648
649            renamedSerializing++;
650
651            inst->setSerializeHandled();
652
653            serializeAfter(insts_to_rename, tid);
654        }
655
656        // Check here to make sure there are enough destination registers
657        // to rename to.  Otherwise block.
658        if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
659            DPRINTF(Rename, "Blocking due to lack of free "
660                    "physical registers to rename to.\n");
661            blockThisCycle = true;
662            insts_to_rename.push_front(inst);
663            ++renameFullRegistersEvents;
664
665            break;
666        }
667
668        renameSrcRegs(inst, inst->threadNumber);
669
670        renameDestRegs(inst, inst->threadNumber);
671
672        ++renamed_insts;
673
674        // Put instruction in rename queue.
675        toIEW->insts[toIEWIndex] = inst;
676        ++(toIEW->size);
677
678        // Increment which instruction we're on.
679        ++toIEWIndex;
680
681        // Decrement how many instructions are available.
682        --insts_available;
683    }
684
685    instsInProgress[tid] += renamed_insts;
686    renameRenamedInsts += renamed_insts;
687
688    // If we wrote to the time buffer, record this.
689    if (toIEWIndex) {
690        wroteToTimeBuffer = true;
691    }
692
693    // Check if there's any instructions left that haven't yet been renamed.
694    // If so then block.
695    if (insts_available) {
696        blockThisCycle = true;
697    }
698
699    if (blockThisCycle) {
700        block(tid);
701        toDecode->renameUnblock[tid] = false;
702    }
703}
704
705template<class Impl>
706void
707DefaultRename<Impl>::skidInsert(ThreadID tid)
708{
709    DynInstPtr inst = NULL;
710
711    while (!insts[tid].empty()) {
712        inst = insts[tid].front();
713
714        insts[tid].pop_front();
715
716        assert(tid == inst->threadNumber);
717
718        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
719                "skidBuffer\n", tid, inst->seqNum, inst->readPC());
720
721        ++renameSkidInsts;
722
723        skidBuffer[tid].push_back(inst);
724    }
725
726    if (skidBuffer[tid].size() > skidBufferMax)
727    {
728        typename InstQueue::iterator it;
729        warn("Skidbuffer contents:\n");
730        for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
731        {
732            warn("[tid:%u]: %s [sn:%i].\n", tid,
733                    (*it)->staticInst->disassemble(inst->readPC()),
734                    (*it)->seqNum);
735        }
736        panic("Skidbuffer Exceeded Max Size");
737    }
738}
739
740template <class Impl>
741void
742DefaultRename<Impl>::sortInsts()
743{
744    int insts_from_decode = fromDecode->size;
745#ifdef DEBUG
746    for (ThreadID tid = 0; tid < numThreads; tid++)
747        assert(insts[tid].empty());
748#endif
749    for (int i = 0; i < insts_from_decode; ++i) {
750        DynInstPtr inst = fromDecode->insts[i];
751        insts[inst->threadNumber].push_back(inst);
752    }
753}
754
755template<class Impl>
756bool
757DefaultRename<Impl>::skidsEmpty()
758{
759    list<ThreadID>::iterator threads = activeThreads->begin();
760    list<ThreadID>::iterator end = activeThreads->end();
761
762    while (threads != end) {
763        ThreadID tid = *threads++;
764
765        if (!skidBuffer[tid].empty())
766            return false;
767    }
768
769    return true;
770}
771
772template<class Impl>
773void
774DefaultRename<Impl>::updateStatus()
775{
776    bool any_unblocking = false;
777
778    list<ThreadID>::iterator threads = activeThreads->begin();
779    list<ThreadID>::iterator end = activeThreads->end();
780
781    while (threads != end) {
782        ThreadID tid = *threads++;
783
784        if (renameStatus[tid] == Unblocking) {
785            any_unblocking = true;
786            break;
787        }
788    }
789
790    // Rename will have activity if it's unblocking.
791    if (any_unblocking) {
792        if (_status == Inactive) {
793            _status = Active;
794
795            DPRINTF(Activity, "Activating stage.\n");
796
797            cpu->activateStage(O3CPU::RenameIdx);
798        }
799    } else {
800        // If it's not unblocking, then rename will not have any internal
801        // activity.  Switch it to inactive.
802        if (_status == Active) {
803            _status = Inactive;
804            DPRINTF(Activity, "Deactivating stage.\n");
805
806            cpu->deactivateStage(O3CPU::RenameIdx);
807        }
808    }
809}
810
811template <class Impl>
812bool
813DefaultRename<Impl>::block(ThreadID tid)
814{
815    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
816
817    // Add the current inputs onto the skid buffer, so they can be
818    // reprocessed when this stage unblocks.
819    skidInsert(tid);
820
821    // Only signal backwards to block if the previous stages do not think
822    // rename is already blocked.
823    if (renameStatus[tid] != Blocked) {
824        // If resumeUnblocking is set, we unblocked during the squash,
825        // but now we're have unblocking status. We need to tell earlier
826        // stages to block.
827        if (resumeUnblocking || renameStatus[tid] != Unblocking) {
828            toDecode->renameBlock[tid] = true;
829            toDecode->renameUnblock[tid] = false;
830            wroteToTimeBuffer = true;
831        }
832
833        // Rename can not go from SerializeStall to Blocked, otherwise
834        // it would not know to complete the serialize stall.
835        if (renameStatus[tid] != SerializeStall) {
836            // Set status to Blocked.
837            renameStatus[tid] = Blocked;
838            return true;
839        }
840    }
841
842    return false;
843}
844
845template <class Impl>
846bool
847DefaultRename<Impl>::unblock(ThreadID tid)
848{
849    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
850
851    // Rename is done unblocking if the skid buffer is empty.
852    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
853
854        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
855
856        toDecode->renameUnblock[tid] = true;
857        wroteToTimeBuffer = true;
858
859        renameStatus[tid] = Running;
860        return true;
861    }
862
863    return false;
864}
865
866template <class Impl>
867void
868DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
869{
870    typename std::list<RenameHistory>::iterator hb_it =
871        historyBuffer[tid].begin();
872
873    // After a syscall squashes everything, the history buffer may be empty
874    // but the ROB may still be squashing instructions.
875    if (historyBuffer[tid].empty()) {
876        return;
877    }
878
879    // Go through the most recent instructions, undoing the mappings
880    // they did and freeing up the registers.
881    while (!historyBuffer[tid].empty() &&
882           (*hb_it).instSeqNum > squashed_seq_num) {
883        assert(hb_it != historyBuffer[tid].end());
884
885        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
886                "number %i.\n", tid, (*hb_it).instSeqNum);
887
888        // Tell the rename map to set the architected register to the
889        // previous physical register that it was renamed to.
890        renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
891
892        // Put the renamed physical register back on the free list.
893        freeList->addReg(hb_it->newPhysReg);
894
895        // Be sure to mark its register as ready if it's a misc register.
896        if (hb_it->newPhysReg >= maxPhysicalRegs) {
897            scoreboard->setReg(hb_it->newPhysReg);
898        }
899
900        historyBuffer[tid].erase(hb_it++);
901
902        ++renameUndoneMaps;
903    }
904}
905
906template<class Impl>
907void
908DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
909{
910    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
911            "history buffer %u (size=%i), until [sn:%lli].\n",
912            tid, tid, historyBuffer[tid].size(), inst_seq_num);
913
914    typename std::list<RenameHistory>::iterator hb_it =
915        historyBuffer[tid].end();
916
917    --hb_it;
918
919    if (historyBuffer[tid].empty()) {
920        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
921        return;
922    } else if (hb_it->instSeqNum > inst_seq_num) {
923        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
924                "that a syscall happened recently.\n", tid);
925        return;
926    }
927
928    // Commit all the renames up until (and including) the committed sequence
929    // number. Some or even all of the committed instructions may not have
930    // rename histories if they did not have destination registers that were
931    // renamed.
932    while (!historyBuffer[tid].empty() &&
933           hb_it != historyBuffer[tid].end() &&
934           (*hb_it).instSeqNum <= inst_seq_num) {
935
936        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
937                "[sn:%lli].\n",
938                tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
939
940        freeList->addReg((*hb_it).prevPhysReg);
941        ++renameCommittedMaps;
942
943        historyBuffer[tid].erase(hb_it--);
944    }
945}
946
947template <class Impl>
948inline void
949DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
950{
951    assert(renameMap[tid] != 0);
952
953    unsigned num_src_regs = inst->numSrcRegs();
954
955    // Get the architectual register numbers from the source and
956    // destination operands, and redirect them to the right register.
957    // Will need to mark dependencies though.
958    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
959        RegIndex src_reg = inst->srcRegIdx(src_idx);
960        RegIndex flat_src_reg = src_reg;
961        if (src_reg < TheISA::FP_Base_DepTag) {
962            flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
963            DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
964        } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
965            src_reg = src_reg - TheISA::FP_Base_DepTag;
966            flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
967            flat_src_reg += TheISA::NumIntRegs;
968        } else {
969            flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
970            DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
971        }
972
973        inst->flattenSrcReg(src_idx, flat_src_reg);
974
975        // Look up the source registers to get the phys. register they've
976        // been renamed to, and set the sources to those registers.
977        PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
978
979        DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
980                "physical reg %i.\n", tid, (int)flat_src_reg,
981                (int)renamed_reg);
982
983        inst->renameSrcReg(src_idx, renamed_reg);
984
985        // See if the register is ready or not.
986        if (scoreboard->getReg(renamed_reg) == true) {
987            DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg);
988
989            inst->markSrcRegReady(src_idx);
990        } else {
991            DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg);
992        }
993
994        ++renameRenameLookups;
995    }
996}
997
998template <class Impl>
999inline void
1000DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1001{
1002    typename RenameMap::RenameInfo rename_result;
1003
1004    unsigned num_dest_regs = inst->numDestRegs();
1005
1006    // Rename the destination registers.
1007    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1008        RegIndex dest_reg = inst->destRegIdx(dest_idx);
1009        RegIndex flat_dest_reg = dest_reg;
1010        if (dest_reg < TheISA::FP_Base_DepTag) {
1011            // Integer registers are flattened.
1012            flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1013            DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1014        } else {
1015            // Floating point and Miscellaneous registers need their indexes
1016            // adjusted to account for the expanded number of flattened int regs.
1017            flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1018            DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
1019        }
1020
1021        inst->flattenDestReg(dest_idx, flat_dest_reg);
1022
1023        // Get the physical register that the destination will be
1024        // renamed to.
1025        rename_result = renameMap[tid]->rename(flat_dest_reg);
1026
1027        //Mark Scoreboard entry as not ready
1028        scoreboard->unsetReg(rename_result.first);
1029
1030        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1031                "reg %i.\n", tid, (int)flat_dest_reg,
1032                (int)rename_result.first);
1033
1034        // Record the rename information so that a history can be kept.
1035        RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1036                               rename_result.first,
1037                               rename_result.second);
1038
1039        historyBuffer[tid].push_front(hb_entry);
1040
1041        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1042                "(size=%i), [sn:%lli].\n",tid,
1043                historyBuffer[tid].size(),
1044                (*historyBuffer[tid].begin()).instSeqNum);
1045
1046        // Tell the instruction to rename the appropriate destination
1047        // register (dest_idx) to the new physical register
1048        // (rename_result.first), and record the previous physical
1049        // register that the same logical register was renamed to
1050        // (rename_result.second).
1051        inst->renameDestReg(dest_idx,
1052                            rename_result.first,
1053                            rename_result.second);
1054
1055        ++renameRenamedOperands;
1056    }
1057}
1058
1059template <class Impl>
1060inline int
1061DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1062{
1063    int num_free = freeEntries[tid].robEntries -
1064                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1065
1066    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1067
1068    return num_free;
1069}
1070
1071template <class Impl>
1072inline int
1073DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1074{
1075    int num_free = freeEntries[tid].iqEntries -
1076                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1077
1078    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1079
1080    return num_free;
1081}
1082
1083template <class Impl>
1084inline int
1085DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1086{
1087    int num_free = freeEntries[tid].lsqEntries -
1088                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1089
1090    //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1091
1092    return num_free;
1093}
1094
1095template <class Impl>
1096unsigned
1097DefaultRename<Impl>::validInsts()
1098{
1099    unsigned inst_count = 0;
1100
1101    for (int i=0; i<fromDecode->size; i++) {
1102        if (!fromDecode->insts[i]->isSquashed())
1103            inst_count++;
1104    }
1105
1106    return inst_count;
1107}
1108
1109template <class Impl>
1110void
1111DefaultRename<Impl>::readStallSignals(ThreadID tid)
1112{
1113    if (fromIEW->iewBlock[tid]) {
1114        stalls[tid].iew = true;
1115    }
1116
1117    if (fromIEW->iewUnblock[tid]) {
1118        assert(stalls[tid].iew);
1119        stalls[tid].iew = false;
1120    }
1121
1122    if (fromCommit->commitBlock[tid]) {
1123        stalls[tid].commit = true;
1124    }
1125
1126    if (fromCommit->commitUnblock[tid]) {
1127        assert(stalls[tid].commit);
1128        stalls[tid].commit = false;
1129    }
1130}
1131
1132template <class Impl>
1133bool
1134DefaultRename<Impl>::checkStall(ThreadID tid)
1135{
1136    bool ret_val = false;
1137
1138    if (stalls[tid].iew) {
1139        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1140        ret_val = true;
1141    } else if (stalls[tid].commit) {
1142        DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1143        ret_val = true;
1144    } else if (calcFreeROBEntries(tid) <= 0) {
1145        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1146        ret_val = true;
1147    } else if (calcFreeIQEntries(tid) <= 0) {
1148        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1149        ret_val = true;
1150    } else if (calcFreeLSQEntries(tid) <= 0) {
1151        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1152        ret_val = true;
1153    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1154        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1155        ret_val = true;
1156    } else if (renameStatus[tid] == SerializeStall &&
1157               (!emptyROB[tid] || instsInProgress[tid])) {
1158        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1159                "empty.\n",
1160                tid);
1161        ret_val = true;
1162    }
1163
1164    return ret_val;
1165}
1166
1167template <class Impl>
1168void
1169DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1170{
1171    bool updated = false;
1172    if (fromIEW->iewInfo[tid].usedIQ) {
1173        freeEntries[tid].iqEntries =
1174            fromIEW->iewInfo[tid].freeIQEntries;
1175        updated = true;
1176    }
1177
1178    if (fromIEW->iewInfo[tid].usedLSQ) {
1179        freeEntries[tid].lsqEntries =
1180            fromIEW->iewInfo[tid].freeLSQEntries;
1181        updated = true;
1182    }
1183
1184    if (fromCommit->commitInfo[tid].usedROB) {
1185        freeEntries[tid].robEntries =
1186            fromCommit->commitInfo[tid].freeROBEntries;
1187        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1188        updated = true;
1189    }
1190
1191    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1192            tid,
1193            freeEntries[tid].iqEntries,
1194            freeEntries[tid].robEntries,
1195            freeEntries[tid].lsqEntries);
1196
1197    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1198            tid, instsInProgress[tid]);
1199}
1200
1201template <class Impl>
1202bool
1203DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1204{
1205    // Check if there's a squash signal, squash if there is
1206    // Check stall signals, block if necessary.
1207    // If status was blocked
1208    //     check if stall conditions have passed
1209    //         if so then go to unblocking
1210    // If status was Squashing
1211    //     check if squashing is not high.  Switch to running this cycle.
1212    // If status was serialize stall
1213    //     check if ROB is empty and no insts are in flight to the ROB
1214
1215    readFreeEntries(tid);
1216    readStallSignals(tid);
1217
1218    if (fromCommit->commitInfo[tid].squash) {
1219        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1220                "commit.\n", tid);
1221
1222        squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1223
1224        return true;
1225    }
1226
1227    if (fromCommit->commitInfo[tid].robSquashing) {
1228        DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1229
1230        renameStatus[tid] = Squashing;
1231
1232        return true;
1233    }
1234
1235    if (checkStall(tid)) {
1236        return block(tid);
1237    }
1238
1239    if (renameStatus[tid] == Blocked) {
1240        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1241                tid);
1242
1243        renameStatus[tid] = Unblocking;
1244
1245        unblock(tid);
1246
1247        return true;
1248    }
1249
1250    if (renameStatus[tid] == Squashing) {
1251        // Switch status to running if rename isn't being told to block or
1252        // squash this cycle.
1253        if (resumeSerialize) {
1254            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1255                    tid);
1256
1257            renameStatus[tid] = SerializeStall;
1258            return true;
1259        } else if (resumeUnblocking) {
1260            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1261                    tid);
1262            renameStatus[tid] = Unblocking;
1263            return true;
1264        } else {
1265            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1266                    tid);
1267
1268            renameStatus[tid] = Running;
1269            return false;
1270        }
1271    }
1272
1273    if (renameStatus[tid] == SerializeStall) {
1274        // Stall ends once the ROB is free.
1275        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1276                "unblocking.\n", tid);
1277
1278        DynInstPtr serial_inst = serializeInst[tid];
1279
1280        renameStatus[tid] = Unblocking;
1281
1282        unblock(tid);
1283
1284        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1285                "PC %#x.\n",
1286                tid, serial_inst->seqNum, serial_inst->readPC());
1287
1288        // Put instruction into queue here.
1289        serial_inst->clearSerializeBefore();
1290
1291        if (!skidBuffer[tid].empty()) {
1292            skidBuffer[tid].push_front(serial_inst);
1293        } else {
1294            insts[tid].push_front(serial_inst);
1295        }
1296
1297        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1298                " Adding to front of list.\n", tid);
1299
1300        serializeInst[tid] = NULL;
1301
1302        return true;
1303    }
1304
1305    // If we've reached this point, we have not gotten any signals that
1306    // cause rename to change its status.  Rename remains the same as before.
1307    return false;
1308}
1309
1310template<class Impl>
1311void
1312DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1313{
1314    if (inst_list.empty()) {
1315        // Mark a bit to say that I must serialize on the next instruction.
1316        serializeOnNextInst[tid] = true;
1317        return;
1318    }
1319
1320    // Set the next instruction as serializing.
1321    inst_list.front()->setSerializeBefore();
1322}
1323
1324template <class Impl>
1325inline void
1326DefaultRename<Impl>::incrFullStat(const FullSource &source)
1327{
1328    switch (source) {
1329      case ROB:
1330        ++renameROBFullEvents;
1331        break;
1332      case IQ:
1333        ++renameIQFullEvents;
1334        break;
1335      case LSQ:
1336        ++renameLSQFullEvents;
1337        break;
1338      default:
1339        panic("Rename full stall stat should be incremented for a reason!");
1340        break;
1341    }
1342}
1343
1344template <class Impl>
1345void
1346DefaultRename<Impl>::dumpHistory()
1347{
1348    typename std::list<RenameHistory>::iterator buf_it;
1349
1350    for (ThreadID tid = 0; tid < numThreads; tid++) {
1351
1352        buf_it = historyBuffer[tid].begin();
1353
1354        while (buf_it != historyBuffer[tid].end()) {
1355            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1356                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1357                    (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1358
1359            buf_it++;
1360        }
1361    }
1362}
1363