rename_impl.hh revision 4632
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <list> 33 34#include "arch/isa_traits.hh" 35#include "arch/regfile.hh" 36#include "config/full_system.hh" 37#include "cpu/o3/rename.hh" 38 39template <class Impl> 40DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params) 41 : cpu(_cpu), 42 iewToRenameDelay(params->iewToRenameDelay), 43 decodeToRenameDelay(params->decodeToRenameDelay), 44 commitToRenameDelay(params->commitToRenameDelay), 45 renameWidth(params->renameWidth), 46 commitWidth(params->commitWidth), 47 resumeSerialize(false), 48 resumeUnblocking(false), 49 numThreads(params->numberOfThreads), 50 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 51{ 52 _status = Inactive; 53 54 for (int i=0; i< numThreads; i++) { 55 renameStatus[i] = Idle; 56 57 freeEntries[i].iqEntries = 0; 58 freeEntries[i].lsqEntries = 0; 59 freeEntries[i].robEntries = 0; 60 61 stalls[i].iew = false; 62 stalls[i].commit = false; 63 serializeInst[i] = NULL; 64 65 instsInProgress[i] = 0; 66 67 emptyROB[i] = true; 68 69 serializeOnNextInst[i] = false; 70 } 71 72 // @todo: Make into a parameter. 73 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 74} 75 76template <class Impl> 77std::string 78DefaultRename<Impl>::name() const 79{ 80 return cpu->name() + ".rename"; 81} 82 83template <class Impl> 84void 85DefaultRename<Impl>::regStats() 86{ 87 renameSquashCycles 88 .name(name() + ".RENAME:SquashCycles") 89 .desc("Number of cycles rename is squashing") 90 .prereq(renameSquashCycles); 91 renameIdleCycles 92 .name(name() + ".RENAME:IdleCycles") 93 .desc("Number of cycles rename is idle") 94 .prereq(renameIdleCycles); 95 renameBlockCycles 96 .name(name() + ".RENAME:BlockCycles") 97 .desc("Number of cycles rename is blocking") 98 .prereq(renameBlockCycles); 99 renameSerializeStallCycles 100 .name(name() + ".RENAME:serializeStallCycles") 101 .desc("count of cycles rename stalled for serializing inst") 102 .flags(Stats::total); 103 renameRunCycles 104 .name(name() + ".RENAME:RunCycles") 105 .desc("Number of cycles rename is running") 106 .prereq(renameIdleCycles); 107 renameUnblockCycles 108 .name(name() + ".RENAME:UnblockCycles") 109 .desc("Number of cycles rename is unblocking") 110 .prereq(renameUnblockCycles); 111 renameRenamedInsts 112 .name(name() + ".RENAME:RenamedInsts") 113 .desc("Number of instructions processed by rename") 114 .prereq(renameRenamedInsts); 115 renameSquashedInsts 116 .name(name() + ".RENAME:SquashedInsts") 117 .desc("Number of squashed instructions processed by rename") 118 .prereq(renameSquashedInsts); 119 renameROBFullEvents 120 .name(name() + ".RENAME:ROBFullEvents") 121 .desc("Number of times rename has blocked due to ROB full") 122 .prereq(renameROBFullEvents); 123 renameIQFullEvents 124 .name(name() + ".RENAME:IQFullEvents") 125 .desc("Number of times rename has blocked due to IQ full") 126 .prereq(renameIQFullEvents); 127 renameLSQFullEvents 128 .name(name() + ".RENAME:LSQFullEvents") 129 .desc("Number of times rename has blocked due to LSQ full") 130 .prereq(renameLSQFullEvents); 131 renameFullRegistersEvents 132 .name(name() + ".RENAME:FullRegisterEvents") 133 .desc("Number of times there has been no free registers") 134 .prereq(renameFullRegistersEvents); 135 renameRenamedOperands 136 .name(name() + ".RENAME:RenamedOperands") 137 .desc("Number of destination operands rename has renamed") 138 .prereq(renameRenamedOperands); 139 renameRenameLookups 140 .name(name() + ".RENAME:RenameLookups") 141 .desc("Number of register rename lookups that rename has made") 142 .prereq(renameRenameLookups); 143 renameCommittedMaps 144 .name(name() + ".RENAME:CommittedMaps") 145 .desc("Number of HB maps that are committed") 146 .prereq(renameCommittedMaps); 147 renameUndoneMaps 148 .name(name() + ".RENAME:UndoneMaps") 149 .desc("Number of HB maps that are undone due to squashing") 150 .prereq(renameUndoneMaps); 151 renamedSerializing 152 .name(name() + ".RENAME:serializingInsts") 153 .desc("count of serializing insts renamed") 154 .flags(Stats::total) 155 ; 156 renamedTempSerializing 157 .name(name() + ".RENAME:tempSerializingInsts") 158 .desc("count of temporary serializing insts renamed") 159 .flags(Stats::total) 160 ; 161 renameSkidInsts 162 .name(name() + ".RENAME:skidInsts") 163 .desc("count of insts added to the skid buffer") 164 .flags(Stats::total) 165 ; 166} 167 168template <class Impl> 169void 170DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 171{ 172 timeBuffer = tb_ptr; 173 174 // Setup wire to read information from time buffer, from IEW stage. 175 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 176 177 // Setup wire to read infromation from time buffer, from commit stage. 178 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 179 180 // Setup wire to write information to previous stages. 181 toDecode = timeBuffer->getWire(0); 182} 183 184template <class Impl> 185void 186DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 187{ 188 renameQueue = rq_ptr; 189 190 // Setup wire to write information to future stages. 191 toIEW = renameQueue->getWire(0); 192} 193 194template <class Impl> 195void 196DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 197{ 198 decodeQueue = dq_ptr; 199 200 // Setup wire to get information from decode. 201 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 202} 203 204template <class Impl> 205void 206DefaultRename<Impl>::initStage() 207{ 208 // Grab the number of free entries directly from the stages. 209 for (int tid=0; tid < numThreads; tid++) { 210 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 211 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 212 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 213 emptyROB[tid] = true; 214 } 215} 216 217template<class Impl> 218void 219DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 220{ 221 activeThreads = at_ptr; 222} 223 224 225template <class Impl> 226void 227DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 228{ 229 for (int i=0; i<numThreads; i++) { 230 renameMap[i] = &rm_ptr[i]; 231 } 232} 233 234template <class Impl> 235void 236DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 237{ 238 freeList = fl_ptr; 239} 240 241template<class Impl> 242void 243DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 244{ 245 scoreboard = _scoreboard; 246} 247 248template <class Impl> 249bool 250DefaultRename<Impl>::drain() 251{ 252 // Rename is ready to switch out at any time. 253 cpu->signalDrained(); 254 return true; 255} 256 257template <class Impl> 258void 259DefaultRename<Impl>::switchOut() 260{ 261 // Clear any state, fix up the rename map. 262 for (int i = 0; i < numThreads; i++) { 263 typename std::list<RenameHistory>::iterator hb_it = 264 historyBuffer[i].begin(); 265 266 while (!historyBuffer[i].empty()) { 267 assert(hb_it != historyBuffer[i].end()); 268 269 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 270 "number %i.\n", i, (*hb_it).instSeqNum); 271 272 // Tell the rename map to set the architected register to the 273 // previous physical register that it was renamed to. 274 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 275 276 // Put the renamed physical register back on the free list. 277 freeList->addReg(hb_it->newPhysReg); 278 279 // Be sure to mark its register as ready if it's a misc register. 280 if (hb_it->newPhysReg >= maxPhysicalRegs) { 281 scoreboard->setReg(hb_it->newPhysReg); 282 } 283 284 historyBuffer[i].erase(hb_it++); 285 } 286 insts[i].clear(); 287 skidBuffer[i].clear(); 288 } 289} 290 291template <class Impl> 292void 293DefaultRename<Impl>::takeOverFrom() 294{ 295 _status = Inactive; 296 initStage(); 297 298 // Reset all state prior to taking over from the other CPU. 299 for (int i=0; i< numThreads; i++) { 300 renameStatus[i] = Idle; 301 302 stalls[i].iew = false; 303 stalls[i].commit = false; 304 serializeInst[i] = NULL; 305 306 instsInProgress[i] = 0; 307 308 emptyROB[i] = true; 309 310 serializeOnNextInst[i] = false; 311 } 312} 313 314template <class Impl> 315void 316DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 317{ 318 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 319 320 // Clear the stall signal if rename was blocked or unblocking before. 321 // If it still needs to block, the blocking should happen the next 322 // cycle and there should be space to hold everything due to the squash. 323 if (renameStatus[tid] == Blocked || 324 renameStatus[tid] == Unblocking) { 325 toDecode->renameUnblock[tid] = 1; 326 327 resumeSerialize = false; 328 serializeInst[tid] = NULL; 329 } else if (renameStatus[tid] == SerializeStall) { 330 if (serializeInst[tid]->seqNum <= squash_seq_num) { 331 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 332 resumeSerialize = true; 333 assert(serializeInst[tid]); 334 } else { 335 resumeSerialize = false; 336 toDecode->renameUnblock[tid] = 1; 337 338 serializeInst[tid] = NULL; 339 } 340 } 341 342 // Set the status to Squashing. 343 renameStatus[tid] = Squashing; 344 345 // Squash any instructions from decode. 346 unsigned squashCount = 0; 347 348 for (int i=0; i<fromDecode->size; i++) { 349 if (fromDecode->insts[i]->threadNumber == tid && 350 fromDecode->insts[i]->seqNum > squash_seq_num) { 351 fromDecode->insts[i]->setSquashed(); 352 wroteToTimeBuffer = true; 353 squashCount++; 354 } 355 356 } 357 358 // Clear the instruction list and skid buffer in case they have any 359 // insts in them. 360 insts[tid].clear(); 361 362 // Clear the skid buffer in case it has any data in it. 363 skidBuffer[tid].clear(); 364 365 doSquash(squash_seq_num, tid); 366} 367 368template <class Impl> 369void 370DefaultRename<Impl>::tick() 371{ 372 wroteToTimeBuffer = false; 373 374 blockThisCycle = false; 375 376 bool status_change = false; 377 378 toIEWIndex = 0; 379 380 sortInsts(); 381 382 std::list<unsigned>::iterator threads = activeThreads->begin(); 383 std::list<unsigned>::iterator end = activeThreads->end(); 384 385 // Check stall and squash signals. 386 while (threads != end) { 387 unsigned tid = *threads++; 388 389 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 390 391 status_change = checkSignalsAndUpdate(tid) || status_change; 392 393 rename(status_change, tid); 394 } 395 396 if (status_change) { 397 updateStatus(); 398 } 399 400 if (wroteToTimeBuffer) { 401 DPRINTF(Activity, "Activity this cycle.\n"); 402 cpu->activityThisCycle(); 403 } 404 405 threads = activeThreads->begin(); 406 407 while (threads != end) { 408 unsigned tid = *threads++; 409 410 // If we committed this cycle then doneSeqNum will be > 0 411 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 412 !fromCommit->commitInfo[tid].squash && 413 renameStatus[tid] != Squashing) { 414 415 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 416 tid); 417 } 418 } 419 420 // @todo: make into updateProgress function 421 for (int tid=0; tid < numThreads; tid++) { 422 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 423 424 assert(instsInProgress[tid] >=0); 425 } 426 427} 428 429template<class Impl> 430void 431DefaultRename<Impl>::rename(bool &status_change, unsigned tid) 432{ 433 // If status is Running or idle, 434 // call renameInsts() 435 // If status is Unblocking, 436 // buffer any instructions coming from decode 437 // continue trying to empty skid buffer 438 // check if stall conditions have passed 439 440 if (renameStatus[tid] == Blocked) { 441 ++renameBlockCycles; 442 } else if (renameStatus[tid] == Squashing) { 443 ++renameSquashCycles; 444 } else if (renameStatus[tid] == SerializeStall) { 445 ++renameSerializeStallCycles; 446 // If we are currently in SerializeStall and resumeSerialize 447 // was set, then that means that we are resuming serializing 448 // this cycle. Tell the previous stages to block. 449 if (resumeSerialize) { 450 resumeSerialize = false; 451 block(tid); 452 toDecode->renameUnblock[tid] = false; 453 } 454 } else if (renameStatus[tid] == Unblocking) { 455 if (resumeUnblocking) { 456 block(tid); 457 resumeUnblocking = false; 458 toDecode->renameUnblock[tid] = false; 459 } 460 } 461 462 if (renameStatus[tid] == Running || 463 renameStatus[tid] == Idle) { 464 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 465 "stage.\n", tid); 466 467 renameInsts(tid); 468 } else if (renameStatus[tid] == Unblocking) { 469 renameInsts(tid); 470 471 if (validInsts()) { 472 // Add the current inputs to the skid buffer so they can be 473 // reprocessed when this stage unblocks. 474 skidInsert(tid); 475 } 476 477 // If we switched over to blocking, then there's a potential for 478 // an overall status change. 479 status_change = unblock(tid) || status_change || blockThisCycle; 480 } 481} 482 483template <class Impl> 484void 485DefaultRename<Impl>::renameInsts(unsigned tid) 486{ 487 // Instructions can be either in the skid buffer or the queue of 488 // instructions coming from decode, depending on the status. 489 int insts_available = renameStatus[tid] == Unblocking ? 490 skidBuffer[tid].size() : insts[tid].size(); 491 492 // Check the decode queue to see if instructions are available. 493 // If there are no available instructions to rename, then do nothing. 494 if (insts_available == 0) { 495 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 496 tid); 497 // Should I change status to idle? 498 ++renameIdleCycles; 499 return; 500 } else if (renameStatus[tid] == Unblocking) { 501 ++renameUnblockCycles; 502 } else if (renameStatus[tid] == Running) { 503 ++renameRunCycles; 504 } 505 506 DynInstPtr inst; 507 508 // Will have to do a different calculation for the number of free 509 // entries. 510 int free_rob_entries = calcFreeROBEntries(tid); 511 int free_iq_entries = calcFreeIQEntries(tid); 512 int free_lsq_entries = calcFreeLSQEntries(tid); 513 int min_free_entries = free_rob_entries; 514 515 FullSource source = ROB; 516 517 if (free_iq_entries < min_free_entries) { 518 min_free_entries = free_iq_entries; 519 source = IQ; 520 } 521 522 if (free_lsq_entries < min_free_entries) { 523 min_free_entries = free_lsq_entries; 524 source = LSQ; 525 } 526 527 // Check if there's any space left. 528 if (min_free_entries <= 0) { 529 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 530 "entries.\n" 531 "ROB has %i free entries.\n" 532 "IQ has %i free entries.\n" 533 "LSQ has %i free entries.\n", 534 tid, 535 free_rob_entries, 536 free_iq_entries, 537 free_lsq_entries); 538 539 blockThisCycle = true; 540 541 block(tid); 542 543 incrFullStat(source); 544 545 return; 546 } else if (min_free_entries < insts_available) { 547 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 548 "%i insts available, but only %i insts can be " 549 "renamed due to ROB/IQ/LSQ limits.\n", 550 tid, insts_available, min_free_entries); 551 552 insts_available = min_free_entries; 553 554 blockThisCycle = true; 555 556 incrFullStat(source); 557 } 558 559 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 560 skidBuffer[tid] : insts[tid]; 561 562 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 563 "send iew.\n", tid, insts_available); 564 565 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 566 "dispatched to IQ last cycle.\n", 567 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 568 569 // Handle serializing the next instruction if necessary. 570 if (serializeOnNextInst[tid]) { 571 if (emptyROB[tid] && instsInProgress[tid] == 0) { 572 // ROB already empty; no need to serialize. 573 serializeOnNextInst[tid] = false; 574 } else if (!insts_to_rename.empty()) { 575 insts_to_rename.front()->setSerializeBefore(); 576 } 577 } 578 579 int renamed_insts = 0; 580 581 while (insts_available > 0 && toIEWIndex < renameWidth) { 582 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 583 584 assert(!insts_to_rename.empty()); 585 586 inst = insts_to_rename.front(); 587 588 insts_to_rename.pop_front(); 589 590 if (renameStatus[tid] == Unblocking) { 591 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 592 "skidBuffer\n", 593 tid, inst->seqNum, inst->readPC()); 594 } 595 596 if (inst->isSquashed()) { 597 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 598 "squashed, skipping.\n", 599 tid, inst->seqNum, inst->readPC()); 600 601 ++renameSquashedInsts; 602 603 // Decrement how many instructions are available. 604 --insts_available; 605 606 continue; 607 } 608 609 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 610 "PC %#x.\n", 611 tid, inst->seqNum, inst->readPC()); 612 613 // Handle serializeAfter/serializeBefore instructions. 614 // serializeAfter marks the next instruction as serializeBefore. 615 // serializeBefore makes the instruction wait in rename until the ROB 616 // is empty. 617 618 // In this model, IPR accesses are serialize before 619 // instructions, and store conditionals are serialize after 620 // instructions. This is mainly due to lack of support for 621 // out-of-order operations of either of those classes of 622 // instructions. 623 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 624 !inst->isSerializeHandled()) { 625 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 626 627 if (!inst->isTempSerializeBefore()) { 628 renamedSerializing++; 629 inst->setSerializeHandled(); 630 } else { 631 renamedTempSerializing++; 632 } 633 634 // Change status over to SerializeStall so that other stages know 635 // what this is blocked on. 636 renameStatus[tid] = SerializeStall; 637 638 serializeInst[tid] = inst; 639 640 blockThisCycle = true; 641 642 break; 643 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 644 !inst->isSerializeHandled()) { 645 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 646 647 renamedSerializing++; 648 649 inst->setSerializeHandled(); 650 651 serializeAfter(insts_to_rename, tid); 652 } 653 654 // Check here to make sure there are enough destination registers 655 // to rename to. Otherwise block. 656 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 657 DPRINTF(Rename, "Blocking due to lack of free " 658 "physical registers to rename to.\n"); 659 blockThisCycle = true; 660 insts_to_rename.push_front(inst); 661 ++renameFullRegistersEvents; 662 663 break; 664 } 665 666 renameSrcRegs(inst, inst->threadNumber); 667 668 renameDestRegs(inst, inst->threadNumber); 669 670 ++renamed_insts; 671 672 // Put instruction in rename queue. 673 toIEW->insts[toIEWIndex] = inst; 674 ++(toIEW->size); 675 676 // Increment which instruction we're on. 677 ++toIEWIndex; 678 679 // Decrement how many instructions are available. 680 --insts_available; 681 } 682 683 instsInProgress[tid] += renamed_insts; 684 renameRenamedInsts += renamed_insts; 685 686 // If we wrote to the time buffer, record this. 687 if (toIEWIndex) { 688 wroteToTimeBuffer = true; 689 } 690 691 // Check if there's any instructions left that haven't yet been renamed. 692 // If so then block. 693 if (insts_available) { 694 blockThisCycle = true; 695 } 696 697 if (blockThisCycle) { 698 block(tid); 699 toDecode->renameUnblock[tid] = false; 700 } 701} 702 703template<class Impl> 704void 705DefaultRename<Impl>::skidInsert(unsigned tid) 706{ 707 DynInstPtr inst = NULL; 708 709 while (!insts[tid].empty()) { 710 inst = insts[tid].front(); 711 712 insts[tid].pop_front(); 713 714 assert(tid == inst->threadNumber); 715 716 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 717 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 718 719 ++renameSkidInsts; 720 721 skidBuffer[tid].push_back(inst); 722 } 723 724 if (skidBuffer[tid].size() > skidBufferMax) 725 { 726 typename InstQueue::iterator it; 727 warn("Skidbuffer contents:\n"); 728 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 729 { 730 warn("[tid:%u]: %s [sn:%i].\n", tid, 731 (*it)->staticInst->disassemble(inst->readPC()), 732 (*it)->seqNum); 733 } 734 panic("Skidbuffer Exceeded Max Size"); 735 } 736} 737 738template <class Impl> 739void 740DefaultRename<Impl>::sortInsts() 741{ 742 int insts_from_decode = fromDecode->size; 743#ifdef DEBUG 744 for (int i=0; i < numThreads; i++) 745 assert(insts[i].empty()); 746#endif 747 for (int i = 0; i < insts_from_decode; ++i) { 748 DynInstPtr inst = fromDecode->insts[i]; 749 insts[inst->threadNumber].push_back(inst); 750 } 751} 752 753template<class Impl> 754bool 755DefaultRename<Impl>::skidsEmpty() 756{ 757 std::list<unsigned>::iterator threads = activeThreads->begin(); 758 std::list<unsigned>::iterator end = activeThreads->end(); 759 760 while (threads != end) { 761 unsigned tid = *threads++; 762 763 if (!skidBuffer[tid].empty()) 764 return false; 765 } 766 767 return true; 768} 769 770template<class Impl> 771void 772DefaultRename<Impl>::updateStatus() 773{ 774 bool any_unblocking = false; 775 776 std::list<unsigned>::iterator threads = activeThreads->begin(); 777 std::list<unsigned>::iterator end = activeThreads->end(); 778 779 while (threads != end) { 780 unsigned tid = *threads++; 781 782 if (renameStatus[tid] == Unblocking) { 783 any_unblocking = true; 784 break; 785 } 786 } 787 788 // Rename will have activity if it's unblocking. 789 if (any_unblocking) { 790 if (_status == Inactive) { 791 _status = Active; 792 793 DPRINTF(Activity, "Activating stage.\n"); 794 795 cpu->activateStage(O3CPU::RenameIdx); 796 } 797 } else { 798 // If it's not unblocking, then rename will not have any internal 799 // activity. Switch it to inactive. 800 if (_status == Active) { 801 _status = Inactive; 802 DPRINTF(Activity, "Deactivating stage.\n"); 803 804 cpu->deactivateStage(O3CPU::RenameIdx); 805 } 806 } 807} 808 809template <class Impl> 810bool 811DefaultRename<Impl>::block(unsigned tid) 812{ 813 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 814 815 // Add the current inputs onto the skid buffer, so they can be 816 // reprocessed when this stage unblocks. 817 skidInsert(tid); 818 819 // Only signal backwards to block if the previous stages do not think 820 // rename is already blocked. 821 if (renameStatus[tid] != Blocked) { 822 // If resumeUnblocking is set, we unblocked during the squash, 823 // but now we're have unblocking status. We need to tell earlier 824 // stages to block. 825 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 826 toDecode->renameBlock[tid] = true; 827 toDecode->renameUnblock[tid] = false; 828 wroteToTimeBuffer = true; 829 } 830 831 // Rename can not go from SerializeStall to Blocked, otherwise 832 // it would not know to complete the serialize stall. 833 if (renameStatus[tid] != SerializeStall) { 834 // Set status to Blocked. 835 renameStatus[tid] = Blocked; 836 return true; 837 } 838 } 839 840 return false; 841} 842 843template <class Impl> 844bool 845DefaultRename<Impl>::unblock(unsigned tid) 846{ 847 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 848 849 // Rename is done unblocking if the skid buffer is empty. 850 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 851 852 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 853 854 toDecode->renameUnblock[tid] = true; 855 wroteToTimeBuffer = true; 856 857 renameStatus[tid] = Running; 858 return true; 859 } 860 861 return false; 862} 863 864template <class Impl> 865void 866DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 867{ 868 typename std::list<RenameHistory>::iterator hb_it = 869 historyBuffer[tid].begin(); 870 871 // After a syscall squashes everything, the history buffer may be empty 872 // but the ROB may still be squashing instructions. 873 if (historyBuffer[tid].empty()) { 874 return; 875 } 876 877 // Go through the most recent instructions, undoing the mappings 878 // they did and freeing up the registers. 879 while (!historyBuffer[tid].empty() && 880 (*hb_it).instSeqNum > squashed_seq_num) { 881 assert(hb_it != historyBuffer[tid].end()); 882 883 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 884 "number %i.\n", tid, (*hb_it).instSeqNum); 885 886 // Tell the rename map to set the architected register to the 887 // previous physical register that it was renamed to. 888 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 889 890 // Put the renamed physical register back on the free list. 891 freeList->addReg(hb_it->newPhysReg); 892 893 // Be sure to mark its register as ready if it's a misc register. 894 if (hb_it->newPhysReg >= maxPhysicalRegs) { 895 scoreboard->setReg(hb_it->newPhysReg); 896 } 897 898 historyBuffer[tid].erase(hb_it++); 899 900 ++renameUndoneMaps; 901 } 902} 903 904template<class Impl> 905void 906DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 907{ 908 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 909 "history buffer %u (size=%i), until [sn:%lli].\n", 910 tid, tid, historyBuffer[tid].size(), inst_seq_num); 911 912 typename std::list<RenameHistory>::iterator hb_it = 913 historyBuffer[tid].end(); 914 915 --hb_it; 916 917 if (historyBuffer[tid].empty()) { 918 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 919 return; 920 } else if (hb_it->instSeqNum > inst_seq_num) { 921 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 922 "that a syscall happened recently.\n", tid); 923 return; 924 } 925 926 // Commit all the renames up until (and including) the committed sequence 927 // number. Some or even all of the committed instructions may not have 928 // rename histories if they did not have destination registers that were 929 // renamed. 930 while (!historyBuffer[tid].empty() && 931 hb_it != historyBuffer[tid].end() && 932 (*hb_it).instSeqNum <= inst_seq_num) { 933 934 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 935 "[sn:%lli].\n", 936 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 937 938 freeList->addReg((*hb_it).prevPhysReg); 939 ++renameCommittedMaps; 940 941 historyBuffer[tid].erase(hb_it--); 942 } 943} 944 945template <class Impl> 946inline void 947DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 948{ 949 assert(renameMap[tid] != 0); 950 951 unsigned num_src_regs = inst->numSrcRegs(); 952 953 // Get the architectual register numbers from the source and 954 // destination operands, and redirect them to the right register. 955 // Will need to mark dependencies though. 956 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 957 RegIndex src_reg = inst->srcRegIdx(src_idx); 958 RegIndex flat_src_reg = src_reg; 959 if (src_reg < TheISA::FP_Base_DepTag) { 960 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 961 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 962 } else { 963 // Floating point and Miscellaneous registers need their indexes 964 // adjusted to account for the expanded number of flattened int regs. 965 flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 966 } 967 968 inst->flattenSrcReg(src_idx, flat_src_reg); 969 970 // Look up the source registers to get the phys. register they've 971 // been renamed to, and set the sources to those registers. 972 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 973 974 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 975 "physical reg %i.\n", tid, (int)flat_src_reg, 976 (int)renamed_reg); 977 978 inst->renameSrcReg(src_idx, renamed_reg); 979 980 // See if the register is ready or not. 981 if (scoreboard->getReg(renamed_reg) == true) { 982 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 983 984 inst->markSrcRegReady(src_idx); 985 } 986 987 ++renameRenameLookups; 988 } 989} 990 991template <class Impl> 992inline void 993DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 994{ 995 typename RenameMap::RenameInfo rename_result; 996 997 unsigned num_dest_regs = inst->numDestRegs(); 998 999 // Rename the destination registers. 1000 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1001 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1002 RegIndex flat_dest_reg = dest_reg; 1003 if (dest_reg < TheISA::FP_Base_DepTag) { 1004 // Integer registers are flattened. 1005 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 1006 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 1007 } else { 1008 // Floating point and Miscellaneous registers need their indexes 1009 // adjusted to account for the expanded number of flattened int regs. 1010 flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 1011 } 1012 1013 inst->flattenDestReg(dest_idx, flat_dest_reg); 1014 1015 // Get the physical register that the destination will be 1016 // renamed to. 1017 rename_result = renameMap[tid]->rename(flat_dest_reg); 1018 1019 //Mark Scoreboard entry as not ready 1020 scoreboard->unsetReg(rename_result.first); 1021 1022 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1023 "reg %i.\n", tid, (int)flat_dest_reg, 1024 (int)rename_result.first); 1025 1026 // Record the rename information so that a history can be kept. 1027 RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 1028 rename_result.first, 1029 rename_result.second); 1030 1031 historyBuffer[tid].push_front(hb_entry); 1032 1033 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1034 "(size=%i), [sn:%lli].\n",tid, 1035 historyBuffer[tid].size(), 1036 (*historyBuffer[tid].begin()).instSeqNum); 1037 1038 // Tell the instruction to rename the appropriate destination 1039 // register (dest_idx) to the new physical register 1040 // (rename_result.first), and record the previous physical 1041 // register that the same logical register was renamed to 1042 // (rename_result.second). 1043 inst->renameDestReg(dest_idx, 1044 rename_result.first, 1045 rename_result.second); 1046 1047 ++renameRenamedOperands; 1048 } 1049} 1050 1051template <class Impl> 1052inline int 1053DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 1054{ 1055 int num_free = freeEntries[tid].robEntries - 1056 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1057 1058 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1059 1060 return num_free; 1061} 1062 1063template <class Impl> 1064inline int 1065DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 1066{ 1067 int num_free = freeEntries[tid].iqEntries - 1068 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1069 1070 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1071 1072 return num_free; 1073} 1074 1075template <class Impl> 1076inline int 1077DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1078{ 1079 int num_free = freeEntries[tid].lsqEntries - 1080 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1081 1082 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1083 1084 return num_free; 1085} 1086 1087template <class Impl> 1088unsigned 1089DefaultRename<Impl>::validInsts() 1090{ 1091 unsigned inst_count = 0; 1092 1093 for (int i=0; i<fromDecode->size; i++) { 1094 if (!fromDecode->insts[i]->isSquashed()) 1095 inst_count++; 1096 } 1097 1098 return inst_count; 1099} 1100 1101template <class Impl> 1102void 1103DefaultRename<Impl>::readStallSignals(unsigned tid) 1104{ 1105 if (fromIEW->iewBlock[tid]) { 1106 stalls[tid].iew = true; 1107 } 1108 1109 if (fromIEW->iewUnblock[tid]) { 1110 assert(stalls[tid].iew); 1111 stalls[tid].iew = false; 1112 } 1113 1114 if (fromCommit->commitBlock[tid]) { 1115 stalls[tid].commit = true; 1116 } 1117 1118 if (fromCommit->commitUnblock[tid]) { 1119 assert(stalls[tid].commit); 1120 stalls[tid].commit = false; 1121 } 1122} 1123 1124template <class Impl> 1125bool 1126DefaultRename<Impl>::checkStall(unsigned tid) 1127{ 1128 bool ret_val = false; 1129 1130 if (stalls[tid].iew) { 1131 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1132 ret_val = true; 1133 } else if (stalls[tid].commit) { 1134 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1135 ret_val = true; 1136 } else if (calcFreeROBEntries(tid) <= 0) { 1137 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1138 ret_val = true; 1139 } else if (calcFreeIQEntries(tid) <= 0) { 1140 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1141 ret_val = true; 1142 } else if (calcFreeLSQEntries(tid) <= 0) { 1143 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1144 ret_val = true; 1145 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1146 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1147 ret_val = true; 1148 } else if (renameStatus[tid] == SerializeStall && 1149 (!emptyROB[tid] || instsInProgress[tid])) { 1150 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1151 "empty.\n", 1152 tid); 1153 ret_val = true; 1154 } 1155 1156 return ret_val; 1157} 1158 1159template <class Impl> 1160void 1161DefaultRename<Impl>::readFreeEntries(unsigned tid) 1162{ 1163 bool updated = false; 1164 if (fromIEW->iewInfo[tid].usedIQ) { 1165 freeEntries[tid].iqEntries = 1166 fromIEW->iewInfo[tid].freeIQEntries; 1167 updated = true; 1168 } 1169 1170 if (fromIEW->iewInfo[tid].usedLSQ) { 1171 freeEntries[tid].lsqEntries = 1172 fromIEW->iewInfo[tid].freeLSQEntries; 1173 updated = true; 1174 } 1175 1176 if (fromCommit->commitInfo[tid].usedROB) { 1177 freeEntries[tid].robEntries = 1178 fromCommit->commitInfo[tid].freeROBEntries; 1179 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1180 updated = true; 1181 } 1182 1183 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1184 tid, 1185 freeEntries[tid].iqEntries, 1186 freeEntries[tid].robEntries, 1187 freeEntries[tid].lsqEntries); 1188 1189 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1190 tid, instsInProgress[tid]); 1191} 1192 1193template <class Impl> 1194bool 1195DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1196{ 1197 // Check if there's a squash signal, squash if there is 1198 // Check stall signals, block if necessary. 1199 // If status was blocked 1200 // check if stall conditions have passed 1201 // if so then go to unblocking 1202 // If status was Squashing 1203 // check if squashing is not high. Switch to running this cycle. 1204 // If status was serialize stall 1205 // check if ROB is empty and no insts are in flight to the ROB 1206 1207 readFreeEntries(tid); 1208 readStallSignals(tid); 1209 1210 if (fromCommit->commitInfo[tid].squash) { 1211 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1212 "commit.\n", tid); 1213 1214 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1215 1216 return true; 1217 } 1218 1219 if (fromCommit->commitInfo[tid].robSquashing) { 1220 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1221 1222 renameStatus[tid] = Squashing; 1223 1224 return true; 1225 } 1226 1227 if (checkStall(tid)) { 1228 return block(tid); 1229 } 1230 1231 if (renameStatus[tid] == Blocked) { 1232 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1233 tid); 1234 1235 renameStatus[tid] = Unblocking; 1236 1237 unblock(tid); 1238 1239 return true; 1240 } 1241 1242 if (renameStatus[tid] == Squashing) { 1243 // Switch status to running if rename isn't being told to block or 1244 // squash this cycle. 1245 if (resumeSerialize) { 1246 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1247 tid); 1248 1249 renameStatus[tid] = SerializeStall; 1250 return true; 1251 } else if (resumeUnblocking) { 1252 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1253 tid); 1254 renameStatus[tid] = Unblocking; 1255 return true; 1256 } else { 1257 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1258 tid); 1259 1260 renameStatus[tid] = Running; 1261 return false; 1262 } 1263 } 1264 1265 if (renameStatus[tid] == SerializeStall) { 1266 // Stall ends once the ROB is free. 1267 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1268 "unblocking.\n", tid); 1269 1270 DynInstPtr serial_inst = serializeInst[tid]; 1271 1272 renameStatus[tid] = Unblocking; 1273 1274 unblock(tid); 1275 1276 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1277 "PC %#x.\n", 1278 tid, serial_inst->seqNum, serial_inst->readPC()); 1279 1280 // Put instruction into queue here. 1281 serial_inst->clearSerializeBefore(); 1282 1283 if (!skidBuffer[tid].empty()) { 1284 skidBuffer[tid].push_front(serial_inst); 1285 } else { 1286 insts[tid].push_front(serial_inst); 1287 } 1288 1289 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1290 " Adding to front of list.\n", tid); 1291 1292 serializeInst[tid] = NULL; 1293 1294 return true; 1295 } 1296 1297 // If we've reached this point, we have not gotten any signals that 1298 // cause rename to change its status. Rename remains the same as before. 1299 return false; 1300} 1301 1302template<class Impl> 1303void 1304DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1305 unsigned tid) 1306{ 1307 if (inst_list.empty()) { 1308 // Mark a bit to say that I must serialize on the next instruction. 1309 serializeOnNextInst[tid] = true; 1310 return; 1311 } 1312 1313 // Set the next instruction as serializing. 1314 inst_list.front()->setSerializeBefore(); 1315} 1316 1317template <class Impl> 1318inline void 1319DefaultRename<Impl>::incrFullStat(const FullSource &source) 1320{ 1321 switch (source) { 1322 case ROB: 1323 ++renameROBFullEvents; 1324 break; 1325 case IQ: 1326 ++renameIQFullEvents; 1327 break; 1328 case LSQ: 1329 ++renameLSQFullEvents; 1330 break; 1331 default: 1332 panic("Rename full stall stat should be incremented for a reason!"); 1333 break; 1334 } 1335} 1336 1337template <class Impl> 1338void 1339DefaultRename<Impl>::dumpHistory() 1340{ 1341 typename std::list<RenameHistory>::iterator buf_it; 1342 1343 for (int i = 0; i < numThreads; i++) { 1344 1345 buf_it = historyBuffer[i].begin(); 1346 1347 while (buf_it != historyBuffer[i].end()) { 1348 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1349 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1350 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1351 1352 buf_it++; 1353 } 1354 } 1355} 1356