rename_impl.hh revision 13598:39220222740c
1/* 2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_RENAME_IMPL_HH__ 46#define __CPU_O3_RENAME_IMPL_HH__ 47 48#include <list> 49 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "config/the_isa.hh" 53#include "cpu/o3/rename.hh" 54#include "cpu/reg_class.hh" 55#include "debug/Activity.hh" 56#include "debug/Rename.hh" 57#include "debug/O3PipeView.hh" 58#include "params/DerivO3CPU.hh" 59 60using namespace std; 61 62template <class Impl> 63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 64 : cpu(_cpu), 65 iewToRenameDelay(params->iewToRenameDelay), 66 decodeToRenameDelay(params->decodeToRenameDelay), 67 commitToRenameDelay(params->commitToRenameDelay), 68 renameWidth(params->renameWidth), 69 commitWidth(params->commitWidth), 70 numThreads(params->numThreads) 71{ 72 if (renameWidth > Impl::MaxWidth) 73 fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 74 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 75 renameWidth, static_cast<int>(Impl::MaxWidth)); 76 77 // @todo: Make into a parameter. 78 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 79 for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) { 80 renameStatus[tid] = Idle; 81 renameMap[tid] = nullptr; 82 instsInProgress[tid] = 0; 83 loadsInProgress[tid] = 0; 84 storesInProgress[tid] = 0; 85 freeEntries[tid] = {0, 0, 0, 0}; 86 emptyROB[tid] = true; 87 stalls[tid] = {false, false}; 88 serializeInst[tid] = nullptr; 89 serializeOnNextInst[tid] = false; 90 } 91} 92 93template <class Impl> 94std::string 95DefaultRename<Impl>::name() const 96{ 97 return cpu->name() + ".rename"; 98} 99 100template <class Impl> 101void 102DefaultRename<Impl>::regStats() 103{ 104 renameSquashCycles 105 .name(name() + ".SquashCycles") 106 .desc("Number of cycles rename is squashing") 107 .prereq(renameSquashCycles); 108 renameIdleCycles 109 .name(name() + ".IdleCycles") 110 .desc("Number of cycles rename is idle") 111 .prereq(renameIdleCycles); 112 renameBlockCycles 113 .name(name() + ".BlockCycles") 114 .desc("Number of cycles rename is blocking") 115 .prereq(renameBlockCycles); 116 renameSerializeStallCycles 117 .name(name() + ".serializeStallCycles") 118 .desc("count of cycles rename stalled for serializing inst") 119 .flags(Stats::total); 120 renameRunCycles 121 .name(name() + ".RunCycles") 122 .desc("Number of cycles rename is running") 123 .prereq(renameIdleCycles); 124 renameUnblockCycles 125 .name(name() + ".UnblockCycles") 126 .desc("Number of cycles rename is unblocking") 127 .prereq(renameUnblockCycles); 128 renameRenamedInsts 129 .name(name() + ".RenamedInsts") 130 .desc("Number of instructions processed by rename") 131 .prereq(renameRenamedInsts); 132 renameSquashedInsts 133 .name(name() + ".SquashedInsts") 134 .desc("Number of squashed instructions processed by rename") 135 .prereq(renameSquashedInsts); 136 renameROBFullEvents 137 .name(name() + ".ROBFullEvents") 138 .desc("Number of times rename has blocked due to ROB full") 139 .prereq(renameROBFullEvents); 140 renameIQFullEvents 141 .name(name() + ".IQFullEvents") 142 .desc("Number of times rename has blocked due to IQ full") 143 .prereq(renameIQFullEvents); 144 renameLQFullEvents 145 .name(name() + ".LQFullEvents") 146 .desc("Number of times rename has blocked due to LQ full") 147 .prereq(renameLQFullEvents); 148 renameSQFullEvents 149 .name(name() + ".SQFullEvents") 150 .desc("Number of times rename has blocked due to SQ full") 151 .prereq(renameSQFullEvents); 152 renameFullRegistersEvents 153 .name(name() + ".FullRegisterEvents") 154 .desc("Number of times there has been no free registers") 155 .prereq(renameFullRegistersEvents); 156 renameRenamedOperands 157 .name(name() + ".RenamedOperands") 158 .desc("Number of destination operands rename has renamed") 159 .prereq(renameRenamedOperands); 160 renameRenameLookups 161 .name(name() + ".RenameLookups") 162 .desc("Number of register rename lookups that rename has made") 163 .prereq(renameRenameLookups); 164 renameCommittedMaps 165 .name(name() + ".CommittedMaps") 166 .desc("Number of HB maps that are committed") 167 .prereq(renameCommittedMaps); 168 renameUndoneMaps 169 .name(name() + ".UndoneMaps") 170 .desc("Number of HB maps that are undone due to squashing") 171 .prereq(renameUndoneMaps); 172 renamedSerializing 173 .name(name() + ".serializingInsts") 174 .desc("count of serializing insts renamed") 175 .flags(Stats::total) 176 ; 177 renamedTempSerializing 178 .name(name() + ".tempSerializingInsts") 179 .desc("count of temporary serializing insts renamed") 180 .flags(Stats::total) 181 ; 182 renameSkidInsts 183 .name(name() + ".skidInsts") 184 .desc("count of insts added to the skid buffer") 185 .flags(Stats::total) 186 ; 187 intRenameLookups 188 .name(name() + ".int_rename_lookups") 189 .desc("Number of integer rename lookups") 190 .prereq(intRenameLookups); 191 fpRenameLookups 192 .name(name() + ".fp_rename_lookups") 193 .desc("Number of floating rename lookups") 194 .prereq(fpRenameLookups); 195 vecRenameLookups 196 .name(name() + ".vec_rename_lookups") 197 .desc("Number of vector rename lookups") 198 .prereq(vecRenameLookups); 199} 200 201template <class Impl> 202void 203DefaultRename<Impl>::regProbePoints() 204{ 205 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 206 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 207 "SquashInRename"); 208} 209 210template <class Impl> 211void 212DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 213{ 214 timeBuffer = tb_ptr; 215 216 // Setup wire to read information from time buffer, from IEW stage. 217 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 218 219 // Setup wire to read infromation from time buffer, from commit stage. 220 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 221 222 // Setup wire to write information to previous stages. 223 toDecode = timeBuffer->getWire(0); 224} 225 226template <class Impl> 227void 228DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 229{ 230 renameQueue = rq_ptr; 231 232 // Setup wire to write information to future stages. 233 toIEW = renameQueue->getWire(0); 234} 235 236template <class Impl> 237void 238DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 239{ 240 decodeQueue = dq_ptr; 241 242 // Setup wire to get information from decode. 243 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 244} 245 246template <class Impl> 247void 248DefaultRename<Impl>::startupStage() 249{ 250 resetStage(); 251} 252 253template <class Impl> 254void 255DefaultRename<Impl>::resetStage() 256{ 257 _status = Inactive; 258 259 resumeSerialize = false; 260 resumeUnblocking = false; 261 262 // Grab the number of free entries directly from the stages. 263 for (ThreadID tid = 0; tid < numThreads; tid++) { 264 renameStatus[tid] = Idle; 265 266 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 267 freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 268 freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 269 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 270 emptyROB[tid] = true; 271 272 stalls[tid].iew = false; 273 serializeInst[tid] = NULL; 274 275 instsInProgress[tid] = 0; 276 loadsInProgress[tid] = 0; 277 storesInProgress[tid] = 0; 278 279 serializeOnNextInst[tid] = false; 280 } 281} 282 283template<class Impl> 284void 285DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 286{ 287 activeThreads = at_ptr; 288} 289 290 291template <class Impl> 292void 293DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 294{ 295 for (ThreadID tid = 0; tid < numThreads; tid++) 296 renameMap[tid] = &rm_ptr[tid]; 297} 298 299template <class Impl> 300void 301DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 302{ 303 freeList = fl_ptr; 304} 305 306template<class Impl> 307void 308DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 309{ 310 scoreboard = _scoreboard; 311} 312 313template <class Impl> 314bool 315DefaultRename<Impl>::isDrained() const 316{ 317 for (ThreadID tid = 0; tid < numThreads; tid++) { 318 if (instsInProgress[tid] != 0 || 319 !historyBuffer[tid].empty() || 320 !skidBuffer[tid].empty() || 321 !insts[tid].empty() || 322 (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 323 return false; 324 } 325 return true; 326} 327 328template <class Impl> 329void 330DefaultRename<Impl>::takeOverFrom() 331{ 332 resetStage(); 333} 334 335template <class Impl> 336void 337DefaultRename<Impl>::drainSanityCheck() const 338{ 339 for (ThreadID tid = 0; tid < numThreads; tid++) { 340 assert(historyBuffer[tid].empty()); 341 assert(insts[tid].empty()); 342 assert(skidBuffer[tid].empty()); 343 assert(instsInProgress[tid] == 0); 344 } 345} 346 347template <class Impl> 348void 349DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 350{ 351 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 352 353 // Clear the stall signal if rename was blocked or unblocking before. 354 // If it still needs to block, the blocking should happen the next 355 // cycle and there should be space to hold everything due to the squash. 356 if (renameStatus[tid] == Blocked || 357 renameStatus[tid] == Unblocking) { 358 toDecode->renameUnblock[tid] = 1; 359 360 resumeSerialize = false; 361 serializeInst[tid] = NULL; 362 } else if (renameStatus[tid] == SerializeStall) { 363 if (serializeInst[tid]->seqNum <= squash_seq_num) { 364 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 365 resumeSerialize = true; 366 assert(serializeInst[tid]); 367 } else { 368 resumeSerialize = false; 369 toDecode->renameUnblock[tid] = 1; 370 371 serializeInst[tid] = NULL; 372 } 373 } 374 375 // Set the status to Squashing. 376 renameStatus[tid] = Squashing; 377 378 // Squash any instructions from decode. 379 for (int i=0; i<fromDecode->size; i++) { 380 if (fromDecode->insts[i]->threadNumber == tid && 381 fromDecode->insts[i]->seqNum > squash_seq_num) { 382 fromDecode->insts[i]->setSquashed(); 383 wroteToTimeBuffer = true; 384 } 385 386 } 387 388 // Clear the instruction list and skid buffer in case they have any 389 // insts in them. 390 insts[tid].clear(); 391 392 // Clear the skid buffer in case it has any data in it. 393 skidBuffer[tid].clear(); 394 395 doSquash(squash_seq_num, tid); 396} 397 398template <class Impl> 399void 400DefaultRename<Impl>::tick() 401{ 402 wroteToTimeBuffer = false; 403 404 blockThisCycle = false; 405 406 bool status_change = false; 407 408 toIEWIndex = 0; 409 410 sortInsts(); 411 412 list<ThreadID>::iterator threads = activeThreads->begin(); 413 list<ThreadID>::iterator end = activeThreads->end(); 414 415 // Check stall and squash signals. 416 while (threads != end) { 417 ThreadID tid = *threads++; 418 419 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 420 421 status_change = checkSignalsAndUpdate(tid) || status_change; 422 423 rename(status_change, tid); 424 } 425 426 if (status_change) { 427 updateStatus(); 428 } 429 430 if (wroteToTimeBuffer) { 431 DPRINTF(Activity, "Activity this cycle.\n"); 432 cpu->activityThisCycle(); 433 } 434 435 threads = activeThreads->begin(); 436 437 while (threads != end) { 438 ThreadID tid = *threads++; 439 440 // If we committed this cycle then doneSeqNum will be > 0 441 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 442 !fromCommit->commitInfo[tid].squash && 443 renameStatus[tid] != Squashing) { 444 445 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 446 tid); 447 } 448 } 449 450 // @todo: make into updateProgress function 451 for (ThreadID tid = 0; tid < numThreads; tid++) { 452 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 453 loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 454 storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 455 assert(loadsInProgress[tid] >= 0); 456 assert(storesInProgress[tid] >= 0); 457 assert(instsInProgress[tid] >=0); 458 } 459 460} 461 462template<class Impl> 463void 464DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 465{ 466 // If status is Running or idle, 467 // call renameInsts() 468 // If status is Unblocking, 469 // buffer any instructions coming from decode 470 // continue trying to empty skid buffer 471 // check if stall conditions have passed 472 473 if (renameStatus[tid] == Blocked) { 474 ++renameBlockCycles; 475 } else if (renameStatus[tid] == Squashing) { 476 ++renameSquashCycles; 477 } else if (renameStatus[tid] == SerializeStall) { 478 ++renameSerializeStallCycles; 479 // If we are currently in SerializeStall and resumeSerialize 480 // was set, then that means that we are resuming serializing 481 // this cycle. Tell the previous stages to block. 482 if (resumeSerialize) { 483 resumeSerialize = false; 484 block(tid); 485 toDecode->renameUnblock[tid] = false; 486 } 487 } else if (renameStatus[tid] == Unblocking) { 488 if (resumeUnblocking) { 489 block(tid); 490 resumeUnblocking = false; 491 toDecode->renameUnblock[tid] = false; 492 } 493 } 494 495 if (renameStatus[tid] == Running || 496 renameStatus[tid] == Idle) { 497 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 498 "stage.\n", tid); 499 500 renameInsts(tid); 501 } else if (renameStatus[tid] == Unblocking) { 502 renameInsts(tid); 503 504 if (validInsts()) { 505 // Add the current inputs to the skid buffer so they can be 506 // reprocessed when this stage unblocks. 507 skidInsert(tid); 508 } 509 510 // If we switched over to blocking, then there's a potential for 511 // an overall status change. 512 status_change = unblock(tid) || status_change || blockThisCycle; 513 } 514} 515 516template <class Impl> 517void 518DefaultRename<Impl>::renameInsts(ThreadID tid) 519{ 520 // Instructions can be either in the skid buffer or the queue of 521 // instructions coming from decode, depending on the status. 522 int insts_available = renameStatus[tid] == Unblocking ? 523 skidBuffer[tid].size() : insts[tid].size(); 524 525 // Check the decode queue to see if instructions are available. 526 // If there are no available instructions to rename, then do nothing. 527 if (insts_available == 0) { 528 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 529 tid); 530 // Should I change status to idle? 531 ++renameIdleCycles; 532 return; 533 } else if (renameStatus[tid] == Unblocking) { 534 ++renameUnblockCycles; 535 } else if (renameStatus[tid] == Running) { 536 ++renameRunCycles; 537 } 538 539 // Will have to do a different calculation for the number of free 540 // entries. 541 int free_rob_entries = calcFreeROBEntries(tid); 542 int free_iq_entries = calcFreeIQEntries(tid); 543 int min_free_entries = free_rob_entries; 544 545 FullSource source = ROB; 546 547 if (free_iq_entries < min_free_entries) { 548 min_free_entries = free_iq_entries; 549 source = IQ; 550 } 551 552 // Check if there's any space left. 553 if (min_free_entries <= 0) { 554 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 555 "entries.\n" 556 "ROB has %i free entries.\n" 557 "IQ has %i free entries.\n", 558 tid, 559 free_rob_entries, 560 free_iq_entries); 561 562 blockThisCycle = true; 563 564 block(tid); 565 566 incrFullStat(source); 567 568 return; 569 } else if (min_free_entries < insts_available) { 570 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 571 "%i insts available, but only %i insts can be " 572 "renamed due to ROB/IQ/LSQ limits.\n", 573 tid, insts_available, min_free_entries); 574 575 insts_available = min_free_entries; 576 577 blockThisCycle = true; 578 579 incrFullStat(source); 580 } 581 582 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 583 skidBuffer[tid] : insts[tid]; 584 585 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 586 "send iew.\n", tid, insts_available); 587 588 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 589 "dispatched to IQ last cycle.\n", 590 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 591 592 // Handle serializing the next instruction if necessary. 593 if (serializeOnNextInst[tid]) { 594 if (emptyROB[tid] && instsInProgress[tid] == 0) { 595 // ROB already empty; no need to serialize. 596 serializeOnNextInst[tid] = false; 597 } else if (!insts_to_rename.empty()) { 598 insts_to_rename.front()->setSerializeBefore(); 599 } 600 } 601 602 int renamed_insts = 0; 603 604 while (insts_available > 0 && toIEWIndex < renameWidth) { 605 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 606 607 assert(!insts_to_rename.empty()); 608 609 DynInstPtr inst = insts_to_rename.front(); 610 611 //For all kind of instructions, check ROB and IQ first 612 //For load instruction, check LQ size and take into account the inflight loads 613 //For store instruction, check SQ size and take into account the inflight stores 614 615 if (inst->isLoad()) { 616 if (calcFreeLQEntries(tid) <= 0) { 617 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 618 source = LQ; 619 incrFullStat(source); 620 break; 621 } 622 } 623 624 if (inst->isStore()) { 625 if (calcFreeSQEntries(tid) <= 0) { 626 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 627 source = SQ; 628 incrFullStat(source); 629 break; 630 } 631 } 632 633 insts_to_rename.pop_front(); 634 635 if (renameStatus[tid] == Unblocking) { 636 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 637 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 638 } 639 640 if (inst->isSquashed()) { 641 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 642 "squashed, skipping.\n", tid, inst->seqNum, 643 inst->pcState()); 644 645 ++renameSquashedInsts; 646 647 // Decrement how many instructions are available. 648 --insts_available; 649 650 continue; 651 } 652 653 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 654 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 655 656 // Check here to make sure there are enough destination registers 657 // to rename to. Otherwise block. 658 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 659 inst->numFPDestRegs(), 660 inst->numVecDestRegs(), 661 inst->numVecElemDestRegs(), 662 inst->numCCDestRegs())) { 663 DPRINTF(Rename, "Blocking due to lack of free " 664 "physical registers to rename to.\n"); 665 blockThisCycle = true; 666 insts_to_rename.push_front(inst); 667 ++renameFullRegistersEvents; 668 669 break; 670 } 671 672 // Handle serializeAfter/serializeBefore instructions. 673 // serializeAfter marks the next instruction as serializeBefore. 674 // serializeBefore makes the instruction wait in rename until the ROB 675 // is empty. 676 677 // In this model, IPR accesses are serialize before 678 // instructions, and store conditionals are serialize after 679 // instructions. This is mainly due to lack of support for 680 // out-of-order operations of either of those classes of 681 // instructions. 682 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 683 !inst->isSerializeHandled()) { 684 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 685 686 if (!inst->isTempSerializeBefore()) { 687 renamedSerializing++; 688 inst->setSerializeHandled(); 689 } else { 690 renamedTempSerializing++; 691 } 692 693 // Change status over to SerializeStall so that other stages know 694 // what this is blocked on. 695 renameStatus[tid] = SerializeStall; 696 697 serializeInst[tid] = inst; 698 699 blockThisCycle = true; 700 701 break; 702 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 703 !inst->isSerializeHandled()) { 704 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 705 706 renamedSerializing++; 707 708 inst->setSerializeHandled(); 709 710 serializeAfter(insts_to_rename, tid); 711 } 712 713 renameSrcRegs(inst, inst->threadNumber); 714 715 renameDestRegs(inst, inst->threadNumber); 716 717 if (inst->isLoad()) { 718 loadsInProgress[tid]++; 719 } 720 if (inst->isStore()) { 721 storesInProgress[tid]++; 722 } 723 ++renamed_insts; 724 // Notify potential listeners that source and destination registers for 725 // this instruction have been renamed. 726 ppRename->notify(inst); 727 728 // Put instruction in rename queue. 729 toIEW->insts[toIEWIndex] = inst; 730 ++(toIEW->size); 731 732 // Increment which instruction we're on. 733 ++toIEWIndex; 734 735 // Decrement how many instructions are available. 736 --insts_available; 737 } 738 739 instsInProgress[tid] += renamed_insts; 740 renameRenamedInsts += renamed_insts; 741 742 // If we wrote to the time buffer, record this. 743 if (toIEWIndex) { 744 wroteToTimeBuffer = true; 745 } 746 747 // Check if there's any instructions left that haven't yet been renamed. 748 // If so then block. 749 if (insts_available) { 750 blockThisCycle = true; 751 } 752 753 if (blockThisCycle) { 754 block(tid); 755 toDecode->renameUnblock[tid] = false; 756 } 757} 758 759template<class Impl> 760void 761DefaultRename<Impl>::skidInsert(ThreadID tid) 762{ 763 DynInstPtr inst = NULL; 764 765 while (!insts[tid].empty()) { 766 inst = insts[tid].front(); 767 768 insts[tid].pop_front(); 769 770 assert(tid == inst->threadNumber); 771 772 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 773 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 774 775 ++renameSkidInsts; 776 777 skidBuffer[tid].push_back(inst); 778 } 779 780 if (skidBuffer[tid].size() > skidBufferMax) 781 { 782 typename InstQueue::iterator it; 783 warn("Skidbuffer contents:\n"); 784 for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 785 { 786 warn("[tid:%u]: %s [sn:%i].\n", tid, 787 (*it)->staticInst->disassemble(inst->instAddr()), 788 (*it)->seqNum); 789 } 790 panic("Skidbuffer Exceeded Max Size"); 791 } 792} 793 794template <class Impl> 795void 796DefaultRename<Impl>::sortInsts() 797{ 798 int insts_from_decode = fromDecode->size; 799 for (int i = 0; i < insts_from_decode; ++i) { 800 const DynInstPtr &inst = fromDecode->insts[i]; 801 insts[inst->threadNumber].push_back(inst); 802#if TRACING_ON 803 if (DTRACE(O3PipeView)) { 804 inst->renameTick = curTick() - inst->fetchTick; 805 } 806#endif 807 } 808} 809 810template<class Impl> 811bool 812DefaultRename<Impl>::skidsEmpty() 813{ 814 list<ThreadID>::iterator threads = activeThreads->begin(); 815 list<ThreadID>::iterator end = activeThreads->end(); 816 817 while (threads != end) { 818 ThreadID tid = *threads++; 819 820 if (!skidBuffer[tid].empty()) 821 return false; 822 } 823 824 return true; 825} 826 827template<class Impl> 828void 829DefaultRename<Impl>::updateStatus() 830{ 831 bool any_unblocking = false; 832 833 list<ThreadID>::iterator threads = activeThreads->begin(); 834 list<ThreadID>::iterator end = activeThreads->end(); 835 836 while (threads != end) { 837 ThreadID tid = *threads++; 838 839 if (renameStatus[tid] == Unblocking) { 840 any_unblocking = true; 841 break; 842 } 843 } 844 845 // Rename will have activity if it's unblocking. 846 if (any_unblocking) { 847 if (_status == Inactive) { 848 _status = Active; 849 850 DPRINTF(Activity, "Activating stage.\n"); 851 852 cpu->activateStage(O3CPU::RenameIdx); 853 } 854 } else { 855 // If it's not unblocking, then rename will not have any internal 856 // activity. Switch it to inactive. 857 if (_status == Active) { 858 _status = Inactive; 859 DPRINTF(Activity, "Deactivating stage.\n"); 860 861 cpu->deactivateStage(O3CPU::RenameIdx); 862 } 863 } 864} 865 866template <class Impl> 867bool 868DefaultRename<Impl>::block(ThreadID tid) 869{ 870 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 871 872 // Add the current inputs onto the skid buffer, so they can be 873 // reprocessed when this stage unblocks. 874 skidInsert(tid); 875 876 // Only signal backwards to block if the previous stages do not think 877 // rename is already blocked. 878 if (renameStatus[tid] != Blocked) { 879 // If resumeUnblocking is set, we unblocked during the squash, 880 // but now we're have unblocking status. We need to tell earlier 881 // stages to block. 882 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 883 toDecode->renameBlock[tid] = true; 884 toDecode->renameUnblock[tid] = false; 885 wroteToTimeBuffer = true; 886 } 887 888 // Rename can not go from SerializeStall to Blocked, otherwise 889 // it would not know to complete the serialize stall. 890 if (renameStatus[tid] != SerializeStall) { 891 // Set status to Blocked. 892 renameStatus[tid] = Blocked; 893 return true; 894 } 895 } 896 897 return false; 898} 899 900template <class Impl> 901bool 902DefaultRename<Impl>::unblock(ThreadID tid) 903{ 904 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 905 906 // Rename is done unblocking if the skid buffer is empty. 907 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 908 909 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 910 911 toDecode->renameUnblock[tid] = true; 912 wroteToTimeBuffer = true; 913 914 renameStatus[tid] = Running; 915 return true; 916 } 917 918 return false; 919} 920 921template <class Impl> 922void 923DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 924{ 925 typename std::list<RenameHistory>::iterator hb_it = 926 historyBuffer[tid].begin(); 927 928 // After a syscall squashes everything, the history buffer may be empty 929 // but the ROB may still be squashing instructions. 930 if (historyBuffer[tid].empty()) { 931 return; 932 } 933 934 // Go through the most recent instructions, undoing the mappings 935 // they did and freeing up the registers. 936 while (!historyBuffer[tid].empty() && 937 hb_it->instSeqNum > squashed_seq_num) { 938 assert(hb_it != historyBuffer[tid].end()); 939 940 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 941 "number %i.\n", tid, hb_it->instSeqNum); 942 943 // Undo the rename mapping only if it was really a change. 944 // Special regs that are not really renamed (like misc regs 945 // and the zero reg) can be recognized because the new mapping 946 // is the same as the old one. While it would be merely a 947 // waste of time to update the rename table, we definitely 948 // don't want to put these on the free list. 949 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 950 // Tell the rename map to set the architected register to the 951 // previous physical register that it was renamed to. 952 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 953 954 // Put the renamed physical register back on the free list. 955 freeList->addReg(hb_it->newPhysReg); 956 } 957 958 // Notify potential listeners that the register mapping needs to be 959 // removed because the instruction it was mapped to got squashed. Note 960 // that this is done before hb_it is incremented. 961 ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 962 hb_it->newPhysReg)); 963 964 historyBuffer[tid].erase(hb_it++); 965 966 ++renameUndoneMaps; 967 } 968} 969 970template<class Impl> 971void 972DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 973{ 974 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 975 "history buffer %u (size=%i), until [sn:%lli].\n", 976 tid, tid, historyBuffer[tid].size(), inst_seq_num); 977 978 typename std::list<RenameHistory>::iterator hb_it = 979 historyBuffer[tid].end(); 980 981 --hb_it; 982 983 if (historyBuffer[tid].empty()) { 984 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 985 return; 986 } else if (hb_it->instSeqNum > inst_seq_num) { 987 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 988 "that a syscall happened recently.\n", tid); 989 return; 990 } 991 992 // Commit all the renames up until (and including) the committed sequence 993 // number. Some or even all of the committed instructions may not have 994 // rename histories if they did not have destination registers that were 995 // renamed. 996 while (!historyBuffer[tid].empty() && 997 hb_it != historyBuffer[tid].end() && 998 hb_it->instSeqNum <= inst_seq_num) { 999 1000 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 1001 "[sn:%lli].\n", 1002 tid, hb_it->prevPhysReg->index(), 1003 hb_it->prevPhysReg->className(), 1004 hb_it->instSeqNum); 1005 1006 // Don't free special phys regs like misc and zero regs, which 1007 // can be recognized because the new mapping is the same as 1008 // the old one. 1009 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 1010 freeList->addReg(hb_it->prevPhysReg); 1011 } 1012 1013 ++renameCommittedMaps; 1014 1015 historyBuffer[tid].erase(hb_it--); 1016 } 1017} 1018 1019template <class Impl> 1020inline void 1021DefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid) 1022{ 1023 ThreadContext *tc = inst->tcBase(); 1024 RenameMap *map = renameMap[tid]; 1025 unsigned num_src_regs = inst->numSrcRegs(); 1026 1027 // Get the architectual register numbers from the source and 1028 // operands, and redirect them to the right physical register. 1029 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1030 const RegId& src_reg = inst->srcRegIdx(src_idx); 1031 PhysRegIdPtr renamed_reg; 1032 1033 renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 1034 switch (src_reg.classValue()) { 1035 case IntRegClass: 1036 intRenameLookups++; 1037 break; 1038 case FloatRegClass: 1039 fpRenameLookups++; 1040 break; 1041 case VecRegClass: 1042 case VecElemClass: 1043 vecRenameLookups++; 1044 break; 1045 case CCRegClass: 1046 case MiscRegClass: 1047 break; 1048 1049 default: 1050 panic("Invalid register class: %d.", src_reg.classValue()); 1051 } 1052 1053 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 1054 ", got phys reg %i (%s)\n", tid, 1055 src_reg.className(), src_reg.index(), 1056 renamed_reg->index(), 1057 renamed_reg->className()); 1058 1059 inst->renameSrcReg(src_idx, renamed_reg); 1060 1061 // See if the register is ready or not. 1062 if (scoreboard->getReg(renamed_reg)) { 1063 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1064 " is ready.\n", tid, renamed_reg->index(), 1065 renamed_reg->flatIndex(), 1066 renamed_reg->className()); 1067 1068 inst->markSrcRegReady(src_idx); 1069 } else { 1070 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1071 " is not ready.\n", tid, renamed_reg->index(), 1072 renamed_reg->flatIndex(), 1073 renamed_reg->className()); 1074 } 1075 1076 ++renameRenameLookups; 1077 } 1078} 1079 1080template <class Impl> 1081inline void 1082DefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid) 1083{ 1084 ThreadContext *tc = inst->tcBase(); 1085 RenameMap *map = renameMap[tid]; 1086 unsigned num_dest_regs = inst->numDestRegs(); 1087 1088 // Rename the destination registers. 1089 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1090 const RegId& dest_reg = inst->destRegIdx(dest_idx); 1091 typename RenameMap::RenameInfo rename_result; 1092 1093 RegId flat_dest_regid = tc->flattenRegId(dest_reg); 1094 1095 rename_result = map->rename(flat_dest_regid); 1096 1097 inst->flattenDestReg(dest_idx, flat_dest_regid); 1098 1099 // Mark Scoreboard entry as not ready 1100 scoreboard->unsetReg(rename_result.first); 1101 1102 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 1103 "reg %i (%i).\n", tid, dest_reg.index(), 1104 dest_reg.className(), 1105 rename_result.first->index(), 1106 rename_result.first->flatIndex()); 1107 1108 // Record the rename information so that a history can be kept. 1109 RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 1110 rename_result.first, 1111 rename_result.second); 1112 1113 historyBuffer[tid].push_front(hb_entry); 1114 1115 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1116 "(size=%i), [sn:%lli].\n",tid, 1117 historyBuffer[tid].size(), 1118 (*historyBuffer[tid].begin()).instSeqNum); 1119 1120 // Tell the instruction to rename the appropriate destination 1121 // register (dest_idx) to the new physical register 1122 // (rename_result.first), and record the previous physical 1123 // register that the same logical register was renamed to 1124 // (rename_result.second). 1125 inst->renameDestReg(dest_idx, 1126 rename_result.first, 1127 rename_result.second); 1128 1129 ++renameRenamedOperands; 1130 } 1131} 1132 1133template <class Impl> 1134inline int 1135DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1136{ 1137 int num_free = freeEntries[tid].robEntries - 1138 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1139 1140 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1141 1142 return num_free; 1143} 1144 1145template <class Impl> 1146inline int 1147DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1148{ 1149 int num_free = freeEntries[tid].iqEntries - 1150 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1151 1152 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1153 1154 return num_free; 1155} 1156 1157template <class Impl> 1158inline int 1159DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1160{ 1161 int num_free = freeEntries[tid].lqEntries - 1162 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1163 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1164 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1165 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1166 return num_free; 1167} 1168 1169template <class Impl> 1170inline int 1171DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1172{ 1173 int num_free = freeEntries[tid].sqEntries - 1174 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1175 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1176 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1177 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1178 return num_free; 1179} 1180 1181template <class Impl> 1182unsigned 1183DefaultRename<Impl>::validInsts() 1184{ 1185 unsigned inst_count = 0; 1186 1187 for (int i=0; i<fromDecode->size; i++) { 1188 if (!fromDecode->insts[i]->isSquashed()) 1189 inst_count++; 1190 } 1191 1192 return inst_count; 1193} 1194 1195template <class Impl> 1196void 1197DefaultRename<Impl>::readStallSignals(ThreadID tid) 1198{ 1199 if (fromIEW->iewBlock[tid]) { 1200 stalls[tid].iew = true; 1201 } 1202 1203 if (fromIEW->iewUnblock[tid]) { 1204 assert(stalls[tid].iew); 1205 stalls[tid].iew = false; 1206 } 1207} 1208 1209template <class Impl> 1210bool 1211DefaultRename<Impl>::checkStall(ThreadID tid) 1212{ 1213 bool ret_val = false; 1214 1215 if (stalls[tid].iew) { 1216 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1217 ret_val = true; 1218 } else if (calcFreeROBEntries(tid) <= 0) { 1219 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1220 ret_val = true; 1221 } else if (calcFreeIQEntries(tid) <= 0) { 1222 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1223 ret_val = true; 1224 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 1225 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1226 ret_val = true; 1227 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1228 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1229 ret_val = true; 1230 } else if (renameStatus[tid] == SerializeStall && 1231 (!emptyROB[tid] || instsInProgress[tid])) { 1232 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1233 "empty.\n", 1234 tid); 1235 ret_val = true; 1236 } 1237 1238 return ret_val; 1239} 1240 1241template <class Impl> 1242void 1243DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1244{ 1245 if (fromIEW->iewInfo[tid].usedIQ) 1246 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1247 1248 if (fromIEW->iewInfo[tid].usedLSQ) { 1249 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1250 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1251 } 1252 1253 if (fromCommit->commitInfo[tid].usedROB) { 1254 freeEntries[tid].robEntries = 1255 fromCommit->commitInfo[tid].freeROBEntries; 1256 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1257 } 1258 1259 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1260 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n", 1261 tid, 1262 freeEntries[tid].iqEntries, 1263 freeEntries[tid].robEntries, 1264 freeEntries[tid].lqEntries, 1265 freeEntries[tid].sqEntries, 1266 renameMap[tid]->numFreeEntries(), 1267 renameMap[tid]->numFreeIntEntries(), 1268 renameMap[tid]->numFreeFloatEntries(), 1269 renameMap[tid]->numFreeVecEntries(), 1270 renameMap[tid]->numFreeCCEntries()); 1271 1272 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1273 tid, instsInProgress[tid]); 1274} 1275 1276template <class Impl> 1277bool 1278DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1279{ 1280 // Check if there's a squash signal, squash if there is 1281 // Check stall signals, block if necessary. 1282 // If status was blocked 1283 // check if stall conditions have passed 1284 // if so then go to unblocking 1285 // If status was Squashing 1286 // check if squashing is not high. Switch to running this cycle. 1287 // If status was serialize stall 1288 // check if ROB is empty and no insts are in flight to the ROB 1289 1290 readFreeEntries(tid); 1291 readStallSignals(tid); 1292 1293 if (fromCommit->commitInfo[tid].squash) { 1294 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1295 "commit.\n", tid); 1296 1297 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1298 1299 return true; 1300 } 1301 1302 if (checkStall(tid)) { 1303 return block(tid); 1304 } 1305 1306 if (renameStatus[tid] == Blocked) { 1307 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1308 tid); 1309 1310 renameStatus[tid] = Unblocking; 1311 1312 unblock(tid); 1313 1314 return true; 1315 } 1316 1317 if (renameStatus[tid] == Squashing) { 1318 // Switch status to running if rename isn't being told to block or 1319 // squash this cycle. 1320 if (resumeSerialize) { 1321 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1322 tid); 1323 1324 renameStatus[tid] = SerializeStall; 1325 return true; 1326 } else if (resumeUnblocking) { 1327 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1328 tid); 1329 renameStatus[tid] = Unblocking; 1330 return true; 1331 } else { 1332 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1333 tid); 1334 1335 renameStatus[tid] = Running; 1336 return false; 1337 } 1338 } 1339 1340 if (renameStatus[tid] == SerializeStall) { 1341 // Stall ends once the ROB is free. 1342 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1343 "unblocking.\n", tid); 1344 1345 DynInstPtr serial_inst = serializeInst[tid]; 1346 1347 renameStatus[tid] = Unblocking; 1348 1349 unblock(tid); 1350 1351 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1352 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1353 1354 // Put instruction into queue here. 1355 serial_inst->clearSerializeBefore(); 1356 1357 if (!skidBuffer[tid].empty()) { 1358 skidBuffer[tid].push_front(serial_inst); 1359 } else { 1360 insts[tid].push_front(serial_inst); 1361 } 1362 1363 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1364 " Adding to front of list.\n", tid); 1365 1366 serializeInst[tid] = NULL; 1367 1368 return true; 1369 } 1370 1371 // If we've reached this point, we have not gotten any signals that 1372 // cause rename to change its status. Rename remains the same as before. 1373 return false; 1374} 1375 1376template<class Impl> 1377void 1378DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1379{ 1380 if (inst_list.empty()) { 1381 // Mark a bit to say that I must serialize on the next instruction. 1382 serializeOnNextInst[tid] = true; 1383 return; 1384 } 1385 1386 // Set the next instruction as serializing. 1387 inst_list.front()->setSerializeBefore(); 1388} 1389 1390template <class Impl> 1391inline void 1392DefaultRename<Impl>::incrFullStat(const FullSource &source) 1393{ 1394 switch (source) { 1395 case ROB: 1396 ++renameROBFullEvents; 1397 break; 1398 case IQ: 1399 ++renameIQFullEvents; 1400 break; 1401 case LQ: 1402 ++renameLQFullEvents; 1403 break; 1404 case SQ: 1405 ++renameSQFullEvents; 1406 break; 1407 default: 1408 panic("Rename full stall stat should be incremented for a reason!"); 1409 break; 1410 } 1411} 1412 1413template <class Impl> 1414void 1415DefaultRename<Impl>::dumpHistory() 1416{ 1417 typename std::list<RenameHistory>::iterator buf_it; 1418 1419 for (ThreadID tid = 0; tid < numThreads; tid++) { 1420 1421 buf_it = historyBuffer[tid].begin(); 1422 1423 while (buf_it != historyBuffer[tid].end()) { 1424 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 1425 " %i[%s] Old phys reg: %i[%s]\n", 1426 (*buf_it).instSeqNum, 1427 (*buf_it).archReg.className(), 1428 (*buf_it).archReg.index(), 1429 (*buf_it).newPhysReg->index(), 1430 (*buf_it).newPhysReg->className(), 1431 (*buf_it).prevPhysReg->index(), 1432 (*buf_it).prevPhysReg->className()); 1433 1434 buf_it++; 1435 } 1436 } 1437} 1438 1439#endif//__CPU_O3_RENAME_IMPL_HH__ 1440