rename_impl.hh revision 13429
1/* 2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_RENAME_IMPL_HH__ 46#define __CPU_O3_RENAME_IMPL_HH__ 47 48#include <list> 49 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "config/the_isa.hh" 53#include "cpu/o3/rename.hh" 54#include "cpu/reg_class.hh" 55#include "debug/Activity.hh" 56#include "debug/Rename.hh" 57#include "debug/O3PipeView.hh" 58#include "params/DerivO3CPU.hh" 59 60using namespace std; 61 62template <class Impl> 63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 64 : cpu(_cpu), 65 iewToRenameDelay(params->iewToRenameDelay), 66 decodeToRenameDelay(params->decodeToRenameDelay), 67 commitToRenameDelay(params->commitToRenameDelay), 68 renameWidth(params->renameWidth), 69 commitWidth(params->commitWidth), 70 numThreads(params->numThreads) 71{ 72 if (renameWidth > Impl::MaxWidth) 73 fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 74 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 75 renameWidth, static_cast<int>(Impl::MaxWidth)); 76 77 // @todo: Make into a parameter. 78 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 79} 80 81template <class Impl> 82std::string 83DefaultRename<Impl>::name() const 84{ 85 return cpu->name() + ".rename"; 86} 87 88template <class Impl> 89void 90DefaultRename<Impl>::regStats() 91{ 92 renameSquashCycles 93 .name(name() + ".SquashCycles") 94 .desc("Number of cycles rename is squashing") 95 .prereq(renameSquashCycles); 96 renameIdleCycles 97 .name(name() + ".IdleCycles") 98 .desc("Number of cycles rename is idle") 99 .prereq(renameIdleCycles); 100 renameBlockCycles 101 .name(name() + ".BlockCycles") 102 .desc("Number of cycles rename is blocking") 103 .prereq(renameBlockCycles); 104 renameSerializeStallCycles 105 .name(name() + ".serializeStallCycles") 106 .desc("count of cycles rename stalled for serializing inst") 107 .flags(Stats::total); 108 renameRunCycles 109 .name(name() + ".RunCycles") 110 .desc("Number of cycles rename is running") 111 .prereq(renameIdleCycles); 112 renameUnblockCycles 113 .name(name() + ".UnblockCycles") 114 .desc("Number of cycles rename is unblocking") 115 .prereq(renameUnblockCycles); 116 renameRenamedInsts 117 .name(name() + ".RenamedInsts") 118 .desc("Number of instructions processed by rename") 119 .prereq(renameRenamedInsts); 120 renameSquashedInsts 121 .name(name() + ".SquashedInsts") 122 .desc("Number of squashed instructions processed by rename") 123 .prereq(renameSquashedInsts); 124 renameROBFullEvents 125 .name(name() + ".ROBFullEvents") 126 .desc("Number of times rename has blocked due to ROB full") 127 .prereq(renameROBFullEvents); 128 renameIQFullEvents 129 .name(name() + ".IQFullEvents") 130 .desc("Number of times rename has blocked due to IQ full") 131 .prereq(renameIQFullEvents); 132 renameLQFullEvents 133 .name(name() + ".LQFullEvents") 134 .desc("Number of times rename has blocked due to LQ full") 135 .prereq(renameLQFullEvents); 136 renameSQFullEvents 137 .name(name() + ".SQFullEvents") 138 .desc("Number of times rename has blocked due to SQ full") 139 .prereq(renameSQFullEvents); 140 renameFullRegistersEvents 141 .name(name() + ".FullRegisterEvents") 142 .desc("Number of times there has been no free registers") 143 .prereq(renameFullRegistersEvents); 144 renameRenamedOperands 145 .name(name() + ".RenamedOperands") 146 .desc("Number of destination operands rename has renamed") 147 .prereq(renameRenamedOperands); 148 renameRenameLookups 149 .name(name() + ".RenameLookups") 150 .desc("Number of register rename lookups that rename has made") 151 .prereq(renameRenameLookups); 152 renameCommittedMaps 153 .name(name() + ".CommittedMaps") 154 .desc("Number of HB maps that are committed") 155 .prereq(renameCommittedMaps); 156 renameUndoneMaps 157 .name(name() + ".UndoneMaps") 158 .desc("Number of HB maps that are undone due to squashing") 159 .prereq(renameUndoneMaps); 160 renamedSerializing 161 .name(name() + ".serializingInsts") 162 .desc("count of serializing insts renamed") 163 .flags(Stats::total) 164 ; 165 renamedTempSerializing 166 .name(name() + ".tempSerializingInsts") 167 .desc("count of temporary serializing insts renamed") 168 .flags(Stats::total) 169 ; 170 renameSkidInsts 171 .name(name() + ".skidInsts") 172 .desc("count of insts added to the skid buffer") 173 .flags(Stats::total) 174 ; 175 intRenameLookups 176 .name(name() + ".int_rename_lookups") 177 .desc("Number of integer rename lookups") 178 .prereq(intRenameLookups); 179 fpRenameLookups 180 .name(name() + ".fp_rename_lookups") 181 .desc("Number of floating rename lookups") 182 .prereq(fpRenameLookups); 183 vecRenameLookups 184 .name(name() + ".vec_rename_lookups") 185 .desc("Number of vector rename lookups") 186 .prereq(vecRenameLookups); 187} 188 189template <class Impl> 190void 191DefaultRename<Impl>::regProbePoints() 192{ 193 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 194 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 195 "SquashInRename"); 196} 197 198template <class Impl> 199void 200DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 201{ 202 timeBuffer = tb_ptr; 203 204 // Setup wire to read information from time buffer, from IEW stage. 205 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 206 207 // Setup wire to read infromation from time buffer, from commit stage. 208 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 209 210 // Setup wire to write information to previous stages. 211 toDecode = timeBuffer->getWire(0); 212} 213 214template <class Impl> 215void 216DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 217{ 218 renameQueue = rq_ptr; 219 220 // Setup wire to write information to future stages. 221 toIEW = renameQueue->getWire(0); 222} 223 224template <class Impl> 225void 226DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 227{ 228 decodeQueue = dq_ptr; 229 230 // Setup wire to get information from decode. 231 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 232} 233 234template <class Impl> 235void 236DefaultRename<Impl>::startupStage() 237{ 238 resetStage(); 239} 240 241template <class Impl> 242void 243DefaultRename<Impl>::resetStage() 244{ 245 _status = Inactive; 246 247 resumeSerialize = false; 248 resumeUnblocking = false; 249 250 // Grab the number of free entries directly from the stages. 251 for (ThreadID tid = 0; tid < numThreads; tid++) { 252 renameStatus[tid] = Idle; 253 254 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 255 freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 256 freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 257 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 258 emptyROB[tid] = true; 259 260 stalls[tid].iew = false; 261 serializeInst[tid] = NULL; 262 263 instsInProgress[tid] = 0; 264 loadsInProgress[tid] = 0; 265 storesInProgress[tid] = 0; 266 267 serializeOnNextInst[tid] = false; 268 } 269} 270 271template<class Impl> 272void 273DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 274{ 275 activeThreads = at_ptr; 276} 277 278 279template <class Impl> 280void 281DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 282{ 283 for (ThreadID tid = 0; tid < numThreads; tid++) 284 renameMap[tid] = &rm_ptr[tid]; 285} 286 287template <class Impl> 288void 289DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 290{ 291 freeList = fl_ptr; 292} 293 294template<class Impl> 295void 296DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 297{ 298 scoreboard = _scoreboard; 299} 300 301template <class Impl> 302bool 303DefaultRename<Impl>::isDrained() const 304{ 305 for (ThreadID tid = 0; tid < numThreads; tid++) { 306 if (instsInProgress[tid] != 0 || 307 !historyBuffer[tid].empty() || 308 !skidBuffer[tid].empty() || 309 !insts[tid].empty() || 310 (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 311 return false; 312 } 313 return true; 314} 315 316template <class Impl> 317void 318DefaultRename<Impl>::takeOverFrom() 319{ 320 resetStage(); 321} 322 323template <class Impl> 324void 325DefaultRename<Impl>::drainSanityCheck() const 326{ 327 for (ThreadID tid = 0; tid < numThreads; tid++) { 328 assert(historyBuffer[tid].empty()); 329 assert(insts[tid].empty()); 330 assert(skidBuffer[tid].empty()); 331 assert(instsInProgress[tid] == 0); 332 } 333} 334 335template <class Impl> 336void 337DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 338{ 339 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 340 341 // Clear the stall signal if rename was blocked or unblocking before. 342 // If it still needs to block, the blocking should happen the next 343 // cycle and there should be space to hold everything due to the squash. 344 if (renameStatus[tid] == Blocked || 345 renameStatus[tid] == Unblocking) { 346 toDecode->renameUnblock[tid] = 1; 347 348 resumeSerialize = false; 349 serializeInst[tid] = NULL; 350 } else if (renameStatus[tid] == SerializeStall) { 351 if (serializeInst[tid]->seqNum <= squash_seq_num) { 352 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 353 resumeSerialize = true; 354 assert(serializeInst[tid]); 355 } else { 356 resumeSerialize = false; 357 toDecode->renameUnblock[tid] = 1; 358 359 serializeInst[tid] = NULL; 360 } 361 } 362 363 // Set the status to Squashing. 364 renameStatus[tid] = Squashing; 365 366 // Squash any instructions from decode. 367 for (int i=0; i<fromDecode->size; i++) { 368 if (fromDecode->insts[i]->threadNumber == tid && 369 fromDecode->insts[i]->seqNum > squash_seq_num) { 370 fromDecode->insts[i]->setSquashed(); 371 wroteToTimeBuffer = true; 372 } 373 374 } 375 376 // Clear the instruction list and skid buffer in case they have any 377 // insts in them. 378 insts[tid].clear(); 379 380 // Clear the skid buffer in case it has any data in it. 381 skidBuffer[tid].clear(); 382 383 doSquash(squash_seq_num, tid); 384} 385 386template <class Impl> 387void 388DefaultRename<Impl>::tick() 389{ 390 wroteToTimeBuffer = false; 391 392 blockThisCycle = false; 393 394 bool status_change = false; 395 396 toIEWIndex = 0; 397 398 sortInsts(); 399 400 list<ThreadID>::iterator threads = activeThreads->begin(); 401 list<ThreadID>::iterator end = activeThreads->end(); 402 403 // Check stall and squash signals. 404 while (threads != end) { 405 ThreadID tid = *threads++; 406 407 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 408 409 status_change = checkSignalsAndUpdate(tid) || status_change; 410 411 rename(status_change, tid); 412 } 413 414 if (status_change) { 415 updateStatus(); 416 } 417 418 if (wroteToTimeBuffer) { 419 DPRINTF(Activity, "Activity this cycle.\n"); 420 cpu->activityThisCycle(); 421 } 422 423 threads = activeThreads->begin(); 424 425 while (threads != end) { 426 ThreadID tid = *threads++; 427 428 // If we committed this cycle then doneSeqNum will be > 0 429 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 430 !fromCommit->commitInfo[tid].squash && 431 renameStatus[tid] != Squashing) { 432 433 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 434 tid); 435 } 436 } 437 438 // @todo: make into updateProgress function 439 for (ThreadID tid = 0; tid < numThreads; tid++) { 440 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 441 loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 442 storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 443 assert(loadsInProgress[tid] >= 0); 444 assert(storesInProgress[tid] >= 0); 445 assert(instsInProgress[tid] >=0); 446 } 447 448} 449 450template<class Impl> 451void 452DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 453{ 454 // If status is Running or idle, 455 // call renameInsts() 456 // If status is Unblocking, 457 // buffer any instructions coming from decode 458 // continue trying to empty skid buffer 459 // check if stall conditions have passed 460 461 if (renameStatus[tid] == Blocked) { 462 ++renameBlockCycles; 463 } else if (renameStatus[tid] == Squashing) { 464 ++renameSquashCycles; 465 } else if (renameStatus[tid] == SerializeStall) { 466 ++renameSerializeStallCycles; 467 // If we are currently in SerializeStall and resumeSerialize 468 // was set, then that means that we are resuming serializing 469 // this cycle. Tell the previous stages to block. 470 if (resumeSerialize) { 471 resumeSerialize = false; 472 block(tid); 473 toDecode->renameUnblock[tid] = false; 474 } 475 } else if (renameStatus[tid] == Unblocking) { 476 if (resumeUnblocking) { 477 block(tid); 478 resumeUnblocking = false; 479 toDecode->renameUnblock[tid] = false; 480 } 481 } 482 483 if (renameStatus[tid] == Running || 484 renameStatus[tid] == Idle) { 485 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 486 "stage.\n", tid); 487 488 renameInsts(tid); 489 } else if (renameStatus[tid] == Unblocking) { 490 renameInsts(tid); 491 492 if (validInsts()) { 493 // Add the current inputs to the skid buffer so they can be 494 // reprocessed when this stage unblocks. 495 skidInsert(tid); 496 } 497 498 // If we switched over to blocking, then there's a potential for 499 // an overall status change. 500 status_change = unblock(tid) || status_change || blockThisCycle; 501 } 502} 503 504template <class Impl> 505void 506DefaultRename<Impl>::renameInsts(ThreadID tid) 507{ 508 // Instructions can be either in the skid buffer or the queue of 509 // instructions coming from decode, depending on the status. 510 int insts_available = renameStatus[tid] == Unblocking ? 511 skidBuffer[tid].size() : insts[tid].size(); 512 513 // Check the decode queue to see if instructions are available. 514 // If there are no available instructions to rename, then do nothing. 515 if (insts_available == 0) { 516 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 517 tid); 518 // Should I change status to idle? 519 ++renameIdleCycles; 520 return; 521 } else if (renameStatus[tid] == Unblocking) { 522 ++renameUnblockCycles; 523 } else if (renameStatus[tid] == Running) { 524 ++renameRunCycles; 525 } 526 527 // Will have to do a different calculation for the number of free 528 // entries. 529 int free_rob_entries = calcFreeROBEntries(tid); 530 int free_iq_entries = calcFreeIQEntries(tid); 531 int min_free_entries = free_rob_entries; 532 533 FullSource source = ROB; 534 535 if (free_iq_entries < min_free_entries) { 536 min_free_entries = free_iq_entries; 537 source = IQ; 538 } 539 540 // Check if there's any space left. 541 if (min_free_entries <= 0) { 542 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 543 "entries.\n" 544 "ROB has %i free entries.\n" 545 "IQ has %i free entries.\n", 546 tid, 547 free_rob_entries, 548 free_iq_entries); 549 550 blockThisCycle = true; 551 552 block(tid); 553 554 incrFullStat(source); 555 556 return; 557 } else if (min_free_entries < insts_available) { 558 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 559 "%i insts available, but only %i insts can be " 560 "renamed due to ROB/IQ/LSQ limits.\n", 561 tid, insts_available, min_free_entries); 562 563 insts_available = min_free_entries; 564 565 blockThisCycle = true; 566 567 incrFullStat(source); 568 } 569 570 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 571 skidBuffer[tid] : insts[tid]; 572 573 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 574 "send iew.\n", tid, insts_available); 575 576 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 577 "dispatched to IQ last cycle.\n", 578 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 579 580 // Handle serializing the next instruction if necessary. 581 if (serializeOnNextInst[tid]) { 582 if (emptyROB[tid] && instsInProgress[tid] == 0) { 583 // ROB already empty; no need to serialize. 584 serializeOnNextInst[tid] = false; 585 } else if (!insts_to_rename.empty()) { 586 insts_to_rename.front()->setSerializeBefore(); 587 } 588 } 589 590 int renamed_insts = 0; 591 592 while (insts_available > 0 && toIEWIndex < renameWidth) { 593 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 594 595 assert(!insts_to_rename.empty()); 596 597 DynInstPtr inst = insts_to_rename.front(); 598 599 //For all kind of instructions, check ROB and IQ first 600 //For load instruction, check LQ size and take into account the inflight loads 601 //For store instruction, check SQ size and take into account the inflight stores 602 603 if (inst->isLoad()) { 604 if (calcFreeLQEntries(tid) <= 0) { 605 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 606 source = LQ; 607 incrFullStat(source); 608 break; 609 } 610 } 611 612 if (inst->isStore()) { 613 if (calcFreeSQEntries(tid) <= 0) { 614 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 615 source = SQ; 616 incrFullStat(source); 617 break; 618 } 619 } 620 621 insts_to_rename.pop_front(); 622 623 if (renameStatus[tid] == Unblocking) { 624 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 625 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 626 } 627 628 if (inst->isSquashed()) { 629 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 630 "squashed, skipping.\n", tid, inst->seqNum, 631 inst->pcState()); 632 633 ++renameSquashedInsts; 634 635 // Decrement how many instructions are available. 636 --insts_available; 637 638 continue; 639 } 640 641 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 642 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 643 644 // Check here to make sure there are enough destination registers 645 // to rename to. Otherwise block. 646 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 647 inst->numFPDestRegs(), 648 inst->numVecDestRegs(), 649 inst->numVecElemDestRegs(), 650 inst->numCCDestRegs())) { 651 DPRINTF(Rename, "Blocking due to lack of free " 652 "physical registers to rename to.\n"); 653 blockThisCycle = true; 654 insts_to_rename.push_front(inst); 655 ++renameFullRegistersEvents; 656 657 break; 658 } 659 660 // Handle serializeAfter/serializeBefore instructions. 661 // serializeAfter marks the next instruction as serializeBefore. 662 // serializeBefore makes the instruction wait in rename until the ROB 663 // is empty. 664 665 // In this model, IPR accesses are serialize before 666 // instructions, and store conditionals are serialize after 667 // instructions. This is mainly due to lack of support for 668 // out-of-order operations of either of those classes of 669 // instructions. 670 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 671 !inst->isSerializeHandled()) { 672 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 673 674 if (!inst->isTempSerializeBefore()) { 675 renamedSerializing++; 676 inst->setSerializeHandled(); 677 } else { 678 renamedTempSerializing++; 679 } 680 681 // Change status over to SerializeStall so that other stages know 682 // what this is blocked on. 683 renameStatus[tid] = SerializeStall; 684 685 serializeInst[tid] = inst; 686 687 blockThisCycle = true; 688 689 break; 690 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 691 !inst->isSerializeHandled()) { 692 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 693 694 renamedSerializing++; 695 696 inst->setSerializeHandled(); 697 698 serializeAfter(insts_to_rename, tid); 699 } 700 701 renameSrcRegs(inst, inst->threadNumber); 702 703 renameDestRegs(inst, inst->threadNumber); 704 705 if (inst->isLoad()) { 706 loadsInProgress[tid]++; 707 } 708 if (inst->isStore()) { 709 storesInProgress[tid]++; 710 } 711 ++renamed_insts; 712 // Notify potential listeners that source and destination registers for 713 // this instruction have been renamed. 714 ppRename->notify(inst); 715 716 // Put instruction in rename queue. 717 toIEW->insts[toIEWIndex] = inst; 718 ++(toIEW->size); 719 720 // Increment which instruction we're on. 721 ++toIEWIndex; 722 723 // Decrement how many instructions are available. 724 --insts_available; 725 } 726 727 instsInProgress[tid] += renamed_insts; 728 renameRenamedInsts += renamed_insts; 729 730 // If we wrote to the time buffer, record this. 731 if (toIEWIndex) { 732 wroteToTimeBuffer = true; 733 } 734 735 // Check if there's any instructions left that haven't yet been renamed. 736 // If so then block. 737 if (insts_available) { 738 blockThisCycle = true; 739 } 740 741 if (blockThisCycle) { 742 block(tid); 743 toDecode->renameUnblock[tid] = false; 744 } 745} 746 747template<class Impl> 748void 749DefaultRename<Impl>::skidInsert(ThreadID tid) 750{ 751 DynInstPtr inst = NULL; 752 753 while (!insts[tid].empty()) { 754 inst = insts[tid].front(); 755 756 insts[tid].pop_front(); 757 758 assert(tid == inst->threadNumber); 759 760 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 761 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 762 763 ++renameSkidInsts; 764 765 skidBuffer[tid].push_back(inst); 766 } 767 768 if (skidBuffer[tid].size() > skidBufferMax) 769 { 770 typename InstQueue::iterator it; 771 warn("Skidbuffer contents:\n"); 772 for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 773 { 774 warn("[tid:%u]: %s [sn:%i].\n", tid, 775 (*it)->staticInst->disassemble(inst->instAddr()), 776 (*it)->seqNum); 777 } 778 panic("Skidbuffer Exceeded Max Size"); 779 } 780} 781 782template <class Impl> 783void 784DefaultRename<Impl>::sortInsts() 785{ 786 int insts_from_decode = fromDecode->size; 787 for (int i = 0; i < insts_from_decode; ++i) { 788 const DynInstPtr &inst = fromDecode->insts[i]; 789 insts[inst->threadNumber].push_back(inst); 790#if TRACING_ON 791 if (DTRACE(O3PipeView)) { 792 inst->renameTick = curTick() - inst->fetchTick; 793 } 794#endif 795 } 796} 797 798template<class Impl> 799bool 800DefaultRename<Impl>::skidsEmpty() 801{ 802 list<ThreadID>::iterator threads = activeThreads->begin(); 803 list<ThreadID>::iterator end = activeThreads->end(); 804 805 while (threads != end) { 806 ThreadID tid = *threads++; 807 808 if (!skidBuffer[tid].empty()) 809 return false; 810 } 811 812 return true; 813} 814 815template<class Impl> 816void 817DefaultRename<Impl>::updateStatus() 818{ 819 bool any_unblocking = false; 820 821 list<ThreadID>::iterator threads = activeThreads->begin(); 822 list<ThreadID>::iterator end = activeThreads->end(); 823 824 while (threads != end) { 825 ThreadID tid = *threads++; 826 827 if (renameStatus[tid] == Unblocking) { 828 any_unblocking = true; 829 break; 830 } 831 } 832 833 // Rename will have activity if it's unblocking. 834 if (any_unblocking) { 835 if (_status == Inactive) { 836 _status = Active; 837 838 DPRINTF(Activity, "Activating stage.\n"); 839 840 cpu->activateStage(O3CPU::RenameIdx); 841 } 842 } else { 843 // If it's not unblocking, then rename will not have any internal 844 // activity. Switch it to inactive. 845 if (_status == Active) { 846 _status = Inactive; 847 DPRINTF(Activity, "Deactivating stage.\n"); 848 849 cpu->deactivateStage(O3CPU::RenameIdx); 850 } 851 } 852} 853 854template <class Impl> 855bool 856DefaultRename<Impl>::block(ThreadID tid) 857{ 858 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 859 860 // Add the current inputs onto the skid buffer, so they can be 861 // reprocessed when this stage unblocks. 862 skidInsert(tid); 863 864 // Only signal backwards to block if the previous stages do not think 865 // rename is already blocked. 866 if (renameStatus[tid] != Blocked) { 867 // If resumeUnblocking is set, we unblocked during the squash, 868 // but now we're have unblocking status. We need to tell earlier 869 // stages to block. 870 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 871 toDecode->renameBlock[tid] = true; 872 toDecode->renameUnblock[tid] = false; 873 wroteToTimeBuffer = true; 874 } 875 876 // Rename can not go from SerializeStall to Blocked, otherwise 877 // it would not know to complete the serialize stall. 878 if (renameStatus[tid] != SerializeStall) { 879 // Set status to Blocked. 880 renameStatus[tid] = Blocked; 881 return true; 882 } 883 } 884 885 return false; 886} 887 888template <class Impl> 889bool 890DefaultRename<Impl>::unblock(ThreadID tid) 891{ 892 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 893 894 // Rename is done unblocking if the skid buffer is empty. 895 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 896 897 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 898 899 toDecode->renameUnblock[tid] = true; 900 wroteToTimeBuffer = true; 901 902 renameStatus[tid] = Running; 903 return true; 904 } 905 906 return false; 907} 908 909template <class Impl> 910void 911DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 912{ 913 typename std::list<RenameHistory>::iterator hb_it = 914 historyBuffer[tid].begin(); 915 916 // After a syscall squashes everything, the history buffer may be empty 917 // but the ROB may still be squashing instructions. 918 if (historyBuffer[tid].empty()) { 919 return; 920 } 921 922 // Go through the most recent instructions, undoing the mappings 923 // they did and freeing up the registers. 924 while (!historyBuffer[tid].empty() && 925 hb_it->instSeqNum > squashed_seq_num) { 926 assert(hb_it != historyBuffer[tid].end()); 927 928 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 929 "number %i.\n", tid, hb_it->instSeqNum); 930 931 // Undo the rename mapping only if it was really a change. 932 // Special regs that are not really renamed (like misc regs 933 // and the zero reg) can be recognized because the new mapping 934 // is the same as the old one. While it would be merely a 935 // waste of time to update the rename table, we definitely 936 // don't want to put these on the free list. 937 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 938 // Tell the rename map to set the architected register to the 939 // previous physical register that it was renamed to. 940 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 941 942 // Put the renamed physical register back on the free list. 943 freeList->addReg(hb_it->newPhysReg); 944 } 945 946 // Notify potential listeners that the register mapping needs to be 947 // removed because the instruction it was mapped to got squashed. Note 948 // that this is done before hb_it is incremented. 949 ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 950 hb_it->newPhysReg)); 951 952 historyBuffer[tid].erase(hb_it++); 953 954 ++renameUndoneMaps; 955 } 956} 957 958template<class Impl> 959void 960DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 961{ 962 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 963 "history buffer %u (size=%i), until [sn:%lli].\n", 964 tid, tid, historyBuffer[tid].size(), inst_seq_num); 965 966 typename std::list<RenameHistory>::iterator hb_it = 967 historyBuffer[tid].end(); 968 969 --hb_it; 970 971 if (historyBuffer[tid].empty()) { 972 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 973 return; 974 } else if (hb_it->instSeqNum > inst_seq_num) { 975 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 976 "that a syscall happened recently.\n", tid); 977 return; 978 } 979 980 // Commit all the renames up until (and including) the committed sequence 981 // number. Some or even all of the committed instructions may not have 982 // rename histories if they did not have destination registers that were 983 // renamed. 984 while (!historyBuffer[tid].empty() && 985 hb_it != historyBuffer[tid].end() && 986 hb_it->instSeqNum <= inst_seq_num) { 987 988 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 989 "[sn:%lli].\n", 990 tid, hb_it->prevPhysReg->index(), 991 hb_it->prevPhysReg->className(), 992 hb_it->instSeqNum); 993 994 // Don't free special phys regs like misc and zero regs, which 995 // can be recognized because the new mapping is the same as 996 // the old one. 997 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 998 freeList->addReg(hb_it->prevPhysReg); 999 } 1000 1001 ++renameCommittedMaps; 1002 1003 historyBuffer[tid].erase(hb_it--); 1004 } 1005} 1006 1007template <class Impl> 1008inline void 1009DefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid) 1010{ 1011 ThreadContext *tc = inst->tcBase(); 1012 RenameMap *map = renameMap[tid]; 1013 unsigned num_src_regs = inst->numSrcRegs(); 1014 1015 // Get the architectual register numbers from the source and 1016 // operands, and redirect them to the right physical register. 1017 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1018 const RegId& src_reg = inst->srcRegIdx(src_idx); 1019 PhysRegIdPtr renamed_reg; 1020 1021 renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 1022 switch (src_reg.classValue()) { 1023 case IntRegClass: 1024 intRenameLookups++; 1025 break; 1026 case FloatRegClass: 1027 fpRenameLookups++; 1028 break; 1029 case VecRegClass: 1030 vecRenameLookups++; 1031 break; 1032 case CCRegClass: 1033 case MiscRegClass: 1034 break; 1035 1036 default: 1037 panic("Invalid register class: %d.", src_reg.classValue()); 1038 } 1039 1040 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 1041 ", got phys reg %i (%s)\n", tid, 1042 src_reg.className(), src_reg.index(), 1043 renamed_reg->index(), 1044 renamed_reg->className()); 1045 1046 inst->renameSrcReg(src_idx, renamed_reg); 1047 1048 // See if the register is ready or not. 1049 if (scoreboard->getReg(renamed_reg)) { 1050 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1051 " is ready.\n", tid, renamed_reg->index(), 1052 renamed_reg->flatIndex(), 1053 renamed_reg->className()); 1054 1055 inst->markSrcRegReady(src_idx); 1056 } else { 1057 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1058 " is not ready.\n", tid, renamed_reg->index(), 1059 renamed_reg->flatIndex(), 1060 renamed_reg->className()); 1061 } 1062 1063 ++renameRenameLookups; 1064 } 1065} 1066 1067template <class Impl> 1068inline void 1069DefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid) 1070{ 1071 ThreadContext *tc = inst->tcBase(); 1072 RenameMap *map = renameMap[tid]; 1073 unsigned num_dest_regs = inst->numDestRegs(); 1074 1075 // Rename the destination registers. 1076 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1077 const RegId& dest_reg = inst->destRegIdx(dest_idx); 1078 typename RenameMap::RenameInfo rename_result; 1079 1080 RegId flat_dest_regid = tc->flattenRegId(dest_reg); 1081 1082 rename_result = map->rename(flat_dest_regid); 1083 1084 inst->flattenDestReg(dest_idx, flat_dest_regid); 1085 1086 // Mark Scoreboard entry as not ready 1087 scoreboard->unsetReg(rename_result.first); 1088 1089 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 1090 "reg %i (%i).\n", tid, dest_reg.index(), 1091 dest_reg.className(), 1092 rename_result.first->index(), 1093 rename_result.first->flatIndex()); 1094 1095 // Record the rename information so that a history can be kept. 1096 RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 1097 rename_result.first, 1098 rename_result.second); 1099 1100 historyBuffer[tid].push_front(hb_entry); 1101 1102 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1103 "(size=%i), [sn:%lli].\n",tid, 1104 historyBuffer[tid].size(), 1105 (*historyBuffer[tid].begin()).instSeqNum); 1106 1107 // Tell the instruction to rename the appropriate destination 1108 // register (dest_idx) to the new physical register 1109 // (rename_result.first), and record the previous physical 1110 // register that the same logical register was renamed to 1111 // (rename_result.second). 1112 inst->renameDestReg(dest_idx, 1113 rename_result.first, 1114 rename_result.second); 1115 1116 ++renameRenamedOperands; 1117 } 1118} 1119 1120template <class Impl> 1121inline int 1122DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1123{ 1124 int num_free = freeEntries[tid].robEntries - 1125 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1126 1127 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1128 1129 return num_free; 1130} 1131 1132template <class Impl> 1133inline int 1134DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1135{ 1136 int num_free = freeEntries[tid].iqEntries - 1137 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1138 1139 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1140 1141 return num_free; 1142} 1143 1144template <class Impl> 1145inline int 1146DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1147{ 1148 int num_free = freeEntries[tid].lqEntries - 1149 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1150 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1151 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1152 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1153 return num_free; 1154} 1155 1156template <class Impl> 1157inline int 1158DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1159{ 1160 int num_free = freeEntries[tid].sqEntries - 1161 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1162 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1163 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1164 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1165 return num_free; 1166} 1167 1168template <class Impl> 1169unsigned 1170DefaultRename<Impl>::validInsts() 1171{ 1172 unsigned inst_count = 0; 1173 1174 for (int i=0; i<fromDecode->size; i++) { 1175 if (!fromDecode->insts[i]->isSquashed()) 1176 inst_count++; 1177 } 1178 1179 return inst_count; 1180} 1181 1182template <class Impl> 1183void 1184DefaultRename<Impl>::readStallSignals(ThreadID tid) 1185{ 1186 if (fromIEW->iewBlock[tid]) { 1187 stalls[tid].iew = true; 1188 } 1189 1190 if (fromIEW->iewUnblock[tid]) { 1191 assert(stalls[tid].iew); 1192 stalls[tid].iew = false; 1193 } 1194} 1195 1196template <class Impl> 1197bool 1198DefaultRename<Impl>::checkStall(ThreadID tid) 1199{ 1200 bool ret_val = false; 1201 1202 if (stalls[tid].iew) { 1203 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1204 ret_val = true; 1205 } else if (calcFreeROBEntries(tid) <= 0) { 1206 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1207 ret_val = true; 1208 } else if (calcFreeIQEntries(tid) <= 0) { 1209 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1210 ret_val = true; 1211 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 1212 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1213 ret_val = true; 1214 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1215 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1216 ret_val = true; 1217 } else if (renameStatus[tid] == SerializeStall && 1218 (!emptyROB[tid] || instsInProgress[tid])) { 1219 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1220 "empty.\n", 1221 tid); 1222 ret_val = true; 1223 } 1224 1225 return ret_val; 1226} 1227 1228template <class Impl> 1229void 1230DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1231{ 1232 if (fromIEW->iewInfo[tid].usedIQ) 1233 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1234 1235 if (fromIEW->iewInfo[tid].usedLSQ) { 1236 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1237 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1238 } 1239 1240 if (fromCommit->commitInfo[tid].usedROB) { 1241 freeEntries[tid].robEntries = 1242 fromCommit->commitInfo[tid].freeROBEntries; 1243 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1244 } 1245 1246 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1247 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n", 1248 tid, 1249 freeEntries[tid].iqEntries, 1250 freeEntries[tid].robEntries, 1251 freeEntries[tid].lqEntries, 1252 freeEntries[tid].sqEntries, 1253 renameMap[tid]->numFreeEntries(), 1254 renameMap[tid]->numFreeIntEntries(), 1255 renameMap[tid]->numFreeFloatEntries(), 1256 renameMap[tid]->numFreeVecEntries(), 1257 renameMap[tid]->numFreeCCEntries()); 1258 1259 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1260 tid, instsInProgress[tid]); 1261} 1262 1263template <class Impl> 1264bool 1265DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1266{ 1267 // Check if there's a squash signal, squash if there is 1268 // Check stall signals, block if necessary. 1269 // If status was blocked 1270 // check if stall conditions have passed 1271 // if so then go to unblocking 1272 // If status was Squashing 1273 // check if squashing is not high. Switch to running this cycle. 1274 // If status was serialize stall 1275 // check if ROB is empty and no insts are in flight to the ROB 1276 1277 readFreeEntries(tid); 1278 readStallSignals(tid); 1279 1280 if (fromCommit->commitInfo[tid].squash) { 1281 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1282 "commit.\n", tid); 1283 1284 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1285 1286 return true; 1287 } 1288 1289 if (checkStall(tid)) { 1290 return block(tid); 1291 } 1292 1293 if (renameStatus[tid] == Blocked) { 1294 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1295 tid); 1296 1297 renameStatus[tid] = Unblocking; 1298 1299 unblock(tid); 1300 1301 return true; 1302 } 1303 1304 if (renameStatus[tid] == Squashing) { 1305 // Switch status to running if rename isn't being told to block or 1306 // squash this cycle. 1307 if (resumeSerialize) { 1308 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1309 tid); 1310 1311 renameStatus[tid] = SerializeStall; 1312 return true; 1313 } else if (resumeUnblocking) { 1314 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1315 tid); 1316 renameStatus[tid] = Unblocking; 1317 return true; 1318 } else { 1319 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1320 tid); 1321 1322 renameStatus[tid] = Running; 1323 return false; 1324 } 1325 } 1326 1327 if (renameStatus[tid] == SerializeStall) { 1328 // Stall ends once the ROB is free. 1329 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1330 "unblocking.\n", tid); 1331 1332 DynInstPtr serial_inst = serializeInst[tid]; 1333 1334 renameStatus[tid] = Unblocking; 1335 1336 unblock(tid); 1337 1338 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1339 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1340 1341 // Put instruction into queue here. 1342 serial_inst->clearSerializeBefore(); 1343 1344 if (!skidBuffer[tid].empty()) { 1345 skidBuffer[tid].push_front(serial_inst); 1346 } else { 1347 insts[tid].push_front(serial_inst); 1348 } 1349 1350 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1351 " Adding to front of list.\n", tid); 1352 1353 serializeInst[tid] = NULL; 1354 1355 return true; 1356 } 1357 1358 // If we've reached this point, we have not gotten any signals that 1359 // cause rename to change its status. Rename remains the same as before. 1360 return false; 1361} 1362 1363template<class Impl> 1364void 1365DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1366{ 1367 if (inst_list.empty()) { 1368 // Mark a bit to say that I must serialize on the next instruction. 1369 serializeOnNextInst[tid] = true; 1370 return; 1371 } 1372 1373 // Set the next instruction as serializing. 1374 inst_list.front()->setSerializeBefore(); 1375} 1376 1377template <class Impl> 1378inline void 1379DefaultRename<Impl>::incrFullStat(const FullSource &source) 1380{ 1381 switch (source) { 1382 case ROB: 1383 ++renameROBFullEvents; 1384 break; 1385 case IQ: 1386 ++renameIQFullEvents; 1387 break; 1388 case LQ: 1389 ++renameLQFullEvents; 1390 break; 1391 case SQ: 1392 ++renameSQFullEvents; 1393 break; 1394 default: 1395 panic("Rename full stall stat should be incremented for a reason!"); 1396 break; 1397 } 1398} 1399 1400template <class Impl> 1401void 1402DefaultRename<Impl>::dumpHistory() 1403{ 1404 typename std::list<RenameHistory>::iterator buf_it; 1405 1406 for (ThreadID tid = 0; tid < numThreads; tid++) { 1407 1408 buf_it = historyBuffer[tid].begin(); 1409 1410 while (buf_it != historyBuffer[tid].end()) { 1411 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 1412 " %i[%s] Old phys reg: %i[%s]\n", 1413 (*buf_it).instSeqNum, 1414 (*buf_it).archReg.className(), 1415 (*buf_it).archReg.index(), 1416 (*buf_it).newPhysReg->index(), 1417 (*buf_it).newPhysReg->className(), 1418 (*buf_it).prevPhysReg->index(), 1419 (*buf_it).prevPhysReg->className()); 1420 1421 buf_it++; 1422 } 1423 } 1424} 1425 1426#endif//__CPU_O3_RENAME_IMPL_HH__ 1427