rename_impl.hh revision 12106:7784fac1b159
1/* 2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_RENAME_IMPL_HH__ 46#define __CPU_O3_RENAME_IMPL_HH__ 47 48#include <list> 49 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "config/the_isa.hh" 53#include "cpu/o3/rename.hh" 54#include "cpu/reg_class.hh" 55#include "debug/Activity.hh" 56#include "debug/Rename.hh" 57#include "debug/O3PipeView.hh" 58#include "params/DerivO3CPU.hh" 59 60using namespace std; 61 62template <class Impl> 63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 64 : cpu(_cpu), 65 iewToRenameDelay(params->iewToRenameDelay), 66 decodeToRenameDelay(params->decodeToRenameDelay), 67 commitToRenameDelay(params->commitToRenameDelay), 68 renameWidth(params->renameWidth), 69 commitWidth(params->commitWidth), 70 numThreads(params->numThreads), 71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 72 + params->numPhysCCRegs) 73{ 74 if (renameWidth > Impl::MaxWidth) 75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 77 renameWidth, static_cast<int>(Impl::MaxWidth)); 78 79 // @todo: Make into a parameter. 80 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 81} 82 83template <class Impl> 84std::string 85DefaultRename<Impl>::name() const 86{ 87 return cpu->name() + ".rename"; 88} 89 90template <class Impl> 91void 92DefaultRename<Impl>::regStats() 93{ 94 renameSquashCycles 95 .name(name() + ".SquashCycles") 96 .desc("Number of cycles rename is squashing") 97 .prereq(renameSquashCycles); 98 renameIdleCycles 99 .name(name() + ".IdleCycles") 100 .desc("Number of cycles rename is idle") 101 .prereq(renameIdleCycles); 102 renameBlockCycles 103 .name(name() + ".BlockCycles") 104 .desc("Number of cycles rename is blocking") 105 .prereq(renameBlockCycles); 106 renameSerializeStallCycles 107 .name(name() + ".serializeStallCycles") 108 .desc("count of cycles rename stalled for serializing inst") 109 .flags(Stats::total); 110 renameRunCycles 111 .name(name() + ".RunCycles") 112 .desc("Number of cycles rename is running") 113 .prereq(renameIdleCycles); 114 renameUnblockCycles 115 .name(name() + ".UnblockCycles") 116 .desc("Number of cycles rename is unblocking") 117 .prereq(renameUnblockCycles); 118 renameRenamedInsts 119 .name(name() + ".RenamedInsts") 120 .desc("Number of instructions processed by rename") 121 .prereq(renameRenamedInsts); 122 renameSquashedInsts 123 .name(name() + ".SquashedInsts") 124 .desc("Number of squashed instructions processed by rename") 125 .prereq(renameSquashedInsts); 126 renameROBFullEvents 127 .name(name() + ".ROBFullEvents") 128 .desc("Number of times rename has blocked due to ROB full") 129 .prereq(renameROBFullEvents); 130 renameIQFullEvents 131 .name(name() + ".IQFullEvents") 132 .desc("Number of times rename has blocked due to IQ full") 133 .prereq(renameIQFullEvents); 134 renameLQFullEvents 135 .name(name() + ".LQFullEvents") 136 .desc("Number of times rename has blocked due to LQ full") 137 .prereq(renameLQFullEvents); 138 renameSQFullEvents 139 .name(name() + ".SQFullEvents") 140 .desc("Number of times rename has blocked due to SQ full") 141 .prereq(renameSQFullEvents); 142 renameFullRegistersEvents 143 .name(name() + ".FullRegisterEvents") 144 .desc("Number of times there has been no free registers") 145 .prereq(renameFullRegistersEvents); 146 renameRenamedOperands 147 .name(name() + ".RenamedOperands") 148 .desc("Number of destination operands rename has renamed") 149 .prereq(renameRenamedOperands); 150 renameRenameLookups 151 .name(name() + ".RenameLookups") 152 .desc("Number of register rename lookups that rename has made") 153 .prereq(renameRenameLookups); 154 renameCommittedMaps 155 .name(name() + ".CommittedMaps") 156 .desc("Number of HB maps that are committed") 157 .prereq(renameCommittedMaps); 158 renameUndoneMaps 159 .name(name() + ".UndoneMaps") 160 .desc("Number of HB maps that are undone due to squashing") 161 .prereq(renameUndoneMaps); 162 renamedSerializing 163 .name(name() + ".serializingInsts") 164 .desc("count of serializing insts renamed") 165 .flags(Stats::total) 166 ; 167 renamedTempSerializing 168 .name(name() + ".tempSerializingInsts") 169 .desc("count of temporary serializing insts renamed") 170 .flags(Stats::total) 171 ; 172 renameSkidInsts 173 .name(name() + ".skidInsts") 174 .desc("count of insts added to the skid buffer") 175 .flags(Stats::total) 176 ; 177 intRenameLookups 178 .name(name() + ".int_rename_lookups") 179 .desc("Number of integer rename lookups") 180 .prereq(intRenameLookups); 181 fpRenameLookups 182 .name(name() + ".fp_rename_lookups") 183 .desc("Number of floating rename lookups") 184 .prereq(fpRenameLookups); 185} 186 187template <class Impl> 188void 189DefaultRename<Impl>::regProbePoints() 190{ 191 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 192 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 193 "SquashInRename"); 194} 195 196template <class Impl> 197void 198DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 199{ 200 timeBuffer = tb_ptr; 201 202 // Setup wire to read information from time buffer, from IEW stage. 203 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 204 205 // Setup wire to read infromation from time buffer, from commit stage. 206 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 207 208 // Setup wire to write information to previous stages. 209 toDecode = timeBuffer->getWire(0); 210} 211 212template <class Impl> 213void 214DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 215{ 216 renameQueue = rq_ptr; 217 218 // Setup wire to write information to future stages. 219 toIEW = renameQueue->getWire(0); 220} 221 222template <class Impl> 223void 224DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 225{ 226 decodeQueue = dq_ptr; 227 228 // Setup wire to get information from decode. 229 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 230} 231 232template <class Impl> 233void 234DefaultRename<Impl>::startupStage() 235{ 236 resetStage(); 237} 238 239template <class Impl> 240void 241DefaultRename<Impl>::resetStage() 242{ 243 _status = Inactive; 244 245 resumeSerialize = false; 246 resumeUnblocking = false; 247 248 // Grab the number of free entries directly from the stages. 249 for (ThreadID tid = 0; tid < numThreads; tid++) { 250 renameStatus[tid] = Idle; 251 252 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 253 freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 254 freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 255 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 256 emptyROB[tid] = true; 257 258 stalls[tid].iew = false; 259 serializeInst[tid] = NULL; 260 261 instsInProgress[tid] = 0; 262 loadsInProgress[tid] = 0; 263 storesInProgress[tid] = 0; 264 265 serializeOnNextInst[tid] = false; 266 } 267} 268 269template<class Impl> 270void 271DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 272{ 273 activeThreads = at_ptr; 274} 275 276 277template <class Impl> 278void 279DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 280{ 281 for (ThreadID tid = 0; tid < numThreads; tid++) 282 renameMap[tid] = &rm_ptr[tid]; 283} 284 285template <class Impl> 286void 287DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 288{ 289 freeList = fl_ptr; 290} 291 292template<class Impl> 293void 294DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 295{ 296 scoreboard = _scoreboard; 297} 298 299template <class Impl> 300bool 301DefaultRename<Impl>::isDrained() const 302{ 303 for (ThreadID tid = 0; tid < numThreads; tid++) { 304 if (instsInProgress[tid] != 0 || 305 !historyBuffer[tid].empty() || 306 !skidBuffer[tid].empty() || 307 !insts[tid].empty() || 308 (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 309 return false; 310 } 311 return true; 312} 313 314template <class Impl> 315void 316DefaultRename<Impl>::takeOverFrom() 317{ 318 resetStage(); 319} 320 321template <class Impl> 322void 323DefaultRename<Impl>::drainSanityCheck() const 324{ 325 for (ThreadID tid = 0; tid < numThreads; tid++) { 326 assert(historyBuffer[tid].empty()); 327 assert(insts[tid].empty()); 328 assert(skidBuffer[tid].empty()); 329 assert(instsInProgress[tid] == 0); 330 } 331} 332 333template <class Impl> 334void 335DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 336{ 337 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 338 339 // Clear the stall signal if rename was blocked or unblocking before. 340 // If it still needs to block, the blocking should happen the next 341 // cycle and there should be space to hold everything due to the squash. 342 if (renameStatus[tid] == Blocked || 343 renameStatus[tid] == Unblocking) { 344 toDecode->renameUnblock[tid] = 1; 345 346 resumeSerialize = false; 347 serializeInst[tid] = NULL; 348 } else if (renameStatus[tid] == SerializeStall) { 349 if (serializeInst[tid]->seqNum <= squash_seq_num) { 350 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 351 resumeSerialize = true; 352 assert(serializeInst[tid]); 353 } else { 354 resumeSerialize = false; 355 toDecode->renameUnblock[tid] = 1; 356 357 serializeInst[tid] = NULL; 358 } 359 } 360 361 // Set the status to Squashing. 362 renameStatus[tid] = Squashing; 363 364 // Squash any instructions from decode. 365 for (int i=0; i<fromDecode->size; i++) { 366 if (fromDecode->insts[i]->threadNumber == tid && 367 fromDecode->insts[i]->seqNum > squash_seq_num) { 368 fromDecode->insts[i]->setSquashed(); 369 wroteToTimeBuffer = true; 370 } 371 372 } 373 374 // Clear the instruction list and skid buffer in case they have any 375 // insts in them. 376 insts[tid].clear(); 377 378 // Clear the skid buffer in case it has any data in it. 379 skidBuffer[tid].clear(); 380 381 doSquash(squash_seq_num, tid); 382} 383 384template <class Impl> 385void 386DefaultRename<Impl>::tick() 387{ 388 wroteToTimeBuffer = false; 389 390 blockThisCycle = false; 391 392 bool status_change = false; 393 394 toIEWIndex = 0; 395 396 sortInsts(); 397 398 list<ThreadID>::iterator threads = activeThreads->begin(); 399 list<ThreadID>::iterator end = activeThreads->end(); 400 401 // Check stall and squash signals. 402 while (threads != end) { 403 ThreadID tid = *threads++; 404 405 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 406 407 status_change = checkSignalsAndUpdate(tid) || status_change; 408 409 rename(status_change, tid); 410 } 411 412 if (status_change) { 413 updateStatus(); 414 } 415 416 if (wroteToTimeBuffer) { 417 DPRINTF(Activity, "Activity this cycle.\n"); 418 cpu->activityThisCycle(); 419 } 420 421 threads = activeThreads->begin(); 422 423 while (threads != end) { 424 ThreadID tid = *threads++; 425 426 // If we committed this cycle then doneSeqNum will be > 0 427 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 428 !fromCommit->commitInfo[tid].squash && 429 renameStatus[tid] != Squashing) { 430 431 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 432 tid); 433 } 434 } 435 436 // @todo: make into updateProgress function 437 for (ThreadID tid = 0; tid < numThreads; tid++) { 438 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 439 loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 440 storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 441 assert(loadsInProgress[tid] >= 0); 442 assert(storesInProgress[tid] >= 0); 443 assert(instsInProgress[tid] >=0); 444 } 445 446} 447 448template<class Impl> 449void 450DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 451{ 452 // If status is Running or idle, 453 // call renameInsts() 454 // If status is Unblocking, 455 // buffer any instructions coming from decode 456 // continue trying to empty skid buffer 457 // check if stall conditions have passed 458 459 if (renameStatus[tid] == Blocked) { 460 ++renameBlockCycles; 461 } else if (renameStatus[tid] == Squashing) { 462 ++renameSquashCycles; 463 } else if (renameStatus[tid] == SerializeStall) { 464 ++renameSerializeStallCycles; 465 // If we are currently in SerializeStall and resumeSerialize 466 // was set, then that means that we are resuming serializing 467 // this cycle. Tell the previous stages to block. 468 if (resumeSerialize) { 469 resumeSerialize = false; 470 block(tid); 471 toDecode->renameUnblock[tid] = false; 472 } 473 } else if (renameStatus[tid] == Unblocking) { 474 if (resumeUnblocking) { 475 block(tid); 476 resumeUnblocking = false; 477 toDecode->renameUnblock[tid] = false; 478 } 479 } 480 481 if (renameStatus[tid] == Running || 482 renameStatus[tid] == Idle) { 483 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 484 "stage.\n", tid); 485 486 renameInsts(tid); 487 } else if (renameStatus[tid] == Unblocking) { 488 renameInsts(tid); 489 490 if (validInsts()) { 491 // Add the current inputs to the skid buffer so they can be 492 // reprocessed when this stage unblocks. 493 skidInsert(tid); 494 } 495 496 // If we switched over to blocking, then there's a potential for 497 // an overall status change. 498 status_change = unblock(tid) || status_change || blockThisCycle; 499 } 500} 501 502template <class Impl> 503void 504DefaultRename<Impl>::renameInsts(ThreadID tid) 505{ 506 // Instructions can be either in the skid buffer or the queue of 507 // instructions coming from decode, depending on the status. 508 int insts_available = renameStatus[tid] == Unblocking ? 509 skidBuffer[tid].size() : insts[tid].size(); 510 511 // Check the decode queue to see if instructions are available. 512 // If there are no available instructions to rename, then do nothing. 513 if (insts_available == 0) { 514 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 515 tid); 516 // Should I change status to idle? 517 ++renameIdleCycles; 518 return; 519 } else if (renameStatus[tid] == Unblocking) { 520 ++renameUnblockCycles; 521 } else if (renameStatus[tid] == Running) { 522 ++renameRunCycles; 523 } 524 525 DynInstPtr inst; 526 527 // Will have to do a different calculation for the number of free 528 // entries. 529 int free_rob_entries = calcFreeROBEntries(tid); 530 int free_iq_entries = calcFreeIQEntries(tid); 531 int min_free_entries = free_rob_entries; 532 533 FullSource source = ROB; 534 535 if (free_iq_entries < min_free_entries) { 536 min_free_entries = free_iq_entries; 537 source = IQ; 538 } 539 540 // Check if there's any space left. 541 if (min_free_entries <= 0) { 542 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 543 "entries.\n" 544 "ROB has %i free entries.\n" 545 "IQ has %i free entries.\n", 546 tid, 547 free_rob_entries, 548 free_iq_entries); 549 550 blockThisCycle = true; 551 552 block(tid); 553 554 incrFullStat(source); 555 556 return; 557 } else if (min_free_entries < insts_available) { 558 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 559 "%i insts available, but only %i insts can be " 560 "renamed due to ROB/IQ/LSQ limits.\n", 561 tid, insts_available, min_free_entries); 562 563 insts_available = min_free_entries; 564 565 blockThisCycle = true; 566 567 incrFullStat(source); 568 } 569 570 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 571 skidBuffer[tid] : insts[tid]; 572 573 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 574 "send iew.\n", tid, insts_available); 575 576 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 577 "dispatched to IQ last cycle.\n", 578 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 579 580 // Handle serializing the next instruction if necessary. 581 if (serializeOnNextInst[tid]) { 582 if (emptyROB[tid] && instsInProgress[tid] == 0) { 583 // ROB already empty; no need to serialize. 584 serializeOnNextInst[tid] = false; 585 } else if (!insts_to_rename.empty()) { 586 insts_to_rename.front()->setSerializeBefore(); 587 } 588 } 589 590 int renamed_insts = 0; 591 592 while (insts_available > 0 && toIEWIndex < renameWidth) { 593 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 594 595 assert(!insts_to_rename.empty()); 596 597 inst = insts_to_rename.front(); 598 599 //For all kind of instructions, check ROB and IQ first 600 //For load instruction, check LQ size and take into account the inflight loads 601 //For store instruction, check SQ size and take into account the inflight stores 602 603 if (inst->isLoad()) { 604 if (calcFreeLQEntries(tid) <= 0) { 605 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 606 source = LQ; 607 incrFullStat(source); 608 break; 609 } 610 } 611 612 if (inst->isStore()) { 613 if (calcFreeSQEntries(tid) <= 0) { 614 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 615 source = SQ; 616 incrFullStat(source); 617 break; 618 } 619 } 620 621 insts_to_rename.pop_front(); 622 623 if (renameStatus[tid] == Unblocking) { 624 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 625 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 626 } 627 628 if (inst->isSquashed()) { 629 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 630 "squashed, skipping.\n", tid, inst->seqNum, 631 inst->pcState()); 632 633 ++renameSquashedInsts; 634 635 // Decrement how many instructions are available. 636 --insts_available; 637 638 continue; 639 } 640 641 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 642 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 643 644 // Check here to make sure there are enough destination registers 645 // to rename to. Otherwise block. 646 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 647 inst->numFPDestRegs(), 648 inst->numCCDestRegs())) { 649 DPRINTF(Rename, "Blocking due to lack of free " 650 "physical registers to rename to.\n"); 651 blockThisCycle = true; 652 insts_to_rename.push_front(inst); 653 ++renameFullRegistersEvents; 654 655 break; 656 } 657 658 // Handle serializeAfter/serializeBefore instructions. 659 // serializeAfter marks the next instruction as serializeBefore. 660 // serializeBefore makes the instruction wait in rename until the ROB 661 // is empty. 662 663 // In this model, IPR accesses are serialize before 664 // instructions, and store conditionals are serialize after 665 // instructions. This is mainly due to lack of support for 666 // out-of-order operations of either of those classes of 667 // instructions. 668 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 669 !inst->isSerializeHandled()) { 670 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 671 672 if (!inst->isTempSerializeBefore()) { 673 renamedSerializing++; 674 inst->setSerializeHandled(); 675 } else { 676 renamedTempSerializing++; 677 } 678 679 // Change status over to SerializeStall so that other stages know 680 // what this is blocked on. 681 renameStatus[tid] = SerializeStall; 682 683 serializeInst[tid] = inst; 684 685 blockThisCycle = true; 686 687 break; 688 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 689 !inst->isSerializeHandled()) { 690 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 691 692 renamedSerializing++; 693 694 inst->setSerializeHandled(); 695 696 serializeAfter(insts_to_rename, tid); 697 } 698 699 renameSrcRegs(inst, inst->threadNumber); 700 701 renameDestRegs(inst, inst->threadNumber); 702 703 if (inst->isLoad()) { 704 loadsInProgress[tid]++; 705 } 706 if (inst->isStore()) { 707 storesInProgress[tid]++; 708 } 709 ++renamed_insts; 710 // Notify potential listeners that source and destination registers for 711 // this instruction have been renamed. 712 ppRename->notify(inst); 713 714 // Put instruction in rename queue. 715 toIEW->insts[toIEWIndex] = inst; 716 ++(toIEW->size); 717 718 // Increment which instruction we're on. 719 ++toIEWIndex; 720 721 // Decrement how many instructions are available. 722 --insts_available; 723 } 724 725 instsInProgress[tid] += renamed_insts; 726 renameRenamedInsts += renamed_insts; 727 728 // If we wrote to the time buffer, record this. 729 if (toIEWIndex) { 730 wroteToTimeBuffer = true; 731 } 732 733 // Check if there's any instructions left that haven't yet been renamed. 734 // If so then block. 735 if (insts_available) { 736 blockThisCycle = true; 737 } 738 739 if (blockThisCycle) { 740 block(tid); 741 toDecode->renameUnblock[tid] = false; 742 } 743} 744 745template<class Impl> 746void 747DefaultRename<Impl>::skidInsert(ThreadID tid) 748{ 749 DynInstPtr inst = NULL; 750 751 while (!insts[tid].empty()) { 752 inst = insts[tid].front(); 753 754 insts[tid].pop_front(); 755 756 assert(tid == inst->threadNumber); 757 758 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 759 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 760 761 ++renameSkidInsts; 762 763 skidBuffer[tid].push_back(inst); 764 } 765 766 if (skidBuffer[tid].size() > skidBufferMax) 767 { 768 typename InstQueue::iterator it; 769 warn("Skidbuffer contents:\n"); 770 for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 771 { 772 warn("[tid:%u]: %s [sn:%i].\n", tid, 773 (*it)->staticInst->disassemble(inst->instAddr()), 774 (*it)->seqNum); 775 } 776 panic("Skidbuffer Exceeded Max Size"); 777 } 778} 779 780template <class Impl> 781void 782DefaultRename<Impl>::sortInsts() 783{ 784 int insts_from_decode = fromDecode->size; 785 for (int i = 0; i < insts_from_decode; ++i) { 786 DynInstPtr inst = fromDecode->insts[i]; 787 insts[inst->threadNumber].push_back(inst); 788#if TRACING_ON 789 if (DTRACE(O3PipeView)) { 790 inst->renameTick = curTick() - inst->fetchTick; 791 } 792#endif 793 } 794} 795 796template<class Impl> 797bool 798DefaultRename<Impl>::skidsEmpty() 799{ 800 list<ThreadID>::iterator threads = activeThreads->begin(); 801 list<ThreadID>::iterator end = activeThreads->end(); 802 803 while (threads != end) { 804 ThreadID tid = *threads++; 805 806 if (!skidBuffer[tid].empty()) 807 return false; 808 } 809 810 return true; 811} 812 813template<class Impl> 814void 815DefaultRename<Impl>::updateStatus() 816{ 817 bool any_unblocking = false; 818 819 list<ThreadID>::iterator threads = activeThreads->begin(); 820 list<ThreadID>::iterator end = activeThreads->end(); 821 822 while (threads != end) { 823 ThreadID tid = *threads++; 824 825 if (renameStatus[tid] == Unblocking) { 826 any_unblocking = true; 827 break; 828 } 829 } 830 831 // Rename will have activity if it's unblocking. 832 if (any_unblocking) { 833 if (_status == Inactive) { 834 _status = Active; 835 836 DPRINTF(Activity, "Activating stage.\n"); 837 838 cpu->activateStage(O3CPU::RenameIdx); 839 } 840 } else { 841 // If it's not unblocking, then rename will not have any internal 842 // activity. Switch it to inactive. 843 if (_status == Active) { 844 _status = Inactive; 845 DPRINTF(Activity, "Deactivating stage.\n"); 846 847 cpu->deactivateStage(O3CPU::RenameIdx); 848 } 849 } 850} 851 852template <class Impl> 853bool 854DefaultRename<Impl>::block(ThreadID tid) 855{ 856 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 857 858 // Add the current inputs onto the skid buffer, so they can be 859 // reprocessed when this stage unblocks. 860 skidInsert(tid); 861 862 // Only signal backwards to block if the previous stages do not think 863 // rename is already blocked. 864 if (renameStatus[tid] != Blocked) { 865 // If resumeUnblocking is set, we unblocked during the squash, 866 // but now we're have unblocking status. We need to tell earlier 867 // stages to block. 868 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 869 toDecode->renameBlock[tid] = true; 870 toDecode->renameUnblock[tid] = false; 871 wroteToTimeBuffer = true; 872 } 873 874 // Rename can not go from SerializeStall to Blocked, otherwise 875 // it would not know to complete the serialize stall. 876 if (renameStatus[tid] != SerializeStall) { 877 // Set status to Blocked. 878 renameStatus[tid] = Blocked; 879 return true; 880 } 881 } 882 883 return false; 884} 885 886template <class Impl> 887bool 888DefaultRename<Impl>::unblock(ThreadID tid) 889{ 890 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 891 892 // Rename is done unblocking if the skid buffer is empty. 893 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 894 895 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 896 897 toDecode->renameUnblock[tid] = true; 898 wroteToTimeBuffer = true; 899 900 renameStatus[tid] = Running; 901 return true; 902 } 903 904 return false; 905} 906 907template <class Impl> 908void 909DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 910{ 911 typename std::list<RenameHistory>::iterator hb_it = 912 historyBuffer[tid].begin(); 913 914 // After a syscall squashes everything, the history buffer may be empty 915 // but the ROB may still be squashing instructions. 916 if (historyBuffer[tid].empty()) { 917 return; 918 } 919 920 // Go through the most recent instructions, undoing the mappings 921 // they did and freeing up the registers. 922 while (!historyBuffer[tid].empty() && 923 hb_it->instSeqNum > squashed_seq_num) { 924 assert(hb_it != historyBuffer[tid].end()); 925 926 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 927 "number %i.\n", tid, hb_it->instSeqNum); 928 929 // Undo the rename mapping only if it was really a change. 930 // Special regs that are not really renamed (like misc regs 931 // and the zero reg) can be recognized because the new mapping 932 // is the same as the old one. While it would be merely a 933 // waste of time to update the rename table, we definitely 934 // don't want to put these on the free list. 935 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 936 // Tell the rename map to set the architected register to the 937 // previous physical register that it was renamed to. 938 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 939 940 // Put the renamed physical register back on the free list. 941 freeList->addReg(hb_it->newPhysReg); 942 } 943 944 // Notify potential listeners that the register mapping needs to be 945 // removed because the instruction it was mapped to got squashed. Note 946 // that this is done before hb_it is incremented. 947 ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 948 hb_it->newPhysReg)); 949 950 historyBuffer[tid].erase(hb_it++); 951 952 ++renameUndoneMaps; 953 } 954} 955 956template<class Impl> 957void 958DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 959{ 960 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 961 "history buffer %u (size=%i), until [sn:%lli].\n", 962 tid, tid, historyBuffer[tid].size(), inst_seq_num); 963 964 typename std::list<RenameHistory>::iterator hb_it = 965 historyBuffer[tid].end(); 966 967 --hb_it; 968 969 if (historyBuffer[tid].empty()) { 970 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 971 return; 972 } else if (hb_it->instSeqNum > inst_seq_num) { 973 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 974 "that a syscall happened recently.\n", tid); 975 return; 976 } 977 978 // Commit all the renames up until (and including) the committed sequence 979 // number. Some or even all of the committed instructions may not have 980 // rename histories if they did not have destination registers that were 981 // renamed. 982 while (!historyBuffer[tid].empty() && 983 hb_it != historyBuffer[tid].end() && 984 hb_it->instSeqNum <= inst_seq_num) { 985 986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 987 "[sn:%lli].\n", 988 tid, hb_it->prevPhysReg->index(), 989 hb_it->prevPhysReg->className(), 990 hb_it->instSeqNum); 991 992 // Don't free special phys regs like misc and zero regs, which 993 // can be recognized because the new mapping is the same as 994 // the old one. 995 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 996 freeList->addReg(hb_it->prevPhysReg); 997 } 998 999 ++renameCommittedMaps; 1000 1001 historyBuffer[tid].erase(hb_it--); 1002 } 1003} 1004 1005template <class Impl> 1006inline void 1007DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 1008{ 1009 ThreadContext *tc = inst->tcBase(); 1010 RenameMap *map = renameMap[tid]; 1011 unsigned num_src_regs = inst->numSrcRegs(); 1012 1013 // Get the architectual register numbers from the source and 1014 // operands, and redirect them to the right physical register. 1015 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1016 const RegId& src_reg = inst->srcRegIdx(src_idx); 1017 PhysRegIdPtr renamed_reg; 1018 1019 renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 1020 switch (src_reg.classValue()) { 1021 case IntRegClass: 1022 intRenameLookups++; 1023 break; 1024 case FloatRegClass: 1025 fpRenameLookups++; 1026 break; 1027 case CCRegClass: 1028 case MiscRegClass: 1029 break; 1030 1031 default: 1032 panic("Invalid register class: %d.", src_reg.classValue()); 1033 } 1034 1035 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 1036 ", got phys reg %i (%s)\n", tid, 1037 src_reg.className(), src_reg.index(), 1038 renamed_reg->index(), 1039 renamed_reg->className()); 1040 1041 inst->renameSrcReg(src_idx, renamed_reg); 1042 1043 // See if the register is ready or not. 1044 if (scoreboard->getReg(renamed_reg)) { 1045 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1046 " is ready.\n", tid, renamed_reg->index(), 1047 renamed_reg->flatIndex(), 1048 renamed_reg->className()); 1049 1050 inst->markSrcRegReady(src_idx); 1051 } else { 1052 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1053 " is not ready.\n", tid, renamed_reg->index(), 1054 renamed_reg->flatIndex(), 1055 renamed_reg->className()); 1056 } 1057 1058 ++renameRenameLookups; 1059 } 1060} 1061 1062template <class Impl> 1063inline void 1064DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1065{ 1066 ThreadContext *tc = inst->tcBase(); 1067 RenameMap *map = renameMap[tid]; 1068 unsigned num_dest_regs = inst->numDestRegs(); 1069 1070 // Rename the destination registers. 1071 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1072 const RegId& dest_reg = inst->destRegIdx(dest_idx); 1073 typename RenameMap::RenameInfo rename_result; 1074 1075 RegId flat_dest_regid = tc->flattenRegId(dest_reg); 1076 1077 rename_result = map->rename(flat_dest_regid); 1078 1079 inst->flattenDestReg(dest_idx, flat_dest_regid); 1080 1081 // Mark Scoreboard entry as not ready 1082 scoreboard->unsetReg(rename_result.first); 1083 1084 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 1085 "reg %i (%i).\n", tid, dest_reg.index(), 1086 dest_reg.className(), 1087 rename_result.first->index(), 1088 rename_result.first->flatIndex()); 1089 1090 // Record the rename information so that a history can be kept. 1091 RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 1092 rename_result.first, 1093 rename_result.second); 1094 1095 historyBuffer[tid].push_front(hb_entry); 1096 1097 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1098 "(size=%i), [sn:%lli].\n",tid, 1099 historyBuffer[tid].size(), 1100 (*historyBuffer[tid].begin()).instSeqNum); 1101 1102 // Tell the instruction to rename the appropriate destination 1103 // register (dest_idx) to the new physical register 1104 // (rename_result.first), and record the previous physical 1105 // register that the same logical register was renamed to 1106 // (rename_result.second). 1107 inst->renameDestReg(dest_idx, 1108 rename_result.first, 1109 rename_result.second); 1110 1111 ++renameRenamedOperands; 1112 } 1113} 1114 1115template <class Impl> 1116inline int 1117DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1118{ 1119 int num_free = freeEntries[tid].robEntries - 1120 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1121 1122 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1123 1124 return num_free; 1125} 1126 1127template <class Impl> 1128inline int 1129DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1130{ 1131 int num_free = freeEntries[tid].iqEntries - 1132 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1133 1134 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1135 1136 return num_free; 1137} 1138 1139template <class Impl> 1140inline int 1141DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1142{ 1143 int num_free = freeEntries[tid].lqEntries - 1144 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1145 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1146 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1147 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1148 return num_free; 1149} 1150 1151template <class Impl> 1152inline int 1153DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1154{ 1155 int num_free = freeEntries[tid].sqEntries - 1156 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1157 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1158 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1159 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1160 return num_free; 1161} 1162 1163template <class Impl> 1164unsigned 1165DefaultRename<Impl>::validInsts() 1166{ 1167 unsigned inst_count = 0; 1168 1169 for (int i=0; i<fromDecode->size; i++) { 1170 if (!fromDecode->insts[i]->isSquashed()) 1171 inst_count++; 1172 } 1173 1174 return inst_count; 1175} 1176 1177template <class Impl> 1178void 1179DefaultRename<Impl>::readStallSignals(ThreadID tid) 1180{ 1181 if (fromIEW->iewBlock[tid]) { 1182 stalls[tid].iew = true; 1183 } 1184 1185 if (fromIEW->iewUnblock[tid]) { 1186 assert(stalls[tid].iew); 1187 stalls[tid].iew = false; 1188 } 1189} 1190 1191template <class Impl> 1192bool 1193DefaultRename<Impl>::checkStall(ThreadID tid) 1194{ 1195 bool ret_val = false; 1196 1197 if (stalls[tid].iew) { 1198 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1199 ret_val = true; 1200 } else if (calcFreeROBEntries(tid) <= 0) { 1201 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1202 ret_val = true; 1203 } else if (calcFreeIQEntries(tid) <= 0) { 1204 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1205 ret_val = true; 1206 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 1207 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1208 ret_val = true; 1209 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1210 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1211 ret_val = true; 1212 } else if (renameStatus[tid] == SerializeStall && 1213 (!emptyROB[tid] || instsInProgress[tid])) { 1214 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1215 "empty.\n", 1216 tid); 1217 ret_val = true; 1218 } 1219 1220 return ret_val; 1221} 1222 1223template <class Impl> 1224void 1225DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1226{ 1227 if (fromIEW->iewInfo[tid].usedIQ) 1228 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1229 1230 if (fromIEW->iewInfo[tid].usedLSQ) { 1231 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1232 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1233 } 1234 1235 if (fromCommit->commitInfo[tid].usedROB) { 1236 freeEntries[tid].robEntries = 1237 fromCommit->commitInfo[tid].freeROBEntries; 1238 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1239 } 1240 1241 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1242 "Free LQ: %i, Free SQ: %i\n", 1243 tid, 1244 freeEntries[tid].iqEntries, 1245 freeEntries[tid].robEntries, 1246 freeEntries[tid].lqEntries, 1247 freeEntries[tid].sqEntries); 1248 1249 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1250 tid, instsInProgress[tid]); 1251} 1252 1253template <class Impl> 1254bool 1255DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1256{ 1257 // Check if there's a squash signal, squash if there is 1258 // Check stall signals, block if necessary. 1259 // If status was blocked 1260 // check if stall conditions have passed 1261 // if so then go to unblocking 1262 // If status was Squashing 1263 // check if squashing is not high. Switch to running this cycle. 1264 // If status was serialize stall 1265 // check if ROB is empty and no insts are in flight to the ROB 1266 1267 readFreeEntries(tid); 1268 readStallSignals(tid); 1269 1270 if (fromCommit->commitInfo[tid].squash) { 1271 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1272 "commit.\n", tid); 1273 1274 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1275 1276 return true; 1277 } 1278 1279 if (checkStall(tid)) { 1280 return block(tid); 1281 } 1282 1283 if (renameStatus[tid] == Blocked) { 1284 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1285 tid); 1286 1287 renameStatus[tid] = Unblocking; 1288 1289 unblock(tid); 1290 1291 return true; 1292 } 1293 1294 if (renameStatus[tid] == Squashing) { 1295 // Switch status to running if rename isn't being told to block or 1296 // squash this cycle. 1297 if (resumeSerialize) { 1298 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1299 tid); 1300 1301 renameStatus[tid] = SerializeStall; 1302 return true; 1303 } else if (resumeUnblocking) { 1304 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1305 tid); 1306 renameStatus[tid] = Unblocking; 1307 return true; 1308 } else { 1309 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1310 tid); 1311 1312 renameStatus[tid] = Running; 1313 return false; 1314 } 1315 } 1316 1317 if (renameStatus[tid] == SerializeStall) { 1318 // Stall ends once the ROB is free. 1319 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1320 "unblocking.\n", tid); 1321 1322 DynInstPtr serial_inst = serializeInst[tid]; 1323 1324 renameStatus[tid] = Unblocking; 1325 1326 unblock(tid); 1327 1328 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1329 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1330 1331 // Put instruction into queue here. 1332 serial_inst->clearSerializeBefore(); 1333 1334 if (!skidBuffer[tid].empty()) { 1335 skidBuffer[tid].push_front(serial_inst); 1336 } else { 1337 insts[tid].push_front(serial_inst); 1338 } 1339 1340 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1341 " Adding to front of list.\n", tid); 1342 1343 serializeInst[tid] = NULL; 1344 1345 return true; 1346 } 1347 1348 // If we've reached this point, we have not gotten any signals that 1349 // cause rename to change its status. Rename remains the same as before. 1350 return false; 1351} 1352 1353template<class Impl> 1354void 1355DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1356{ 1357 if (inst_list.empty()) { 1358 // Mark a bit to say that I must serialize on the next instruction. 1359 serializeOnNextInst[tid] = true; 1360 return; 1361 } 1362 1363 // Set the next instruction as serializing. 1364 inst_list.front()->setSerializeBefore(); 1365} 1366 1367template <class Impl> 1368inline void 1369DefaultRename<Impl>::incrFullStat(const FullSource &source) 1370{ 1371 switch (source) { 1372 case ROB: 1373 ++renameROBFullEvents; 1374 break; 1375 case IQ: 1376 ++renameIQFullEvents; 1377 break; 1378 case LQ: 1379 ++renameLQFullEvents; 1380 break; 1381 case SQ: 1382 ++renameSQFullEvents; 1383 break; 1384 default: 1385 panic("Rename full stall stat should be incremented for a reason!"); 1386 break; 1387 } 1388} 1389 1390template <class Impl> 1391void 1392DefaultRename<Impl>::dumpHistory() 1393{ 1394 typename std::list<RenameHistory>::iterator buf_it; 1395 1396 for (ThreadID tid = 0; tid < numThreads; tid++) { 1397 1398 buf_it = historyBuffer[tid].begin(); 1399 1400 while (buf_it != historyBuffer[tid].end()) { 1401 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 1402 " %i[%s] Old phys reg: %i[%s]\n", 1403 (*buf_it).instSeqNum, 1404 (*buf_it).archReg.className(), 1405 (*buf_it).archReg.index(), 1406 (*buf_it).newPhysReg->index(), 1407 (*buf_it).newPhysReg->className(), 1408 (*buf_it).prevPhysReg->index(), 1409 (*buf_it).prevPhysReg->className()); 1410 1411 buf_it++; 1412 } 1413 } 1414} 1415 1416#endif//__CPU_O3_RENAME_IMPL_HH__ 1417