rename_impl.hh revision 11246:93d2a1526103
1/* 2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_RENAME_IMPL_HH__ 46#define __CPU_O3_RENAME_IMPL_HH__ 47 48#include <list> 49 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "config/the_isa.hh" 53#include "cpu/o3/rename.hh" 54#include "cpu/reg_class.hh" 55#include "debug/Activity.hh" 56#include "debug/Rename.hh" 57#include "debug/O3PipeView.hh" 58#include "params/DerivO3CPU.hh" 59 60using namespace std; 61 62template <class Impl> 63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 64 : cpu(_cpu), 65 iewToRenameDelay(params->iewToRenameDelay), 66 decodeToRenameDelay(params->decodeToRenameDelay), 67 commitToRenameDelay(params->commitToRenameDelay), 68 renameWidth(params->renameWidth), 69 commitWidth(params->commitWidth), 70 numThreads(params->numThreads), 71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 72 + params->numPhysCCRegs) 73{ 74 if (renameWidth > Impl::MaxWidth) 75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 77 renameWidth, static_cast<int>(Impl::MaxWidth)); 78 79 // @todo: Make into a parameter. 80 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 81} 82 83template <class Impl> 84std::string 85DefaultRename<Impl>::name() const 86{ 87 return cpu->name() + ".rename"; 88} 89 90template <class Impl> 91void 92DefaultRename<Impl>::regStats() 93{ 94 renameSquashCycles 95 .name(name() + ".SquashCycles") 96 .desc("Number of cycles rename is squashing") 97 .prereq(renameSquashCycles); 98 renameIdleCycles 99 .name(name() + ".IdleCycles") 100 .desc("Number of cycles rename is idle") 101 .prereq(renameIdleCycles); 102 renameBlockCycles 103 .name(name() + ".BlockCycles") 104 .desc("Number of cycles rename is blocking") 105 .prereq(renameBlockCycles); 106 renameSerializeStallCycles 107 .name(name() + ".serializeStallCycles") 108 .desc("count of cycles rename stalled for serializing inst") 109 .flags(Stats::total); 110 renameRunCycles 111 .name(name() + ".RunCycles") 112 .desc("Number of cycles rename is running") 113 .prereq(renameIdleCycles); 114 renameUnblockCycles 115 .name(name() + ".UnblockCycles") 116 .desc("Number of cycles rename is unblocking") 117 .prereq(renameUnblockCycles); 118 renameRenamedInsts 119 .name(name() + ".RenamedInsts") 120 .desc("Number of instructions processed by rename") 121 .prereq(renameRenamedInsts); 122 renameSquashedInsts 123 .name(name() + ".SquashedInsts") 124 .desc("Number of squashed instructions processed by rename") 125 .prereq(renameSquashedInsts); 126 renameROBFullEvents 127 .name(name() + ".ROBFullEvents") 128 .desc("Number of times rename has blocked due to ROB full") 129 .prereq(renameROBFullEvents); 130 renameIQFullEvents 131 .name(name() + ".IQFullEvents") 132 .desc("Number of times rename has blocked due to IQ full") 133 .prereq(renameIQFullEvents); 134 renameLQFullEvents 135 .name(name() + ".LQFullEvents") 136 .desc("Number of times rename has blocked due to LQ full") 137 .prereq(renameLQFullEvents); 138 renameSQFullEvents 139 .name(name() + ".SQFullEvents") 140 .desc("Number of times rename has blocked due to SQ full") 141 .prereq(renameSQFullEvents); 142 renameFullRegistersEvents 143 .name(name() + ".FullRegisterEvents") 144 .desc("Number of times there has been no free registers") 145 .prereq(renameFullRegistersEvents); 146 renameRenamedOperands 147 .name(name() + ".RenamedOperands") 148 .desc("Number of destination operands rename has renamed") 149 .prereq(renameRenamedOperands); 150 renameRenameLookups 151 .name(name() + ".RenameLookups") 152 .desc("Number of register rename lookups that rename has made") 153 .prereq(renameRenameLookups); 154 renameCommittedMaps 155 .name(name() + ".CommittedMaps") 156 .desc("Number of HB maps that are committed") 157 .prereq(renameCommittedMaps); 158 renameUndoneMaps 159 .name(name() + ".UndoneMaps") 160 .desc("Number of HB maps that are undone due to squashing") 161 .prereq(renameUndoneMaps); 162 renamedSerializing 163 .name(name() + ".serializingInsts") 164 .desc("count of serializing insts renamed") 165 .flags(Stats::total) 166 ; 167 renamedTempSerializing 168 .name(name() + ".tempSerializingInsts") 169 .desc("count of temporary serializing insts renamed") 170 .flags(Stats::total) 171 ; 172 renameSkidInsts 173 .name(name() + ".skidInsts") 174 .desc("count of insts added to the skid buffer") 175 .flags(Stats::total) 176 ; 177 intRenameLookups 178 .name(name() + ".int_rename_lookups") 179 .desc("Number of integer rename lookups") 180 .prereq(intRenameLookups); 181 fpRenameLookups 182 .name(name() + ".fp_rename_lookups") 183 .desc("Number of floating rename lookups") 184 .prereq(fpRenameLookups); 185} 186 187template <class Impl> 188void 189DefaultRename<Impl>::regProbePoints() 190{ 191 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 192 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 193 "SquashInRename"); 194} 195 196template <class Impl> 197void 198DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 199{ 200 timeBuffer = tb_ptr; 201 202 // Setup wire to read information from time buffer, from IEW stage. 203 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 204 205 // Setup wire to read infromation from time buffer, from commit stage. 206 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 207 208 // Setup wire to write information to previous stages. 209 toDecode = timeBuffer->getWire(0); 210} 211 212template <class Impl> 213void 214DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 215{ 216 renameQueue = rq_ptr; 217 218 // Setup wire to write information to future stages. 219 toIEW = renameQueue->getWire(0); 220} 221 222template <class Impl> 223void 224DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 225{ 226 decodeQueue = dq_ptr; 227 228 // Setup wire to get information from decode. 229 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 230} 231 232template <class Impl> 233void 234DefaultRename<Impl>::startupStage() 235{ 236 resetStage(); 237} 238 239template <class Impl> 240void 241DefaultRename<Impl>::resetStage() 242{ 243 _status = Inactive; 244 245 resumeSerialize = false; 246 resumeUnblocking = false; 247 248 // Grab the number of free entries directly from the stages. 249 for (ThreadID tid = 0; tid < numThreads; tid++) { 250 renameStatus[tid] = Idle; 251 252 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 253 freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 254 freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 255 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 256 emptyROB[tid] = true; 257 258 stalls[tid].iew = false; 259 serializeInst[tid] = NULL; 260 261 instsInProgress[tid] = 0; 262 loadsInProgress[tid] = 0; 263 storesInProgress[tid] = 0; 264 265 serializeOnNextInst[tid] = false; 266 } 267} 268 269template<class Impl> 270void 271DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 272{ 273 activeThreads = at_ptr; 274} 275 276 277template <class Impl> 278void 279DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 280{ 281 for (ThreadID tid = 0; tid < numThreads; tid++) 282 renameMap[tid] = &rm_ptr[tid]; 283} 284 285template <class Impl> 286void 287DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 288{ 289 freeList = fl_ptr; 290} 291 292template<class Impl> 293void 294DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 295{ 296 scoreboard = _scoreboard; 297} 298 299template <class Impl> 300bool 301DefaultRename<Impl>::isDrained() const 302{ 303 for (ThreadID tid = 0; tid < numThreads; tid++) { 304 if (instsInProgress[tid] != 0 || 305 !historyBuffer[tid].empty() || 306 !skidBuffer[tid].empty() || 307 !insts[tid].empty()) 308 return false; 309 } 310 return true; 311} 312 313template <class Impl> 314void 315DefaultRename<Impl>::takeOverFrom() 316{ 317 resetStage(); 318} 319 320template <class Impl> 321void 322DefaultRename<Impl>::drainSanityCheck() const 323{ 324 for (ThreadID tid = 0; tid < numThreads; tid++) { 325 assert(historyBuffer[tid].empty()); 326 assert(insts[tid].empty()); 327 assert(skidBuffer[tid].empty()); 328 assert(instsInProgress[tid] == 0); 329 } 330} 331 332template <class Impl> 333void 334DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 335{ 336 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 337 338 // Clear the stall signal if rename was blocked or unblocking before. 339 // If it still needs to block, the blocking should happen the next 340 // cycle and there should be space to hold everything due to the squash. 341 if (renameStatus[tid] == Blocked || 342 renameStatus[tid] == Unblocking) { 343 toDecode->renameUnblock[tid] = 1; 344 345 resumeSerialize = false; 346 serializeInst[tid] = NULL; 347 } else if (renameStatus[tid] == SerializeStall) { 348 if (serializeInst[tid]->seqNum <= squash_seq_num) { 349 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 350 resumeSerialize = true; 351 assert(serializeInst[tid]); 352 } else { 353 resumeSerialize = false; 354 toDecode->renameUnblock[tid] = 1; 355 356 serializeInst[tid] = NULL; 357 } 358 } 359 360 // Set the status to Squashing. 361 renameStatus[tid] = Squashing; 362 363 // Squash any instructions from decode. 364 for (int i=0; i<fromDecode->size; i++) { 365 if (fromDecode->insts[i]->threadNumber == tid && 366 fromDecode->insts[i]->seqNum > squash_seq_num) { 367 fromDecode->insts[i]->setSquashed(); 368 wroteToTimeBuffer = true; 369 } 370 371 } 372 373 // Clear the instruction list and skid buffer in case they have any 374 // insts in them. 375 insts[tid].clear(); 376 377 // Clear the skid buffer in case it has any data in it. 378 skidBuffer[tid].clear(); 379 380 doSquash(squash_seq_num, tid); 381} 382 383template <class Impl> 384void 385DefaultRename<Impl>::tick() 386{ 387 wroteToTimeBuffer = false; 388 389 blockThisCycle = false; 390 391 bool status_change = false; 392 393 toIEWIndex = 0; 394 395 sortInsts(); 396 397 list<ThreadID>::iterator threads = activeThreads->begin(); 398 list<ThreadID>::iterator end = activeThreads->end(); 399 400 // Check stall and squash signals. 401 while (threads != end) { 402 ThreadID tid = *threads++; 403 404 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 405 406 status_change = checkSignalsAndUpdate(tid) || status_change; 407 408 rename(status_change, tid); 409 } 410 411 if (status_change) { 412 updateStatus(); 413 } 414 415 if (wroteToTimeBuffer) { 416 DPRINTF(Activity, "Activity this cycle.\n"); 417 cpu->activityThisCycle(); 418 } 419 420 threads = activeThreads->begin(); 421 422 while (threads != end) { 423 ThreadID tid = *threads++; 424 425 // If we committed this cycle then doneSeqNum will be > 0 426 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 427 !fromCommit->commitInfo[tid].squash && 428 renameStatus[tid] != Squashing) { 429 430 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 431 tid); 432 } 433 } 434 435 // @todo: make into updateProgress function 436 for (ThreadID tid = 0; tid < numThreads; tid++) { 437 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 438 loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 439 storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 440 assert(loadsInProgress[tid] >= 0); 441 assert(storesInProgress[tid] >= 0); 442 assert(instsInProgress[tid] >=0); 443 } 444 445} 446 447template<class Impl> 448void 449DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 450{ 451 // If status is Running or idle, 452 // call renameInsts() 453 // If status is Unblocking, 454 // buffer any instructions coming from decode 455 // continue trying to empty skid buffer 456 // check if stall conditions have passed 457 458 if (renameStatus[tid] == Blocked) { 459 ++renameBlockCycles; 460 } else if (renameStatus[tid] == Squashing) { 461 ++renameSquashCycles; 462 } else if (renameStatus[tid] == SerializeStall) { 463 ++renameSerializeStallCycles; 464 // If we are currently in SerializeStall and resumeSerialize 465 // was set, then that means that we are resuming serializing 466 // this cycle. Tell the previous stages to block. 467 if (resumeSerialize) { 468 resumeSerialize = false; 469 block(tid); 470 toDecode->renameUnblock[tid] = false; 471 } 472 } else if (renameStatus[tid] == Unblocking) { 473 if (resumeUnblocking) { 474 block(tid); 475 resumeUnblocking = false; 476 toDecode->renameUnblock[tid] = false; 477 } 478 } 479 480 if (renameStatus[tid] == Running || 481 renameStatus[tid] == Idle) { 482 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 483 "stage.\n", tid); 484 485 renameInsts(tid); 486 } else if (renameStatus[tid] == Unblocking) { 487 renameInsts(tid); 488 489 if (validInsts()) { 490 // Add the current inputs to the skid buffer so they can be 491 // reprocessed when this stage unblocks. 492 skidInsert(tid); 493 } 494 495 // If we switched over to blocking, then there's a potential for 496 // an overall status change. 497 status_change = unblock(tid) || status_change || blockThisCycle; 498 } 499} 500 501template <class Impl> 502void 503DefaultRename<Impl>::renameInsts(ThreadID tid) 504{ 505 // Instructions can be either in the skid buffer or the queue of 506 // instructions coming from decode, depending on the status. 507 int insts_available = renameStatus[tid] == Unblocking ? 508 skidBuffer[tid].size() : insts[tid].size(); 509 510 // Check the decode queue to see if instructions are available. 511 // If there are no available instructions to rename, then do nothing. 512 if (insts_available == 0) { 513 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 514 tid); 515 // Should I change status to idle? 516 ++renameIdleCycles; 517 return; 518 } else if (renameStatus[tid] == Unblocking) { 519 ++renameUnblockCycles; 520 } else if (renameStatus[tid] == Running) { 521 ++renameRunCycles; 522 } 523 524 DynInstPtr inst; 525 526 // Will have to do a different calculation for the number of free 527 // entries. 528 int free_rob_entries = calcFreeROBEntries(tid); 529 int free_iq_entries = calcFreeIQEntries(tid); 530 int min_free_entries = free_rob_entries; 531 532 FullSource source = ROB; 533 534 if (free_iq_entries < min_free_entries) { 535 min_free_entries = free_iq_entries; 536 source = IQ; 537 } 538 539 // Check if there's any space left. 540 if (min_free_entries <= 0) { 541 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 542 "entries.\n" 543 "ROB has %i free entries.\n" 544 "IQ has %i free entries.\n", 545 tid, 546 free_rob_entries, 547 free_iq_entries); 548 549 blockThisCycle = true; 550 551 block(tid); 552 553 incrFullStat(source); 554 555 return; 556 } else if (min_free_entries < insts_available) { 557 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 558 "%i insts available, but only %i insts can be " 559 "renamed due to ROB/IQ/LSQ limits.\n", 560 tid, insts_available, min_free_entries); 561 562 insts_available = min_free_entries; 563 564 blockThisCycle = true; 565 566 incrFullStat(source); 567 } 568 569 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 570 skidBuffer[tid] : insts[tid]; 571 572 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 573 "send iew.\n", tid, insts_available); 574 575 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 576 "dispatched to IQ last cycle.\n", 577 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 578 579 // Handle serializing the next instruction if necessary. 580 if (serializeOnNextInst[tid]) { 581 if (emptyROB[tid] && instsInProgress[tid] == 0) { 582 // ROB already empty; no need to serialize. 583 serializeOnNextInst[tid] = false; 584 } else if (!insts_to_rename.empty()) { 585 insts_to_rename.front()->setSerializeBefore(); 586 } 587 } 588 589 int renamed_insts = 0; 590 591 while (insts_available > 0 && toIEWIndex < renameWidth) { 592 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 593 594 assert(!insts_to_rename.empty()); 595 596 inst = insts_to_rename.front(); 597 598 //For all kind of instructions, check ROB and IQ first 599 //For load instruction, check LQ size and take into account the inflight loads 600 //For store instruction, check SQ size and take into account the inflight stores 601 602 if (inst->isLoad()) { 603 if (calcFreeLQEntries(tid) <= 0) { 604 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 605 source = LQ; 606 incrFullStat(source); 607 break; 608 } 609 } 610 611 if (inst->isStore()) { 612 if (calcFreeSQEntries(tid) <= 0) { 613 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 614 source = SQ; 615 incrFullStat(source); 616 break; 617 } 618 } 619 620 insts_to_rename.pop_front(); 621 622 if (renameStatus[tid] == Unblocking) { 623 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 624 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 625 } 626 627 if (inst->isSquashed()) { 628 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 629 "squashed, skipping.\n", tid, inst->seqNum, 630 inst->pcState()); 631 632 ++renameSquashedInsts; 633 634 // Decrement how many instructions are available. 635 --insts_available; 636 637 continue; 638 } 639 640 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 641 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 642 643 // Check here to make sure there are enough destination registers 644 // to rename to. Otherwise block. 645 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 646 inst->numFPDestRegs(), 647 inst->numCCDestRegs())) { 648 DPRINTF(Rename, "Blocking due to lack of free " 649 "physical registers to rename to.\n"); 650 blockThisCycle = true; 651 insts_to_rename.push_front(inst); 652 ++renameFullRegistersEvents; 653 654 break; 655 } 656 657 // Handle serializeAfter/serializeBefore instructions. 658 // serializeAfter marks the next instruction as serializeBefore. 659 // serializeBefore makes the instruction wait in rename until the ROB 660 // is empty. 661 662 // In this model, IPR accesses are serialize before 663 // instructions, and store conditionals are serialize after 664 // instructions. This is mainly due to lack of support for 665 // out-of-order operations of either of those classes of 666 // instructions. 667 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 668 !inst->isSerializeHandled()) { 669 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 670 671 if (!inst->isTempSerializeBefore()) { 672 renamedSerializing++; 673 inst->setSerializeHandled(); 674 } else { 675 renamedTempSerializing++; 676 } 677 678 // Change status over to SerializeStall so that other stages know 679 // what this is blocked on. 680 renameStatus[tid] = SerializeStall; 681 682 serializeInst[tid] = inst; 683 684 blockThisCycle = true; 685 686 break; 687 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 688 !inst->isSerializeHandled()) { 689 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 690 691 renamedSerializing++; 692 693 inst->setSerializeHandled(); 694 695 serializeAfter(insts_to_rename, tid); 696 } 697 698 renameSrcRegs(inst, inst->threadNumber); 699 700 renameDestRegs(inst, inst->threadNumber); 701 702 if (inst->isLoad()) { 703 loadsInProgress[tid]++; 704 } 705 if (inst->isStore()) { 706 storesInProgress[tid]++; 707 } 708 ++renamed_insts; 709 // Notify potential listeners that source and destination registers for 710 // this instruction have been renamed. 711 ppRename->notify(inst); 712 713 // Put instruction in rename queue. 714 toIEW->insts[toIEWIndex] = inst; 715 ++(toIEW->size); 716 717 // Increment which instruction we're on. 718 ++toIEWIndex; 719 720 // Decrement how many instructions are available. 721 --insts_available; 722 } 723 724 instsInProgress[tid] += renamed_insts; 725 renameRenamedInsts += renamed_insts; 726 727 // If we wrote to the time buffer, record this. 728 if (toIEWIndex) { 729 wroteToTimeBuffer = true; 730 } 731 732 // Check if there's any instructions left that haven't yet been renamed. 733 // If so then block. 734 if (insts_available) { 735 blockThisCycle = true; 736 } 737 738 if (blockThisCycle) { 739 block(tid); 740 toDecode->renameUnblock[tid] = false; 741 } 742} 743 744template<class Impl> 745void 746DefaultRename<Impl>::skidInsert(ThreadID tid) 747{ 748 DynInstPtr inst = NULL; 749 750 while (!insts[tid].empty()) { 751 inst = insts[tid].front(); 752 753 insts[tid].pop_front(); 754 755 assert(tid == inst->threadNumber); 756 757 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 758 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 759 760 ++renameSkidInsts; 761 762 skidBuffer[tid].push_back(inst); 763 } 764 765 if (skidBuffer[tid].size() > skidBufferMax) 766 { 767 typename InstQueue::iterator it; 768 warn("Skidbuffer contents:\n"); 769 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 770 { 771 warn("[tid:%u]: %s [sn:%i].\n", tid, 772 (*it)->staticInst->disassemble(inst->instAddr()), 773 (*it)->seqNum); 774 } 775 panic("Skidbuffer Exceeded Max Size"); 776 } 777} 778 779template <class Impl> 780void 781DefaultRename<Impl>::sortInsts() 782{ 783 int insts_from_decode = fromDecode->size; 784 for (int i = 0; i < insts_from_decode; ++i) { 785 DynInstPtr inst = fromDecode->insts[i]; 786 insts[inst->threadNumber].push_back(inst); 787#if TRACING_ON 788 if (DTRACE(O3PipeView)) { 789 inst->renameTick = curTick() - inst->fetchTick; 790 } 791#endif 792 } 793} 794 795template<class Impl> 796bool 797DefaultRename<Impl>::skidsEmpty() 798{ 799 list<ThreadID>::iterator threads = activeThreads->begin(); 800 list<ThreadID>::iterator end = activeThreads->end(); 801 802 while (threads != end) { 803 ThreadID tid = *threads++; 804 805 if (!skidBuffer[tid].empty()) 806 return false; 807 } 808 809 return true; 810} 811 812template<class Impl> 813void 814DefaultRename<Impl>::updateStatus() 815{ 816 bool any_unblocking = false; 817 818 list<ThreadID>::iterator threads = activeThreads->begin(); 819 list<ThreadID>::iterator end = activeThreads->end(); 820 821 while (threads != end) { 822 ThreadID tid = *threads++; 823 824 if (renameStatus[tid] == Unblocking) { 825 any_unblocking = true; 826 break; 827 } 828 } 829 830 // Rename will have activity if it's unblocking. 831 if (any_unblocking) { 832 if (_status == Inactive) { 833 _status = Active; 834 835 DPRINTF(Activity, "Activating stage.\n"); 836 837 cpu->activateStage(O3CPU::RenameIdx); 838 } 839 } else { 840 // If it's not unblocking, then rename will not have any internal 841 // activity. Switch it to inactive. 842 if (_status == Active) { 843 _status = Inactive; 844 DPRINTF(Activity, "Deactivating stage.\n"); 845 846 cpu->deactivateStage(O3CPU::RenameIdx); 847 } 848 } 849} 850 851template <class Impl> 852bool 853DefaultRename<Impl>::block(ThreadID tid) 854{ 855 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 856 857 // Add the current inputs onto the skid buffer, so they can be 858 // reprocessed when this stage unblocks. 859 skidInsert(tid); 860 861 // Only signal backwards to block if the previous stages do not think 862 // rename is already blocked. 863 if (renameStatus[tid] != Blocked) { 864 // If resumeUnblocking is set, we unblocked during the squash, 865 // but now we're have unblocking status. We need to tell earlier 866 // stages to block. 867 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 868 toDecode->renameBlock[tid] = true; 869 toDecode->renameUnblock[tid] = false; 870 wroteToTimeBuffer = true; 871 } 872 873 // Rename can not go from SerializeStall to Blocked, otherwise 874 // it would not know to complete the serialize stall. 875 if (renameStatus[tid] != SerializeStall) { 876 // Set status to Blocked. 877 renameStatus[tid] = Blocked; 878 return true; 879 } 880 } 881 882 return false; 883} 884 885template <class Impl> 886bool 887DefaultRename<Impl>::unblock(ThreadID tid) 888{ 889 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 890 891 // Rename is done unblocking if the skid buffer is empty. 892 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 893 894 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 895 896 toDecode->renameUnblock[tid] = true; 897 wroteToTimeBuffer = true; 898 899 renameStatus[tid] = Running; 900 return true; 901 } 902 903 return false; 904} 905 906template <class Impl> 907void 908DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 909{ 910 typename std::list<RenameHistory>::iterator hb_it = 911 historyBuffer[tid].begin(); 912 913 // After a syscall squashes everything, the history buffer may be empty 914 // but the ROB may still be squashing instructions. 915 if (historyBuffer[tid].empty()) { 916 return; 917 } 918 919 // Go through the most recent instructions, undoing the mappings 920 // they did and freeing up the registers. 921 while (!historyBuffer[tid].empty() && 922 hb_it->instSeqNum > squashed_seq_num) { 923 assert(hb_it != historyBuffer[tid].end()); 924 925 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 926 "number %i.\n", tid, hb_it->instSeqNum); 927 928 // Undo the rename mapping only if it was really a change. 929 // Special regs that are not really renamed (like misc regs 930 // and the zero reg) can be recognized because the new mapping 931 // is the same as the old one. While it would be merely a 932 // waste of time to update the rename table, we definitely 933 // don't want to put these on the free list. 934 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 935 // Tell the rename map to set the architected register to the 936 // previous physical register that it was renamed to. 937 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 938 939 // Put the renamed physical register back on the free list. 940 freeList->addReg(hb_it->newPhysReg); 941 } 942 943 // Notify potential listeners that the register mapping needs to be 944 // removed because the instruction it was mapped to got squashed. Note 945 // that this is done before hb_it is incremented. 946 ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 947 hb_it->newPhysReg)); 948 949 historyBuffer[tid].erase(hb_it++); 950 951 ++renameUndoneMaps; 952 } 953} 954 955template<class Impl> 956void 957DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 958{ 959 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 960 "history buffer %u (size=%i), until [sn:%lli].\n", 961 tid, tid, historyBuffer[tid].size(), inst_seq_num); 962 963 typename std::list<RenameHistory>::iterator hb_it = 964 historyBuffer[tid].end(); 965 966 --hb_it; 967 968 if (historyBuffer[tid].empty()) { 969 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 970 return; 971 } else if (hb_it->instSeqNum > inst_seq_num) { 972 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 973 "that a syscall happened recently.\n", tid); 974 return; 975 } 976 977 // Commit all the renames up until (and including) the committed sequence 978 // number. Some or even all of the committed instructions may not have 979 // rename histories if they did not have destination registers that were 980 // renamed. 981 while (!historyBuffer[tid].empty() && 982 hb_it != historyBuffer[tid].end() && 983 hb_it->instSeqNum <= inst_seq_num) { 984 985 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 986 "[sn:%lli].\n", 987 tid, hb_it->prevPhysReg, hb_it->instSeqNum); 988 989 // Don't free special phys regs like misc and zero regs, which 990 // can be recognized because the new mapping is the same as 991 // the old one. 992 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 993 freeList->addReg(hb_it->prevPhysReg); 994 } 995 996 ++renameCommittedMaps; 997 998 historyBuffer[tid].erase(hb_it--); 999 } 1000} 1001 1002template <class Impl> 1003inline void 1004DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 1005{ 1006 ThreadContext *tc = inst->tcBase(); 1007 RenameMap *map = renameMap[tid]; 1008 unsigned num_src_regs = inst->numSrcRegs(); 1009 1010 // Get the architectual register numbers from the source and 1011 // operands, and redirect them to the right physical register. 1012 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1013 RegIndex src_reg = inst->srcRegIdx(src_idx); 1014 RegIndex rel_src_reg; 1015 RegIndex flat_rel_src_reg; 1016 PhysRegIndex renamed_reg; 1017 1018 switch (regIdxToClass(src_reg, &rel_src_reg)) { 1019 case IntRegClass: 1020 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 1021 renamed_reg = map->lookupInt(flat_rel_src_reg); 1022 intRenameLookups++; 1023 break; 1024 1025 case FloatRegClass: 1026 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 1027 renamed_reg = map->lookupFloat(flat_rel_src_reg); 1028 fpRenameLookups++; 1029 break; 1030 1031 case CCRegClass: 1032 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 1033 renamed_reg = map->lookupCC(flat_rel_src_reg); 1034 break; 1035 1036 case MiscRegClass: 1037 // misc regs don't get flattened 1038 flat_rel_src_reg = rel_src_reg; 1039 renamed_reg = map->lookupMisc(flat_rel_src_reg); 1040 break; 1041 1042 default: 1043 panic("Reg index is out of bound: %d.", src_reg); 1044 } 1045 1046 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 1047 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 1048 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); 1049 1050 inst->renameSrcReg(src_idx, renamed_reg); 1051 1052 // See if the register is ready or not. 1053 if (scoreboard->getReg(renamed_reg)) { 1054 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1055 tid, renamed_reg); 1056 1057 inst->markSrcRegReady(src_idx); 1058 } else { 1059 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1060 tid, renamed_reg); 1061 } 1062 1063 ++renameRenameLookups; 1064 } 1065} 1066 1067template <class Impl> 1068inline void 1069DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1070{ 1071 ThreadContext *tc = inst->tcBase(); 1072 RenameMap *map = renameMap[tid]; 1073 unsigned num_dest_regs = inst->numDestRegs(); 1074 1075 // Rename the destination registers. 1076 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1077 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1078 RegIndex rel_dest_reg; 1079 RegIndex flat_rel_dest_reg; 1080 RegIndex flat_uni_dest_reg; 1081 typename RenameMap::RenameInfo rename_result; 1082 1083 switch (regIdxToClass(dest_reg, &rel_dest_reg)) { 1084 case IntRegClass: 1085 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 1086 rename_result = map->renameInt(flat_rel_dest_reg); 1087 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping 1088 break; 1089 1090 case FloatRegClass: 1091 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1092 rename_result = map->renameFloat(flat_rel_dest_reg); 1093 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 1094 break; 1095 1096 case CCRegClass: 1097 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 1098 rename_result = map->renameCC(flat_rel_dest_reg); 1099 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 1100 break; 1101 1102 case MiscRegClass: 1103 // misc regs don't get flattened 1104 flat_rel_dest_reg = rel_dest_reg; 1105 rename_result = map->renameMisc(flat_rel_dest_reg); 1106 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 1107 break; 1108 1109 default: 1110 panic("Reg index is out of bound: %d.", dest_reg); 1111 } 1112 1113 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1114 1115 // Mark Scoreboard entry as not ready 1116 scoreboard->unsetReg(rename_result.first); 1117 1118 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1119 "reg %i.\n", tid, (int)flat_rel_dest_reg, 1120 (int)rename_result.first); 1121 1122 // Record the rename information so that a history can be kept. 1123 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1124 rename_result.first, 1125 rename_result.second); 1126 1127 historyBuffer[tid].push_front(hb_entry); 1128 1129 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1130 "(size=%i), [sn:%lli].\n",tid, 1131 historyBuffer[tid].size(), 1132 (*historyBuffer[tid].begin()).instSeqNum); 1133 1134 // Tell the instruction to rename the appropriate destination 1135 // register (dest_idx) to the new physical register 1136 // (rename_result.first), and record the previous physical 1137 // register that the same logical register was renamed to 1138 // (rename_result.second). 1139 inst->renameDestReg(dest_idx, 1140 rename_result.first, 1141 rename_result.second); 1142 1143 ++renameRenamedOperands; 1144 } 1145} 1146 1147template <class Impl> 1148inline int 1149DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1150{ 1151 int num_free = freeEntries[tid].robEntries - 1152 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1153 1154 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1155 1156 return num_free; 1157} 1158 1159template <class Impl> 1160inline int 1161DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1162{ 1163 int num_free = freeEntries[tid].iqEntries - 1164 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1165 1166 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1167 1168 return num_free; 1169} 1170 1171template <class Impl> 1172inline int 1173DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1174{ 1175 int num_free = freeEntries[tid].lqEntries - 1176 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1177 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1178 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1179 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1180 return num_free; 1181} 1182 1183template <class Impl> 1184inline int 1185DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1186{ 1187 int num_free = freeEntries[tid].sqEntries - 1188 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1189 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1190 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1191 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1192 return num_free; 1193} 1194 1195template <class Impl> 1196unsigned 1197DefaultRename<Impl>::validInsts() 1198{ 1199 unsigned inst_count = 0; 1200 1201 for (int i=0; i<fromDecode->size; i++) { 1202 if (!fromDecode->insts[i]->isSquashed()) 1203 inst_count++; 1204 } 1205 1206 return inst_count; 1207} 1208 1209template <class Impl> 1210void 1211DefaultRename<Impl>::readStallSignals(ThreadID tid) 1212{ 1213 if (fromIEW->iewBlock[tid]) { 1214 stalls[tid].iew = true; 1215 } 1216 1217 if (fromIEW->iewUnblock[tid]) { 1218 assert(stalls[tid].iew); 1219 stalls[tid].iew = false; 1220 } 1221} 1222 1223template <class Impl> 1224bool 1225DefaultRename<Impl>::checkStall(ThreadID tid) 1226{ 1227 bool ret_val = false; 1228 1229 if (stalls[tid].iew) { 1230 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1231 ret_val = true; 1232 } else if (calcFreeROBEntries(tid) <= 0) { 1233 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1234 ret_val = true; 1235 } else if (calcFreeIQEntries(tid) <= 0) { 1236 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1237 ret_val = true; 1238 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 1239 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1240 ret_val = true; 1241 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1242 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1243 ret_val = true; 1244 } else if (renameStatus[tid] == SerializeStall && 1245 (!emptyROB[tid] || instsInProgress[tid])) { 1246 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1247 "empty.\n", 1248 tid); 1249 ret_val = true; 1250 } 1251 1252 return ret_val; 1253} 1254 1255template <class Impl> 1256void 1257DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1258{ 1259 if (fromIEW->iewInfo[tid].usedIQ) 1260 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1261 1262 if (fromIEW->iewInfo[tid].usedLSQ) { 1263 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1264 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1265 } 1266 1267 if (fromCommit->commitInfo[tid].usedROB) { 1268 freeEntries[tid].robEntries = 1269 fromCommit->commitInfo[tid].freeROBEntries; 1270 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1271 } 1272 1273 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1274 "Free LQ: %i, Free SQ: %i\n", 1275 tid, 1276 freeEntries[tid].iqEntries, 1277 freeEntries[tid].robEntries, 1278 freeEntries[tid].lqEntries, 1279 freeEntries[tid].sqEntries); 1280 1281 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1282 tid, instsInProgress[tid]); 1283} 1284 1285template <class Impl> 1286bool 1287DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1288{ 1289 // Check if there's a squash signal, squash if there is 1290 // Check stall signals, block if necessary. 1291 // If status was blocked 1292 // check if stall conditions have passed 1293 // if so then go to unblocking 1294 // If status was Squashing 1295 // check if squashing is not high. Switch to running this cycle. 1296 // If status was serialize stall 1297 // check if ROB is empty and no insts are in flight to the ROB 1298 1299 readFreeEntries(tid); 1300 readStallSignals(tid); 1301 1302 if (fromCommit->commitInfo[tid].squash) { 1303 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1304 "commit.\n", tid); 1305 1306 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1307 1308 return true; 1309 } 1310 1311 if (checkStall(tid)) { 1312 return block(tid); 1313 } 1314 1315 if (renameStatus[tid] == Blocked) { 1316 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1317 tid); 1318 1319 renameStatus[tid] = Unblocking; 1320 1321 unblock(tid); 1322 1323 return true; 1324 } 1325 1326 if (renameStatus[tid] == Squashing) { 1327 // Switch status to running if rename isn't being told to block or 1328 // squash this cycle. 1329 if (resumeSerialize) { 1330 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1331 tid); 1332 1333 renameStatus[tid] = SerializeStall; 1334 return true; 1335 } else if (resumeUnblocking) { 1336 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1337 tid); 1338 renameStatus[tid] = Unblocking; 1339 return true; 1340 } else { 1341 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1342 tid); 1343 1344 renameStatus[tid] = Running; 1345 return false; 1346 } 1347 } 1348 1349 if (renameStatus[tid] == SerializeStall) { 1350 // Stall ends once the ROB is free. 1351 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1352 "unblocking.\n", tid); 1353 1354 DynInstPtr serial_inst = serializeInst[tid]; 1355 1356 renameStatus[tid] = Unblocking; 1357 1358 unblock(tid); 1359 1360 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1361 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1362 1363 // Put instruction into queue here. 1364 serial_inst->clearSerializeBefore(); 1365 1366 if (!skidBuffer[tid].empty()) { 1367 skidBuffer[tid].push_front(serial_inst); 1368 } else { 1369 insts[tid].push_front(serial_inst); 1370 } 1371 1372 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1373 " Adding to front of list.\n", tid); 1374 1375 serializeInst[tid] = NULL; 1376 1377 return true; 1378 } 1379 1380 // If we've reached this point, we have not gotten any signals that 1381 // cause rename to change its status. Rename remains the same as before. 1382 return false; 1383} 1384 1385template<class Impl> 1386void 1387DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1388{ 1389 if (inst_list.empty()) { 1390 // Mark a bit to say that I must serialize on the next instruction. 1391 serializeOnNextInst[tid] = true; 1392 return; 1393 } 1394 1395 // Set the next instruction as serializing. 1396 inst_list.front()->setSerializeBefore(); 1397} 1398 1399template <class Impl> 1400inline void 1401DefaultRename<Impl>::incrFullStat(const FullSource &source) 1402{ 1403 switch (source) { 1404 case ROB: 1405 ++renameROBFullEvents; 1406 break; 1407 case IQ: 1408 ++renameIQFullEvents; 1409 break; 1410 case LQ: 1411 ++renameLQFullEvents; 1412 break; 1413 case SQ: 1414 ++renameSQFullEvents; 1415 break; 1416 default: 1417 panic("Rename full stall stat should be incremented for a reason!"); 1418 break; 1419 } 1420} 1421 1422template <class Impl> 1423void 1424DefaultRename<Impl>::dumpHistory() 1425{ 1426 typename std::list<RenameHistory>::iterator buf_it; 1427 1428 for (ThreadID tid = 0; tid < numThreads; tid++) { 1429 1430 buf_it = historyBuffer[tid].begin(); 1431 1432 while (buf_it != historyBuffer[tid].end()) { 1433 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1434 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1435 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1436 1437 buf_it++; 1438 } 1439 } 1440} 1441 1442#endif//__CPU_O3_RENAME_IMPL_HH__ 1443