rename_impl.hh revision 10172
12SN/A/* 21762SN/A * Copyright (c) 2010-2012 ARM Limited 32SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 42SN/A * All rights reserved. 52SN/A * 62SN/A * The license below extends only to copyright in the software and shall 72SN/A * not be construed as granting a license to any other intellectual 82SN/A * property including but not limited to intellectual property relating 92SN/A * to a hardware implementation of the functionality of the software 102SN/A * licensed hereunder. You may use the software subject to the license 112SN/A * terms below provided that you ensure that this notice is replicated 122SN/A * unmodified and in its entirety in all distributions of the software, 132SN/A * modified or unmodified, in source code or in binary form. 142SN/A * 152SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316216Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322439SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336216Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34146SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35146SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36146SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37146SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38146SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39146SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 401717SN/A * 41146SN/A * Authors: Kevin Lim 426216Snate@binkert.org * Korey Sewell 431717SN/A */ 44146SN/A 451977SN/A#ifndef __CPU_O3_RENAME_IMPL_HH__ 462623SN/A#define __CPU_O3_RENAME_IMPL_HH__ 472683Sktlim@umich.edu 481717SN/A#include <list> 49146SN/A 502683Sktlim@umich.edu#include "arch/isa_traits.hh" 513348Sbinkertn@umich.edu#include "arch/registers.hh" 526105Ssteve.reinhardt@amd.com#include "config/the_isa.hh" 536216Snate@binkert.org#include "cpu/o3/rename.hh" 542036SN/A#include "cpu/reg_class.hh" 55146SN/A#include "debug/Activity.hh" 5656SN/A#include "debug/Rename.hh" 5756SN/A#include "debug/O3PipeView.hh" 58695SN/A#include "params/DerivO3CPU.hh" 592901Ssaidi@eecs.umich.edu 602SN/Ausing namespace std; 611858SN/A 623565Sgblack@eecs.umich.edutemplate <class Impl> 633565Sgblack@eecs.umich.eduDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 642171SN/A : cpu(_cpu), 652170SN/A iewToRenameDelay(params->iewToRenameDelay), 663562Sgblack@eecs.umich.edu decodeToRenameDelay(params->decodeToRenameDelay), 67146SN/A commitToRenameDelay(params->commitToRenameDelay), 682462SN/A renameWidth(params->renameWidth), 69146SN/A commitWidth(params->commitWidth), 702SN/A numThreads(params->numThreads), 712SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 722449SN/A + params->numPhysCCRegs) 731355SN/A{ 745529Snate@binkert.org if (renameWidth > Impl::MaxWidth) 754495Sacolyte@umich.edu fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 76224SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 771858SN/A renameWidth, static_cast<int>(Impl::MaxWidth)); 782683Sktlim@umich.edu 792420SN/A // @todo: Make into a parameter. 805529Snate@binkert.org skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 816331Sgblack@eecs.umich.edu} 822420SN/A 832SN/Atemplate <class Impl> 846029Ssteve.reinhardt@amd.comstd::string 852672Sktlim@umich.eduDefaultRename<Impl>::name() const 862683Sktlim@umich.edu{ 872SN/A return cpu->name() + ".rename"; 882SN/A} 89334SN/A 90140SN/Atemplate <class Impl> 91334SN/Avoid 922SN/ADefaultRename<Impl>::regStats() 932SN/A{ 942SN/A renameSquashCycles 952680Sktlim@umich.edu .name(name() + ".SquashCycles") 964377Sgblack@eecs.umich.edu .desc("Number of cycles rename is squashing") 975169Ssaidi@eecs.umich.edu .prereq(renameSquashCycles); 984377Sgblack@eecs.umich.edu renameIdleCycles 994377Sgblack@eecs.umich.edu .name(name() + ".IdleCycles") 1002SN/A .desc("Number of cycles rename is idle") 1012SN/A .prereq(renameIdleCycles); 1022623SN/A renameBlockCycles 1032SN/A .name(name() + ".BlockCycles") 1042SN/A .desc("Number of cycles rename is blocking") 1052SN/A .prereq(renameBlockCycles); 106180SN/A renameSerializeStallCycles 1072623SN/A .name(name() + ".serializeStallCycles") 108393SN/A .desc("count of cycles rename stalled for serializing inst") 109393SN/A .flags(Stats::total); 110393SN/A renameRunCycles 111393SN/A .name(name() + ".RunCycles") 112384SN/A .desc("Number of cycles rename is running") 113384SN/A .prereq(renameIdleCycles); 114393SN/A renameUnblockCycles 1152623SN/A .name(name() + ".UnblockCycles") 116393SN/A .desc("Number of cycles rename is unblocking") 117393SN/A .prereq(renameUnblockCycles); 118393SN/A renameRenamedInsts 119393SN/A .name(name() + ".RenamedInsts") 120384SN/A .desc("Number of instructions processed by rename") 121189SN/A .prereq(renameRenamedInsts); 122189SN/A renameSquashedInsts 1232623SN/A .name(name() + ".SquashedInsts") 1242SN/A .desc("Number of squashed instructions processed by rename") 125729SN/A .prereq(renameSquashedInsts); 126334SN/A renameROBFullEvents 1272SN/A .name(name() + ".ROBFullEvents") 1282SN/A .desc("Number of times rename has blocked due to ROB full") 1292SN/A .prereq(renameROBFullEvents); 1302SN/A renameIQFullEvents 1312SN/A .name(name() + ".IQFullEvents") 1322SN/A .desc("Number of times rename has blocked due to IQ full") 1332SN/A .prereq(renameIQFullEvents); 1342SN/A renameLSQFullEvents 1352SN/A .name(name() + ".LSQFullEvents") 1362SN/A .desc("Number of times rename has blocked due to LSQ full") 1372SN/A .prereq(renameLSQFullEvents); 1382SN/A renameFullRegistersEvents 1391001SN/A .name(name() + ".FullRegisterEvents") 1401001SN/A .desc("Number of times there has been no free registers") 1411001SN/A .prereq(renameFullRegistersEvents); 1421001SN/A renameRenamedOperands 1431001SN/A .name(name() + ".RenamedOperands") 1442SN/A .desc("Number of destination operands rename has renamed") 1452SN/A .prereq(renameRenamedOperands); 1462SN/A renameRenameLookups 1472SN/A .name(name() + ".RenameLookups") 1482SN/A .desc("Number of register rename lookups that rename has made") 1492SN/A .prereq(renameRenameLookups); 1502SN/A renameCommittedMaps 1512SN/A .name(name() + ".CommittedMaps") 1522SN/A .desc("Number of HB maps that are committed") 1532SN/A .prereq(renameCommittedMaps); 1542SN/A renameUndoneMaps 1552SN/A .name(name() + ".UndoneMaps") 1562SN/A .desc("Number of HB maps that are undone due to squashing") 1572SN/A .prereq(renameUndoneMaps); 1582SN/A renamedSerializing 1592SN/A .name(name() + ".serializingInsts") 1602SN/A .desc("count of serializing insts renamed") 1612390SN/A .flags(Stats::total) 1622390SN/A ; 1632390SN/A renamedTempSerializing 1642390SN/A .name(name() + ".tempSerializingInsts") 1652390SN/A .desc("count of temporary serializing insts renamed") 1662390SN/A .flags(Stats::total) 1672390SN/A ; 1682390SN/A renameSkidInsts 1692390SN/A .name(name() + ".skidInsts") 1702390SN/A .desc("count of insts added to the skid buffer") 1712390SN/A .flags(Stats::total) 1722390SN/A ; 173385SN/A intRenameLookups 1742SN/A .name(name() + ".int_rename_lookups") 1752SN/A .desc("Number of integer rename lookups") 1762SN/A .prereq(intRenameLookups); 1772623SN/A fpRenameLookups 178334SN/A .name(name() + ".fp_rename_lookups") 1792361SN/A .desc("Number of floating rename lookups") 1805496Ssaidi@eecs.umich.edu .prereq(fpRenameLookups); 181334SN/A} 182334SN/A 183334SN/Atemplate <class Impl> 1842623SN/Avoid 1852SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1865496Ssaidi@eecs.umich.edu{ 187921SN/A timeBuffer = tb_ptr; 1882915Sktlim@umich.edu 1892915Sktlim@umich.edu // Setup wire to read information from time buffer, from IEW stage. 1902683Sktlim@umich.edu fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1912SN/A 1922SN/A // Setup wire to read infromation from time buffer, from commit stage. 1932SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1942623SN/A 1952SN/A // Setup wire to write information to previous stages. 1965496Ssaidi@eecs.umich.edu toDecode = timeBuffer->getWire(0); 197921SN/A} 1982915Sktlim@umich.edu 1992915Sktlim@umich.edutemplate <class Impl> 2002SN/Avoid 2012SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2022SN/A{ 2036221Snate@binkert.org renameQueue = rq_ptr; 2042SN/A 2052SN/A // Setup wire to write information to future stages. 2062SN/A toIEW = renameQueue->getWire(0); 207595SN/A} 2082623SN/A 209595SN/Atemplate <class Impl> 2102390SN/Avoid 2111080SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2126227Snate@binkert.org{ 2136227Snate@binkert.org decodeQueue = dq_ptr; 2141080SN/A 2151080SN/A // Setup wire to get information from decode. 2161080SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2171080SN/A} 2181080SN/A 2191121SN/Atemplate <class Impl> 2202107SN/Avoid 2211089SN/ADefaultRename<Impl>::startupStage() 2221089SN/A{ 2231080SN/A resetStage(); 2241080SN/A} 2251080SN/A 2261080SN/Atemplate <class Impl> 227595SN/Avoid 2282623SN/ADefaultRename<Impl>::resetStage() 2292683Sktlim@umich.edu{ 230595SN/A _status = Inactive; 2312090SN/A 2322683Sktlim@umich.edu resumeSerialize = false; 2332683Sktlim@umich.edu resumeUnblocking = false; 234595SN/A 2352205SN/A // Grab the number of free entries directly from the stages. 2362205SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2372683Sktlim@umich.edu renameStatus[tid] = Idle; 2382683Sktlim@umich.edu 239595SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 240595SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2412390SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2422423SN/A emptyROB[tid] = true; 2432390SN/A 244595SN/A stalls[tid].iew = false; 245595SN/A stalls[tid].commit = false; 246595SN/A serializeInst[tid] = NULL; 2472623SN/A 248595SN/A instsInProgress[tid] = 0; 2492390SN/A 2501080SN/A serializeOnNextInst[tid] = false; 2516227Snate@binkert.org } 2526227Snate@binkert.org} 2531080SN/A 2541080SN/Atemplate<class Impl> 255595SN/Avoid 2562683Sktlim@umich.eduDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2571080SN/A{ 2581080SN/A activeThreads = at_ptr; 2591080SN/A} 2601121SN/A 2612107SN/A 2621089SN/Atemplate <class Impl> 2631080SN/Avoid 2641089SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2651080SN/A{ 2661080SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 2671080SN/A renameMap[tid] = &rm_ptr[tid]; 268595SN/A} 2692683Sktlim@umich.edu 2701080SN/Atemplate <class Impl> 2712090SN/Avoid 2721080SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 273595SN/A{ 2742683Sktlim@umich.edu freeList = fl_ptr; 2752683Sktlim@umich.edu} 276595SN/A 2772683Sktlim@umich.edutemplate<class Impl> 2781098SN/Avoid 2791098SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2801098SN/A{ 2812683Sktlim@umich.edu scoreboard = _scoreboard; 2821098SN/A} 2831098SN/A 2841098SN/Atemplate <class Impl> 2856105Ssteve.reinhardt@amd.combool 2861098SN/ADefaultRename<Impl>::isDrained() const 2871098SN/A{ 288595SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2892205SN/A if (instsInProgress[tid] != 0 || 2902205SN/A !historyBuffer[tid].empty() || 2912205SN/A !skidBuffer[tid].empty() || 292595SN/A !insts[tid].empty()) 2932390SN/A return false; 2942420SN/A } 2952423SN/A return true; 2962390SN/A} 297595SN/A 298595SN/Atemplate <class Impl> 2991858SN/Avoid 3002SN/ADefaultRename<Impl>::takeOverFrom() 3012623SN/A{ 3022SN/A resetStage(); 3032680Sktlim@umich.edu} 3042SN/A 3052SN/Atemplate <class Impl> 3062SN/Avoid 3071858SN/ADefaultRename<Impl>::drainSanityCheck() const 3082SN/A{ 3095807Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3102SN/A assert(historyBuffer[tid].empty()); 3115807Snate@binkert.org assert(insts[tid].empty()); 3125807Snate@binkert.org assert(skidBuffer[tid].empty()); 3132SN/A assert(instsInProgress[tid] == 0); 3145807Snate@binkert.org } 3155807Snate@binkert.org} 3162SN/A 3172SN/Atemplate <class Impl> 3182SN/Avoid 3192SN/ADefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3202623SN/A{ 3212SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3221858SN/A 3235704Snate@binkert.org // Clear the stall signal if rename was blocked or unblocking before. 3245647Sgblack@eecs.umich.edu // If it still needs to block, the blocking should happen the next 3252SN/A // cycle and there should be space to hold everything due to the squash. 3263520Sgblack@eecs.umich.edu if (renameStatus[tid] == Blocked || 3275835Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3285647Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3293520Sgblack@eecs.umich.edu 3302SN/A resumeSerialize = false; 3312SN/A serializeInst[tid] = NULL; 3322SN/A } else if (renameStatus[tid] == SerializeStall) { 3332623SN/A if (serializeInst[tid]->seqNum <= squash_seq_num) { 3342SN/A DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3352623SN/A resumeSerialize = true; 3365894Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3372662Sstever@eecs.umich.edu } else { 3382623SN/A resumeSerialize = false; 3394514Ssaidi@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3404495Sacolyte@umich.edu 3412623SN/A serializeInst[tid] = NULL; 3423093Sksewell@umich.edu } 3434495Sacolyte@umich.edu } 3443093Sksewell@umich.edu 3453093Sksewell@umich.edu // Set the status to Squashing. 3464564Sgblack@eecs.umich.edu renameStatus[tid] = Squashing; 3472741Sksewell@umich.edu 3482741Sksewell@umich.edu // Squash any instructions from decode. 3492623SN/A for (int i=0; i<fromDecode->size; i++) { 3504564Sgblack@eecs.umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3516105Ssteve.reinhardt@amd.com fromDecode->insts[i]->seqNum > squash_seq_num) { 3522623SN/A fromDecode->insts[i]->setSquashed(); 3532623SN/A wroteToTimeBuffer = true; 3542623SN/A } 3552623SN/A 3562623SN/A } 3572623SN/A 3582SN/A // Clear the instruction list and skid buffer in case they have any 3592683Sktlim@umich.edu // insts in them. 3602427SN/A insts[tid].clear(); 3612683Sktlim@umich.edu 3622427SN/A // Clear the skid buffer in case it has any data in it. 3632SN/A skidBuffer[tid].clear(); 3642623SN/A 3652623SN/A doSquash(squash_seq_num, tid); 3662SN/A} 3672623SN/A 3682623SN/Atemplate <class Impl> 3694377Sgblack@eecs.umich.eduvoid 3705665Sgblack@eecs.umich.eduDefaultRename<Impl>::tick() 3714377Sgblack@eecs.umich.edu{ 3725665Sgblack@eecs.umich.edu wroteToTimeBuffer = false; 3735665Sgblack@eecs.umich.edu 3745665Sgblack@eecs.umich.edu blockThisCycle = false; 3755665Sgblack@eecs.umich.edu 3765665Sgblack@eecs.umich.edu bool status_change = false; 3774181Sgblack@eecs.umich.edu 3784181Sgblack@eecs.umich.edu toIEWIndex = 0; 3794181Sgblack@eecs.umich.edu 3804182Sgblack@eecs.umich.edu sortInsts(); 3814182Sgblack@eecs.umich.edu 3824182Sgblack@eecs.umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 3834593Sgblack@eecs.umich.edu list<ThreadID>::iterator end = activeThreads->end(); 3844593Sgblack@eecs.umich.edu 3854593Sgblack@eecs.umich.edu // Check stall and squash signals. 3864593Sgblack@eecs.umich.edu while (threads != end) { 3874593Sgblack@eecs.umich.edu ThreadID tid = *threads++; 3884377Sgblack@eecs.umich.edu 3894377Sgblack@eecs.umich.edu DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3904377Sgblack@eecs.umich.edu 3914377Sgblack@eecs.umich.edu status_change = checkSignalsAndUpdate(tid) || status_change; 3924377Sgblack@eecs.umich.edu 3934377Sgblack@eecs.umich.edu rename(status_change, tid); 3944377Sgblack@eecs.umich.edu } 3954377Sgblack@eecs.umich.edu 3964572Sacolyte@umich.edu if (status_change) { 3974572Sacolyte@umich.edu updateStatus(); 3984377Sgblack@eecs.umich.edu } 3994377Sgblack@eecs.umich.edu 4004377Sgblack@eecs.umich.edu if (wroteToTimeBuffer) { 4014377Sgblack@eecs.umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 4024181Sgblack@eecs.umich.edu cpu->activityThisCycle(); 4034181Sgblack@eecs.umich.edu } 4044181Sgblack@eecs.umich.edu 4054539Sgblack@eecs.umich.edu threads = activeThreads->begin(); 4063276Sgblack@eecs.umich.edu 4075665Sgblack@eecs.umich.edu while (threads != end) { 4083280Sgblack@eecs.umich.edu ThreadID tid = *threads++; 4093280Sgblack@eecs.umich.edu 4103276Sgblack@eecs.umich.edu // If we committed this cycle then doneSeqNum will be > 0 4113276Sgblack@eecs.umich.edu if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4123276Sgblack@eecs.umich.edu !fromCommit->commitInfo[tid].squash && 4135665Sgblack@eecs.umich.edu renameStatus[tid] != Squashing) { 4143276Sgblack@eecs.umich.edu 4153276Sgblack@eecs.umich.edu removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4164181Sgblack@eecs.umich.edu tid); 4174181Sgblack@eecs.umich.edu } 4184181Sgblack@eecs.umich.edu } 4194522Ssaidi@eecs.umich.edu 4205784Sgblack@eecs.umich.edu // @todo: make into updateProgress function 4215784Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 4225784Sgblack@eecs.umich.edu instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4232470SN/A 4244181Sgblack@eecs.umich.edu assert(instsInProgress[tid] >=0); 4254181Sgblack@eecs.umich.edu } 4264522Ssaidi@eecs.umich.edu 4272623SN/A} 4282623SN/A 4294181Sgblack@eecs.umich.edutemplate<class Impl> 4302623SN/Avoid 4314181Sgblack@eecs.umich.eduDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4322623SN/A{ 4332623SN/A // If status is Running or idle, 4342623SN/A // call renameInsts() 4352623SN/A // If status is Unblocking, 4362623SN/A // buffer any instructions coming from decode 4372623SN/A // continue trying to empty skid buffer 4385086Sgblack@eecs.umich.edu // check if stall conditions have passed 4393577Sgblack@eecs.umich.edu 4402683Sktlim@umich.edu if (renameStatus[tid] == Blocked) { 4415086Sgblack@eecs.umich.edu ++renameBlockCycles; 4422623SN/A } else if (renameStatus[tid] == Squashing) { 4432683Sktlim@umich.edu ++renameSquashCycles; 4442623SN/A } else if (renameStatus[tid] == SerializeStall) { 4452420SN/A ++renameSerializeStallCycles; 4462SN/A // If we are currently in SerializeStall and resumeSerialize 4472623SN/A // was set, then that means that we are resuming serializing 4482623SN/A // this cycle. Tell the previous stages to block. 4492SN/A if (resumeSerialize) { 4502SN/A resumeSerialize = false; 4512623SN/A block(tid); 4522623SN/A toDecode->renameUnblock[tid] = false; 4532623SN/A } 4542623SN/A } else if (renameStatus[tid] == Unblocking) { 4552SN/A if (resumeUnblocking) { 4565953Ssaidi@eecs.umich.edu block(tid); 4575953Ssaidi@eecs.umich.edu resumeUnblocking = false; 4585953Ssaidi@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4595953Ssaidi@eecs.umich.edu } 4602683Sktlim@umich.edu } 4612644Sstever@eecs.umich.edu 4622644Sstever@eecs.umich.edu if (renameStatus[tid] == Running || 4634046Sbinkertn@umich.edu renameStatus[tid] == Idle) { 4644046Sbinkertn@umich.edu DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4654046Sbinkertn@umich.edu "stage.\n", tid); 4662644Sstever@eecs.umich.edu 4672623SN/A renameInsts(tid); 4682SN/A } else if (renameStatus[tid] == Unblocking) { 4692SN/A renameInsts(tid); 4702623SN/A 4712623SN/A if (validInsts()) { 4722623SN/A // Add the current inputs to the skid buffer so they can be 4734377Sgblack@eecs.umich.edu // reprocessed when this stage unblocks. 4744377Sgblack@eecs.umich.edu skidInsert(tid); 4752090SN/A } 4763905Ssaidi@eecs.umich.edu 4775120Sgblack@eecs.umich.edu // If we switched over to blocking, then there's a potential for 4785281Sgblack@eecs.umich.edu // an overall status change. 4794377Sgblack@eecs.umich.edu status_change = unblock(tid) || status_change || blockThisCycle; 4803276Sgblack@eecs.umich.edu } 4814539Sgblack@eecs.umich.edu} 4825665Sgblack@eecs.umich.edu 4835665Sgblack@eecs.umich.edutemplate <class Impl> 4845665Sgblack@eecs.umich.eduvoid 4853276Sgblack@eecs.umich.eduDefaultRename<Impl>::renameInsts(ThreadID tid) 4863276Sgblack@eecs.umich.edu{ 4873280Sgblack@eecs.umich.edu // Instructions can be either in the skid buffer or the queue of 4885665Sgblack@eecs.umich.edu // instructions coming from decode, depending on the status. 4895665Sgblack@eecs.umich.edu int insts_available = renameStatus[tid] == Unblocking ? 4903276Sgblack@eecs.umich.edu skidBuffer[tid].size() : insts[tid].size(); 4913276Sgblack@eecs.umich.edu 4925665Sgblack@eecs.umich.edu // Check the decode queue to see if instructions are available. 4933276Sgblack@eecs.umich.edu // If there are no available instructions to rename, then do nothing. 4943280Sgblack@eecs.umich.edu if (insts_available == 0) { 4953276Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4963276Sgblack@eecs.umich.edu tid); 4973280Sgblack@eecs.umich.edu // Should I change status to idle? 4983276Sgblack@eecs.umich.edu ++renameIdleCycles; 4993276Sgblack@eecs.umich.edu return; 5003276Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 5013276Sgblack@eecs.umich.edu ++renameUnblockCycles; 5023276Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Running) { 5033276Sgblack@eecs.umich.edu ++renameRunCycles; 5043276Sgblack@eecs.umich.edu } 5052SN/A 5062SN/A DynInstPtr inst; 5072SN/A 5085250Sksewell@umich.edu // Will have to do a different calculation for the number of free 5095222Sksewell@umich.edu // entries. 5105222Sksewell@umich.edu int free_rob_entries = calcFreeROBEntries(tid); 5115222Sksewell@umich.edu int free_iq_entries = calcFreeIQEntries(tid); 5125222Sksewell@umich.edu int free_lsq_entries = calcFreeLSQEntries(tid); 5135222Sksewell@umich.edu int min_free_entries = free_rob_entries; 5145222Sksewell@umich.edu 5155222Sksewell@umich.edu FullSource source = ROB; 5165222Sksewell@umich.edu 5175222Sksewell@umich.edu if (free_iq_entries < min_free_entries) { 5185222Sksewell@umich.edu min_free_entries = free_iq_entries; 5195222Sksewell@umich.edu source = IQ; 5205222Sksewell@umich.edu } 5215222Sksewell@umich.edu 5225222Sksewell@umich.edu if (free_lsq_entries < min_free_entries) { 5235222Sksewell@umich.edu min_free_entries = free_lsq_entries; 5245222Sksewell@umich.edu source = LSQ; 5255222Sksewell@umich.edu } 5265222Sksewell@umich.edu 5275222Sksewell@umich.edu // Check if there's any space left. 5285222Sksewell@umich.edu if (min_free_entries <= 0) { 5295222Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5305222Sksewell@umich.edu "entries.\n" 5315222Sksewell@umich.edu "ROB has %i free entries.\n" 5325222Sksewell@umich.edu "IQ has %i free entries.\n" 5335222Sksewell@umich.edu "LSQ has %i free entries.\n", 5345222Sksewell@umich.edu tid, 5355222Sksewell@umich.edu free_rob_entries, 5365222Sksewell@umich.edu free_iq_entries, 5375222Sksewell@umich.edu free_lsq_entries); 5385222Sksewell@umich.edu 5395222Sksewell@umich.edu blockThisCycle = true; 5405222Sksewell@umich.edu 5415250Sksewell@umich.edu block(tid); 542 543 incrFullStat(source); 544 545 return; 546 } else if (min_free_entries < insts_available) { 547 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 548 "%i insts available, but only %i insts can be " 549 "renamed due to ROB/IQ/LSQ limits.\n", 550 tid, insts_available, min_free_entries); 551 552 insts_available = min_free_entries; 553 554 blockThisCycle = true; 555 556 incrFullStat(source); 557 } 558 559 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 560 skidBuffer[tid] : insts[tid]; 561 562 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 563 "send iew.\n", tid, insts_available); 564 565 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 566 "dispatched to IQ last cycle.\n", 567 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 568 569 // Handle serializing the next instruction if necessary. 570 if (serializeOnNextInst[tid]) { 571 if (emptyROB[tid] && instsInProgress[tid] == 0) { 572 // ROB already empty; no need to serialize. 573 serializeOnNextInst[tid] = false; 574 } else if (!insts_to_rename.empty()) { 575 insts_to_rename.front()->setSerializeBefore(); 576 } 577 } 578 579 int renamed_insts = 0; 580 581 while (insts_available > 0 && toIEWIndex < renameWidth) { 582 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 583 584 assert(!insts_to_rename.empty()); 585 586 inst = insts_to_rename.front(); 587 588 insts_to_rename.pop_front(); 589 590 if (renameStatus[tid] == Unblocking) { 591 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 592 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 593 } 594 595 if (inst->isSquashed()) { 596 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 597 "squashed, skipping.\n", tid, inst->seqNum, 598 inst->pcState()); 599 600 ++renameSquashedInsts; 601 602 // Decrement how many instructions are available. 603 --insts_available; 604 605 continue; 606 } 607 608 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 609 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 610 611 // Check here to make sure there are enough destination registers 612 // to rename to. Otherwise block. 613 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 614 DPRINTF(Rename, "Blocking due to lack of free " 615 "physical registers to rename to.\n"); 616 blockThisCycle = true; 617 insts_to_rename.push_front(inst); 618 ++renameFullRegistersEvents; 619 620 break; 621 } 622 623 // Handle serializeAfter/serializeBefore instructions. 624 // serializeAfter marks the next instruction as serializeBefore. 625 // serializeBefore makes the instruction wait in rename until the ROB 626 // is empty. 627 628 // In this model, IPR accesses are serialize before 629 // instructions, and store conditionals are serialize after 630 // instructions. This is mainly due to lack of support for 631 // out-of-order operations of either of those classes of 632 // instructions. 633 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 634 !inst->isSerializeHandled()) { 635 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 636 637 if (!inst->isTempSerializeBefore()) { 638 renamedSerializing++; 639 inst->setSerializeHandled(); 640 } else { 641 renamedTempSerializing++; 642 } 643 644 // Change status over to SerializeStall so that other stages know 645 // what this is blocked on. 646 renameStatus[tid] = SerializeStall; 647 648 serializeInst[tid] = inst; 649 650 blockThisCycle = true; 651 652 break; 653 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 654 !inst->isSerializeHandled()) { 655 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 656 657 renamedSerializing++; 658 659 inst->setSerializeHandled(); 660 661 serializeAfter(insts_to_rename, tid); 662 } 663 664 renameSrcRegs(inst, inst->threadNumber); 665 666 renameDestRegs(inst, inst->threadNumber); 667 668 ++renamed_insts; 669 670 671 // Put instruction in rename queue. 672 toIEW->insts[toIEWIndex] = inst; 673 ++(toIEW->size); 674 675 // Increment which instruction we're on. 676 ++toIEWIndex; 677 678 // Decrement how many instructions are available. 679 --insts_available; 680 } 681 682 instsInProgress[tid] += renamed_insts; 683 renameRenamedInsts += renamed_insts; 684 685 // If we wrote to the time buffer, record this. 686 if (toIEWIndex) { 687 wroteToTimeBuffer = true; 688 } 689 690 // Check if there's any instructions left that haven't yet been renamed. 691 // If so then block. 692 if (insts_available) { 693 blockThisCycle = true; 694 } 695 696 if (blockThisCycle) { 697 block(tid); 698 toDecode->renameUnblock[tid] = false; 699 } 700} 701 702template<class Impl> 703void 704DefaultRename<Impl>::skidInsert(ThreadID tid) 705{ 706 DynInstPtr inst = NULL; 707 708 while (!insts[tid].empty()) { 709 inst = insts[tid].front(); 710 711 insts[tid].pop_front(); 712 713 assert(tid == inst->threadNumber); 714 715 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 716 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 717 718 ++renameSkidInsts; 719 720 skidBuffer[tid].push_back(inst); 721 } 722 723 if (skidBuffer[tid].size() > skidBufferMax) 724 { 725 typename InstQueue::iterator it; 726 warn("Skidbuffer contents:\n"); 727 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 728 { 729 warn("[tid:%u]: %s [sn:%i].\n", tid, 730 (*it)->staticInst->disassemble(inst->instAddr()), 731 (*it)->seqNum); 732 } 733 panic("Skidbuffer Exceeded Max Size"); 734 } 735} 736 737template <class Impl> 738void 739DefaultRename<Impl>::sortInsts() 740{ 741 int insts_from_decode = fromDecode->size; 742 for (int i = 0; i < insts_from_decode; ++i) { 743 DynInstPtr inst = fromDecode->insts[i]; 744 insts[inst->threadNumber].push_back(inst); 745#if TRACING_ON 746 if (DTRACE(O3PipeView)) { 747 inst->renameTick = curTick() - inst->fetchTick; 748 } 749#endif 750 } 751} 752 753template<class Impl> 754bool 755DefaultRename<Impl>::skidsEmpty() 756{ 757 list<ThreadID>::iterator threads = activeThreads->begin(); 758 list<ThreadID>::iterator end = activeThreads->end(); 759 760 while (threads != end) { 761 ThreadID tid = *threads++; 762 763 if (!skidBuffer[tid].empty()) 764 return false; 765 } 766 767 return true; 768} 769 770template<class Impl> 771void 772DefaultRename<Impl>::updateStatus() 773{ 774 bool any_unblocking = false; 775 776 list<ThreadID>::iterator threads = activeThreads->begin(); 777 list<ThreadID>::iterator end = activeThreads->end(); 778 779 while (threads != end) { 780 ThreadID tid = *threads++; 781 782 if (renameStatus[tid] == Unblocking) { 783 any_unblocking = true; 784 break; 785 } 786 } 787 788 // Rename will have activity if it's unblocking. 789 if (any_unblocking) { 790 if (_status == Inactive) { 791 _status = Active; 792 793 DPRINTF(Activity, "Activating stage.\n"); 794 795 cpu->activateStage(O3CPU::RenameIdx); 796 } 797 } else { 798 // If it's not unblocking, then rename will not have any internal 799 // activity. Switch it to inactive. 800 if (_status == Active) { 801 _status = Inactive; 802 DPRINTF(Activity, "Deactivating stage.\n"); 803 804 cpu->deactivateStage(O3CPU::RenameIdx); 805 } 806 } 807} 808 809template <class Impl> 810bool 811DefaultRename<Impl>::block(ThreadID tid) 812{ 813 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 814 815 // Add the current inputs onto the skid buffer, so they can be 816 // reprocessed when this stage unblocks. 817 skidInsert(tid); 818 819 // Only signal backwards to block if the previous stages do not think 820 // rename is already blocked. 821 if (renameStatus[tid] != Blocked) { 822 // If resumeUnblocking is set, we unblocked during the squash, 823 // but now we're have unblocking status. We need to tell earlier 824 // stages to block. 825 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 826 toDecode->renameBlock[tid] = true; 827 toDecode->renameUnblock[tid] = false; 828 wroteToTimeBuffer = true; 829 } 830 831 // Rename can not go from SerializeStall to Blocked, otherwise 832 // it would not know to complete the serialize stall. 833 if (renameStatus[tid] != SerializeStall) { 834 // Set status to Blocked. 835 renameStatus[tid] = Blocked; 836 return true; 837 } 838 } 839 840 return false; 841} 842 843template <class Impl> 844bool 845DefaultRename<Impl>::unblock(ThreadID tid) 846{ 847 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 848 849 // Rename is done unblocking if the skid buffer is empty. 850 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 851 852 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 853 854 toDecode->renameUnblock[tid] = true; 855 wroteToTimeBuffer = true; 856 857 renameStatus[tid] = Running; 858 return true; 859 } 860 861 return false; 862} 863 864template <class Impl> 865void 866DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 867{ 868 typename std::list<RenameHistory>::iterator hb_it = 869 historyBuffer[tid].begin(); 870 871 // After a syscall squashes everything, the history buffer may be empty 872 // but the ROB may still be squashing instructions. 873 if (historyBuffer[tid].empty()) { 874 return; 875 } 876 877 // Go through the most recent instructions, undoing the mappings 878 // they did and freeing up the registers. 879 while (!historyBuffer[tid].empty() && 880 hb_it->instSeqNum > squashed_seq_num) { 881 assert(hb_it != historyBuffer[tid].end()); 882 883 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 884 "number %i.\n", tid, hb_it->instSeqNum); 885 886 // Undo the rename mapping only if it was really a change. 887 // Special regs that are not really renamed (like misc regs 888 // and the zero reg) can be recognized because the new mapping 889 // is the same as the old one. While it would be merely a 890 // waste of time to update the rename table, we definitely 891 // don't want to put these on the free list. 892 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 893 // Tell the rename map to set the architected register to the 894 // previous physical register that it was renamed to. 895 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 896 897 // Put the renamed physical register back on the free list. 898 freeList->addReg(hb_it->newPhysReg); 899 } 900 901 historyBuffer[tid].erase(hb_it++); 902 903 ++renameUndoneMaps; 904 } 905} 906 907template<class Impl> 908void 909DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 910{ 911 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 912 "history buffer %u (size=%i), until [sn:%lli].\n", 913 tid, tid, historyBuffer[tid].size(), inst_seq_num); 914 915 typename std::list<RenameHistory>::iterator hb_it = 916 historyBuffer[tid].end(); 917 918 --hb_it; 919 920 if (historyBuffer[tid].empty()) { 921 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 922 return; 923 } else if (hb_it->instSeqNum > inst_seq_num) { 924 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 925 "that a syscall happened recently.\n", tid); 926 return; 927 } 928 929 // Commit all the renames up until (and including) the committed sequence 930 // number. Some or even all of the committed instructions may not have 931 // rename histories if they did not have destination registers that were 932 // renamed. 933 while (!historyBuffer[tid].empty() && 934 hb_it != historyBuffer[tid].end() && 935 hb_it->instSeqNum <= inst_seq_num) { 936 937 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 938 "[sn:%lli].\n", 939 tid, hb_it->prevPhysReg, hb_it->instSeqNum); 940 941 // Don't free special phys regs like misc and zero regs, which 942 // can be recognized because the new mapping is the same as 943 // the old one. 944 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 945 freeList->addReg(hb_it->prevPhysReg); 946 } 947 948 ++renameCommittedMaps; 949 950 historyBuffer[tid].erase(hb_it--); 951 } 952} 953 954template <class Impl> 955inline void 956DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 957{ 958 ThreadContext *tc = inst->tcBase(); 959 RenameMap *map = renameMap[tid]; 960 unsigned num_src_regs = inst->numSrcRegs(); 961 962 // Get the architectual register numbers from the source and 963 // operands, and redirect them to the right physical register. 964 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 965 RegIndex src_reg = inst->srcRegIdx(src_idx); 966 RegIndex rel_src_reg; 967 RegIndex flat_rel_src_reg; 968 PhysRegIndex renamed_reg; 969 970 switch (regIdxToClass(src_reg, &rel_src_reg)) { 971 case IntRegClass: 972 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 973 renamed_reg = map->lookupInt(flat_rel_src_reg); 974 intRenameLookups++; 975 break; 976 977 case FloatRegClass: 978 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 979 renamed_reg = map->lookupFloat(flat_rel_src_reg); 980 fpRenameLookups++; 981 break; 982 983 case CCRegClass: 984 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 985 renamed_reg = map->lookupCC(flat_rel_src_reg); 986 break; 987 988 case MiscRegClass: 989 // misc regs don't get flattened 990 flat_rel_src_reg = rel_src_reg; 991 renamed_reg = map->lookupMisc(flat_rel_src_reg); 992 break; 993 994 default: 995 panic("Reg index is out of bound: %d.", src_reg); 996 } 997 998 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 999 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 1000 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); 1001 1002 inst->renameSrcReg(src_idx, renamed_reg); 1003 1004 // See if the register is ready or not. 1005 if (scoreboard->getReg(renamed_reg)) { 1006 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1007 tid, renamed_reg); 1008 1009 inst->markSrcRegReady(src_idx); 1010 } else { 1011 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1012 tid, renamed_reg); 1013 } 1014 1015 ++renameRenameLookups; 1016 } 1017} 1018 1019template <class Impl> 1020inline void 1021DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1022{ 1023 ThreadContext *tc = inst->tcBase(); 1024 RenameMap *map = renameMap[tid]; 1025 unsigned num_dest_regs = inst->numDestRegs(); 1026 1027 // Rename the destination registers. 1028 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1029 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1030 RegIndex rel_dest_reg; 1031 RegIndex flat_rel_dest_reg; 1032 RegIndex flat_uni_dest_reg; 1033 typename RenameMap::RenameInfo rename_result; 1034 1035 switch (regIdxToClass(dest_reg, &rel_dest_reg)) { 1036 case IntRegClass: 1037 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 1038 rename_result = map->renameInt(flat_rel_dest_reg); 1039 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping 1040 break; 1041 1042 case FloatRegClass: 1043 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1044 rename_result = map->renameFloat(flat_rel_dest_reg); 1045 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 1046 break; 1047 1048 case CCRegClass: 1049 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 1050 rename_result = map->renameCC(flat_rel_dest_reg); 1051 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 1052 break; 1053 1054 case MiscRegClass: 1055 // misc regs don't get flattened 1056 flat_rel_dest_reg = rel_dest_reg; 1057 rename_result = map->renameMisc(flat_rel_dest_reg); 1058 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 1059 break; 1060 1061 default: 1062 panic("Reg index is out of bound: %d.", dest_reg); 1063 } 1064 1065 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1066 1067 // Mark Scoreboard entry as not ready 1068 scoreboard->unsetReg(rename_result.first); 1069 1070 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1071 "reg %i.\n", tid, (int)flat_rel_dest_reg, 1072 (int)rename_result.first); 1073 1074 // Record the rename information so that a history can be kept. 1075 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1076 rename_result.first, 1077 rename_result.second); 1078 1079 historyBuffer[tid].push_front(hb_entry); 1080 1081 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1082 "(size=%i), [sn:%lli].\n",tid, 1083 historyBuffer[tid].size(), 1084 (*historyBuffer[tid].begin()).instSeqNum); 1085 1086 // Tell the instruction to rename the appropriate destination 1087 // register (dest_idx) to the new physical register 1088 // (rename_result.first), and record the previous physical 1089 // register that the same logical register was renamed to 1090 // (rename_result.second). 1091 inst->renameDestReg(dest_idx, 1092 rename_result.first, 1093 rename_result.second); 1094 1095 ++renameRenamedOperands; 1096 } 1097} 1098 1099template <class Impl> 1100inline int 1101DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1102{ 1103 int num_free = freeEntries[tid].robEntries - 1104 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1105 1106 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1107 1108 return num_free; 1109} 1110 1111template <class Impl> 1112inline int 1113DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1114{ 1115 int num_free = freeEntries[tid].iqEntries - 1116 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1117 1118 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1119 1120 return num_free; 1121} 1122 1123template <class Impl> 1124inline int 1125DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 1126{ 1127 int num_free = freeEntries[tid].lsqEntries - 1128 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1129 1130 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1131 1132 return num_free; 1133} 1134 1135template <class Impl> 1136unsigned 1137DefaultRename<Impl>::validInsts() 1138{ 1139 unsigned inst_count = 0; 1140 1141 for (int i=0; i<fromDecode->size; i++) { 1142 if (!fromDecode->insts[i]->isSquashed()) 1143 inst_count++; 1144 } 1145 1146 return inst_count; 1147} 1148 1149template <class Impl> 1150void 1151DefaultRename<Impl>::readStallSignals(ThreadID tid) 1152{ 1153 if (fromIEW->iewBlock[tid]) { 1154 stalls[tid].iew = true; 1155 } 1156 1157 if (fromIEW->iewUnblock[tid]) { 1158 assert(stalls[tid].iew); 1159 stalls[tid].iew = false; 1160 } 1161 1162 if (fromCommit->commitBlock[tid]) { 1163 stalls[tid].commit = true; 1164 } 1165 1166 if (fromCommit->commitUnblock[tid]) { 1167 assert(stalls[tid].commit); 1168 stalls[tid].commit = false; 1169 } 1170} 1171 1172template <class Impl> 1173bool 1174DefaultRename<Impl>::checkStall(ThreadID tid) 1175{ 1176 bool ret_val = false; 1177 1178 if (stalls[tid].iew) { 1179 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1180 ret_val = true; 1181 } else if (stalls[tid].commit) { 1182 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1183 ret_val = true; 1184 } else if (calcFreeROBEntries(tid) <= 0) { 1185 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1186 ret_val = true; 1187 } else if (calcFreeIQEntries(tid) <= 0) { 1188 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1189 ret_val = true; 1190 } else if (calcFreeLSQEntries(tid) <= 0) { 1191 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1192 ret_val = true; 1193 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1194 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1195 ret_val = true; 1196 } else if (renameStatus[tid] == SerializeStall && 1197 (!emptyROB[tid] || instsInProgress[tid])) { 1198 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1199 "empty.\n", 1200 tid); 1201 ret_val = true; 1202 } 1203 1204 return ret_val; 1205} 1206 1207template <class Impl> 1208void 1209DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1210{ 1211 if (fromIEW->iewInfo[tid].usedIQ) 1212 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1213 1214 if (fromIEW->iewInfo[tid].usedLSQ) 1215 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 1216 1217 if (fromCommit->commitInfo[tid].usedROB) { 1218 freeEntries[tid].robEntries = 1219 fromCommit->commitInfo[tid].freeROBEntries; 1220 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1221 } 1222 1223 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1224 tid, 1225 freeEntries[tid].iqEntries, 1226 freeEntries[tid].robEntries, 1227 freeEntries[tid].lsqEntries); 1228 1229 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1230 tid, instsInProgress[tid]); 1231} 1232 1233template <class Impl> 1234bool 1235DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1236{ 1237 // Check if there's a squash signal, squash if there is 1238 // Check stall signals, block if necessary. 1239 // If status was blocked 1240 // check if stall conditions have passed 1241 // if so then go to unblocking 1242 // If status was Squashing 1243 // check if squashing is not high. Switch to running this cycle. 1244 // If status was serialize stall 1245 // check if ROB is empty and no insts are in flight to the ROB 1246 1247 readFreeEntries(tid); 1248 readStallSignals(tid); 1249 1250 if (fromCommit->commitInfo[tid].squash) { 1251 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1252 "commit.\n", tid); 1253 1254 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1255 1256 return true; 1257 } 1258 1259 if (fromCommit->commitInfo[tid].robSquashing) { 1260 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1261 1262 renameStatus[tid] = Squashing; 1263 1264 return true; 1265 } 1266 1267 if (checkStall(tid)) { 1268 return block(tid); 1269 } 1270 1271 if (renameStatus[tid] == Blocked) { 1272 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1273 tid); 1274 1275 renameStatus[tid] = Unblocking; 1276 1277 unblock(tid); 1278 1279 return true; 1280 } 1281 1282 if (renameStatus[tid] == Squashing) { 1283 // Switch status to running if rename isn't being told to block or 1284 // squash this cycle. 1285 if (resumeSerialize) { 1286 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1287 tid); 1288 1289 renameStatus[tid] = SerializeStall; 1290 return true; 1291 } else if (resumeUnblocking) { 1292 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1293 tid); 1294 renameStatus[tid] = Unblocking; 1295 return true; 1296 } else { 1297 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1298 tid); 1299 1300 renameStatus[tid] = Running; 1301 return false; 1302 } 1303 } 1304 1305 if (renameStatus[tid] == SerializeStall) { 1306 // Stall ends once the ROB is free. 1307 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1308 "unblocking.\n", tid); 1309 1310 DynInstPtr serial_inst = serializeInst[tid]; 1311 1312 renameStatus[tid] = Unblocking; 1313 1314 unblock(tid); 1315 1316 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1317 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1318 1319 // Put instruction into queue here. 1320 serial_inst->clearSerializeBefore(); 1321 1322 if (!skidBuffer[tid].empty()) { 1323 skidBuffer[tid].push_front(serial_inst); 1324 } else { 1325 insts[tid].push_front(serial_inst); 1326 } 1327 1328 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1329 " Adding to front of list.\n", tid); 1330 1331 serializeInst[tid] = NULL; 1332 1333 return true; 1334 } 1335 1336 // If we've reached this point, we have not gotten any signals that 1337 // cause rename to change its status. Rename remains the same as before. 1338 return false; 1339} 1340 1341template<class Impl> 1342void 1343DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1344{ 1345 if (inst_list.empty()) { 1346 // Mark a bit to say that I must serialize on the next instruction. 1347 serializeOnNextInst[tid] = true; 1348 return; 1349 } 1350 1351 // Set the next instruction as serializing. 1352 inst_list.front()->setSerializeBefore(); 1353} 1354 1355template <class Impl> 1356inline void 1357DefaultRename<Impl>::incrFullStat(const FullSource &source) 1358{ 1359 switch (source) { 1360 case ROB: 1361 ++renameROBFullEvents; 1362 break; 1363 case IQ: 1364 ++renameIQFullEvents; 1365 break; 1366 case LSQ: 1367 ++renameLSQFullEvents; 1368 break; 1369 default: 1370 panic("Rename full stall stat should be incremented for a reason!"); 1371 break; 1372 } 1373} 1374 1375template <class Impl> 1376void 1377DefaultRename<Impl>::dumpHistory() 1378{ 1379 typename std::list<RenameHistory>::iterator buf_it; 1380 1381 for (ThreadID tid = 0; tid < numThreads; tid++) { 1382 1383 buf_it = historyBuffer[tid].begin(); 1384 1385 while (buf_it != historyBuffer[tid].end()) { 1386 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1387 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1388 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1389 1390 buf_it++; 1391 } 1392 } 1393} 1394 1395#endif//__CPU_O3_RENAME_IMPL_HH__ 1396