rename_impl.hh revision 9913
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 451060SN/A#include <list> 461060SN/A 473773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 486329Sgblack@eecs.umich.edu#include "arch/registers.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 501717SN/A#include "cpu/o3/rename.hh" 519913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 528232Snate@binkert.org#include "debug/Activity.hh" 538232Snate@binkert.org#include "debug/Rename.hh" 549527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 555529Snate@binkert.org#include "params/DerivO3CPU.hh" 561060SN/A 576221Snate@binkert.orgusing namespace std; 586221Snate@binkert.org 591061SN/Atemplate <class Impl> 605529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 614329Sktlim@umich.edu : cpu(_cpu), 624329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 632292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 642292SN/A commitToRenameDelay(params->commitToRenameDelay), 652292SN/A renameWidth(params->renameWidth), 662292SN/A commitWidth(params->commitWidth), 675529Snate@binkert.org numThreads(params->numThreads), 682361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 691060SN/A{ 702292SN/A // @todo: Make into a parameter. 718907Slukefahr@umich.edu skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 722292SN/A} 732292SN/A 742292SN/Atemplate <class Impl> 752292SN/Astd::string 762292SN/ADefaultRename<Impl>::name() const 772292SN/A{ 782292SN/A return cpu->name() + ".rename"; 791060SN/A} 801060SN/A 811061SN/Atemplate <class Impl> 821060SN/Avoid 832292SN/ADefaultRename<Impl>::regStats() 841062SN/A{ 851062SN/A renameSquashCycles 868240Snate@binkert.org .name(name() + ".SquashCycles") 871062SN/A .desc("Number of cycles rename is squashing") 881062SN/A .prereq(renameSquashCycles); 891062SN/A renameIdleCycles 908240Snate@binkert.org .name(name() + ".IdleCycles") 911062SN/A .desc("Number of cycles rename is idle") 921062SN/A .prereq(renameIdleCycles); 931062SN/A renameBlockCycles 948240Snate@binkert.org .name(name() + ".BlockCycles") 951062SN/A .desc("Number of cycles rename is blocking") 961062SN/A .prereq(renameBlockCycles); 972301SN/A renameSerializeStallCycles 988240Snate@binkert.org .name(name() + ".serializeStallCycles") 992301SN/A .desc("count of cycles rename stalled for serializing inst") 1002301SN/A .flags(Stats::total); 1012292SN/A renameRunCycles 1028240Snate@binkert.org .name(name() + ".RunCycles") 1032292SN/A .desc("Number of cycles rename is running") 1042292SN/A .prereq(renameIdleCycles); 1051062SN/A renameUnblockCycles 1068240Snate@binkert.org .name(name() + ".UnblockCycles") 1071062SN/A .desc("Number of cycles rename is unblocking") 1081062SN/A .prereq(renameUnblockCycles); 1091062SN/A renameRenamedInsts 1108240Snate@binkert.org .name(name() + ".RenamedInsts") 1111062SN/A .desc("Number of instructions processed by rename") 1121062SN/A .prereq(renameRenamedInsts); 1131062SN/A renameSquashedInsts 1148240Snate@binkert.org .name(name() + ".SquashedInsts") 1151062SN/A .desc("Number of squashed instructions processed by rename") 1161062SN/A .prereq(renameSquashedInsts); 1171062SN/A renameROBFullEvents 1188240Snate@binkert.org .name(name() + ".ROBFullEvents") 1192292SN/A .desc("Number of times rename has blocked due to ROB full") 1201062SN/A .prereq(renameROBFullEvents); 1211062SN/A renameIQFullEvents 1228240Snate@binkert.org .name(name() + ".IQFullEvents") 1232292SN/A .desc("Number of times rename has blocked due to IQ full") 1241062SN/A .prereq(renameIQFullEvents); 1252292SN/A renameLSQFullEvents 1268240Snate@binkert.org .name(name() + ".LSQFullEvents") 1272292SN/A .desc("Number of times rename has blocked due to LSQ full") 1282292SN/A .prereq(renameLSQFullEvents); 1291062SN/A renameFullRegistersEvents 1308240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1311062SN/A .desc("Number of times there has been no free registers") 1321062SN/A .prereq(renameFullRegistersEvents); 1331062SN/A renameRenamedOperands 1348240Snate@binkert.org .name(name() + ".RenamedOperands") 1351062SN/A .desc("Number of destination operands rename has renamed") 1361062SN/A .prereq(renameRenamedOperands); 1371062SN/A renameRenameLookups 1388240Snate@binkert.org .name(name() + ".RenameLookups") 1391062SN/A .desc("Number of register rename lookups that rename has made") 1401062SN/A .prereq(renameRenameLookups); 1411062SN/A renameCommittedMaps 1428240Snate@binkert.org .name(name() + ".CommittedMaps") 1431062SN/A .desc("Number of HB maps that are committed") 1441062SN/A .prereq(renameCommittedMaps); 1451062SN/A renameUndoneMaps 1468240Snate@binkert.org .name(name() + ".UndoneMaps") 1471062SN/A .desc("Number of HB maps that are undone due to squashing") 1481062SN/A .prereq(renameUndoneMaps); 1492301SN/A renamedSerializing 1508240Snate@binkert.org .name(name() + ".serializingInsts") 1512301SN/A .desc("count of serializing insts renamed") 1522301SN/A .flags(Stats::total) 1532301SN/A ; 1542301SN/A renamedTempSerializing 1558240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1562301SN/A .desc("count of temporary serializing insts renamed") 1572301SN/A .flags(Stats::total) 1582301SN/A ; 1592307SN/A renameSkidInsts 1608240Snate@binkert.org .name(name() + ".skidInsts") 1612307SN/A .desc("count of insts added to the skid buffer") 1622307SN/A .flags(Stats::total) 1632307SN/A ; 1647897Shestness@cs.utexas.edu intRenameLookups 1658240Snate@binkert.org .name(name() + ".int_rename_lookups") 1667897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1677897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1687897Shestness@cs.utexas.edu fpRenameLookups 1698240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1707897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1717897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1721062SN/A} 1731062SN/A 1741062SN/Atemplate <class Impl> 1751062SN/Avoid 1762292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1771060SN/A{ 1781060SN/A timeBuffer = tb_ptr; 1791060SN/A 1801060SN/A // Setup wire to read information from time buffer, from IEW stage. 1811060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1821060SN/A 1831060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1841060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1851060SN/A 1861060SN/A // Setup wire to write information to previous stages. 1871060SN/A toDecode = timeBuffer->getWire(0); 1881060SN/A} 1891060SN/A 1901061SN/Atemplate <class Impl> 1911060SN/Avoid 1922292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1931060SN/A{ 1941060SN/A renameQueue = rq_ptr; 1951060SN/A 1961060SN/A // Setup wire to write information to future stages. 1971060SN/A toIEW = renameQueue->getWire(0); 1981060SN/A} 1991060SN/A 2001061SN/Atemplate <class Impl> 2011060SN/Avoid 2022292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2031060SN/A{ 2041060SN/A decodeQueue = dq_ptr; 2051060SN/A 2061060SN/A // Setup wire to get information from decode. 2071060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2081060SN/A} 2091060SN/A 2101061SN/Atemplate <class Impl> 2111060SN/Avoid 2129427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2131060SN/A{ 2149444SAndreas.Sandberg@ARM.com resetStage(); 2159444SAndreas.Sandberg@ARM.com} 2169444SAndreas.Sandberg@ARM.com 2179444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2189444SAndreas.Sandberg@ARM.comvoid 2199444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2209444SAndreas.Sandberg@ARM.com{ 2219444SAndreas.Sandberg@ARM.com _status = Inactive; 2229444SAndreas.Sandberg@ARM.com 2239444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2249444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2259444SAndreas.Sandberg@ARM.com 2262329SN/A // Grab the number of free entries directly from the stages. 2276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2289444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2299444SAndreas.Sandberg@ARM.com 2302292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2312292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2322292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2332292SN/A emptyROB[tid] = true; 2349444SAndreas.Sandberg@ARM.com 2359444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2369444SAndreas.Sandberg@ARM.com stalls[tid].commit = false; 2379444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2389444SAndreas.Sandberg@ARM.com 2399444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 2409444SAndreas.Sandberg@ARM.com 2419444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2422292SN/A } 2431060SN/A} 2441060SN/A 2452292SN/Atemplate<class Impl> 2462292SN/Avoid 2476221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2482292SN/A{ 2492292SN/A activeThreads = at_ptr; 2502292SN/A} 2512292SN/A 2522292SN/A 2531061SN/Atemplate <class Impl> 2541060SN/Avoid 2552292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2561060SN/A{ 2576221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2586221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2591060SN/A} 2601060SN/A 2611061SN/Atemplate <class Impl> 2621060SN/Avoid 2632292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2641060SN/A{ 2652292SN/A freeList = fl_ptr; 2662292SN/A} 2671060SN/A 2682292SN/Atemplate<class Impl> 2692292SN/Avoid 2702292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2712292SN/A{ 2722292SN/A scoreboard = _scoreboard; 2731060SN/A} 2741060SN/A 2751061SN/Atemplate <class Impl> 2762863Sktlim@umich.edubool 2779444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 2781060SN/A{ 2799444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 2809444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 2819444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 2829444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 2839444SAndreas.Sandberg@ARM.com !insts[tid].empty()) 2849444SAndreas.Sandberg@ARM.com return false; 2859444SAndreas.Sandberg@ARM.com } 2862863Sktlim@umich.edu return true; 2872316SN/A} 2881060SN/A 2892316SN/Atemplate <class Impl> 2902316SN/Avoid 2912307SN/ADefaultRename<Impl>::takeOverFrom() 2921060SN/A{ 2939444SAndreas.Sandberg@ARM.com resetStage(); 2949444SAndreas.Sandberg@ARM.com} 2951060SN/A 2969444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2979444SAndreas.Sandberg@ARM.comvoid 2989444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 2999444SAndreas.Sandberg@ARM.com{ 3006221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3019444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3029444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3039444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3049444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3052307SN/A } 3062307SN/A} 3072307SN/A 3082307SN/Atemplate <class Impl> 3092307SN/Avoid 3106221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3111858SN/A{ 3122292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3131858SN/A 3142292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3152292SN/A // If it still needs to block, the blocking should happen the next 3162292SN/A // cycle and there should be space to hold everything due to the squash. 3172292SN/A if (renameStatus[tid] == Blocked || 3183788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3192292SN/A toDecode->renameUnblock[tid] = 1; 3202698Sktlim@umich.edu 3213788Sgblack@eecs.umich.edu resumeSerialize = false; 3222301SN/A serializeInst[tid] = NULL; 3233788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3243788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3253788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3263788Sgblack@eecs.umich.edu resumeSerialize = true; 3273788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3283788Sgblack@eecs.umich.edu } else { 3293788Sgblack@eecs.umich.edu resumeSerialize = false; 3303788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3313788Sgblack@eecs.umich.edu 3323788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3333788Sgblack@eecs.umich.edu } 3342292SN/A } 3352292SN/A 3362292SN/A // Set the status to Squashing. 3372292SN/A renameStatus[tid] = Squashing; 3382292SN/A 3392329SN/A // Squash any instructions from decode. 3402292SN/A unsigned squashCount = 0; 3412292SN/A 3422292SN/A for (int i=0; i<fromDecode->size; i++) { 3432935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3442935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3452731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3462292SN/A wroteToTimeBuffer = true; 3472292SN/A squashCount++; 3482292SN/A } 3492935Sksewell@umich.edu 3502292SN/A } 3512292SN/A 3522935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3534632Sgblack@eecs.umich.edu // insts in them. 3543093Sksewell@umich.edu insts[tid].clear(); 3552292SN/A 3562292SN/A // Clear the skid buffer in case it has any data in it. 3573093Sksewell@umich.edu skidBuffer[tid].clear(); 3584632Sgblack@eecs.umich.edu 3592935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3602292SN/A} 3612292SN/A 3622292SN/Atemplate <class Impl> 3632292SN/Avoid 3642292SN/ADefaultRename<Impl>::tick() 3652292SN/A{ 3662292SN/A wroteToTimeBuffer = false; 3672292SN/A 3682292SN/A blockThisCycle = false; 3692292SN/A 3702292SN/A bool status_change = false; 3712292SN/A 3722292SN/A toIEWIndex = 0; 3732292SN/A 3742292SN/A sortInsts(); 3752292SN/A 3766221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3776221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3782292SN/A 3792292SN/A // Check stall and squash signals. 3803867Sbinkertn@umich.edu while (threads != end) { 3816221Snate@binkert.org ThreadID tid = *threads++; 3822292SN/A 3832292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3842292SN/A 3852292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3862292SN/A 3872292SN/A rename(status_change, tid); 3882292SN/A } 3892292SN/A 3902292SN/A if (status_change) { 3912292SN/A updateStatus(); 3922292SN/A } 3932292SN/A 3942292SN/A if (wroteToTimeBuffer) { 3952292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 3962292SN/A cpu->activityThisCycle(); 3972292SN/A } 3982292SN/A 3993867Sbinkertn@umich.edu threads = activeThreads->begin(); 4002292SN/A 4013867Sbinkertn@umich.edu while (threads != end) { 4026221Snate@binkert.org ThreadID tid = *threads++; 4032292SN/A 4042292SN/A // If we committed this cycle then doneSeqNum will be > 0 4052292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4062292SN/A !fromCommit->commitInfo[tid].squash && 4072292SN/A renameStatus[tid] != Squashing) { 4082292SN/A 4092292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4102292SN/A tid); 4112292SN/A } 4122292SN/A } 4132292SN/A 4142292SN/A // @todo: make into updateProgress function 4156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4162292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4172292SN/A 4182292SN/A assert(instsInProgress[tid] >=0); 4192292SN/A } 4202292SN/A 4212292SN/A} 4222292SN/A 4232292SN/Atemplate<class Impl> 4242292SN/Avoid 4256221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4262292SN/A{ 4272292SN/A // If status is Running or idle, 4282292SN/A // call renameInsts() 4292292SN/A // If status is Unblocking, 4302292SN/A // buffer any instructions coming from decode 4312292SN/A // continue trying to empty skid buffer 4322292SN/A // check if stall conditions have passed 4332292SN/A 4342292SN/A if (renameStatus[tid] == Blocked) { 4352292SN/A ++renameBlockCycles; 4362292SN/A } else if (renameStatus[tid] == Squashing) { 4372292SN/A ++renameSquashCycles; 4382301SN/A } else if (renameStatus[tid] == SerializeStall) { 4392301SN/A ++renameSerializeStallCycles; 4403788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4413788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4423788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4433788Sgblack@eecs.umich.edu if (resumeSerialize) { 4443788Sgblack@eecs.umich.edu resumeSerialize = false; 4453788Sgblack@eecs.umich.edu block(tid); 4463788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4473788Sgblack@eecs.umich.edu } 4483798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4493798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4503798Sgblack@eecs.umich.edu block(tid); 4513798Sgblack@eecs.umich.edu resumeUnblocking = false; 4523798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4533798Sgblack@eecs.umich.edu } 4542292SN/A } 4552292SN/A 4562292SN/A if (renameStatus[tid] == Running || 4572292SN/A renameStatus[tid] == Idle) { 4582292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4592292SN/A "stage.\n", tid); 4602292SN/A 4612292SN/A renameInsts(tid); 4622292SN/A } else if (renameStatus[tid] == Unblocking) { 4632292SN/A renameInsts(tid); 4642292SN/A 4652292SN/A if (validInsts()) { 4662292SN/A // Add the current inputs to the skid buffer so they can be 4672292SN/A // reprocessed when this stage unblocks. 4682292SN/A skidInsert(tid); 4692292SN/A } 4702292SN/A 4712292SN/A // If we switched over to blocking, then there's a potential for 4722292SN/A // an overall status change. 4732292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4741858SN/A } 4751858SN/A} 4761858SN/A 4771858SN/Atemplate <class Impl> 4781858SN/Avoid 4796221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 4801858SN/A{ 4812292SN/A // Instructions can be either in the skid buffer or the queue of 4822292SN/A // instructions coming from decode, depending on the status. 4832292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4842292SN/A skidBuffer[tid].size() : insts[tid].size(); 4851858SN/A 4862292SN/A // Check the decode queue to see if instructions are available. 4872292SN/A // If there are no available instructions to rename, then do nothing. 4882292SN/A if (insts_available == 0) { 4892292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4902292SN/A tid); 4912292SN/A // Should I change status to idle? 4922292SN/A ++renameIdleCycles; 4932292SN/A return; 4942292SN/A } else if (renameStatus[tid] == Unblocking) { 4952292SN/A ++renameUnblockCycles; 4962292SN/A } else if (renameStatus[tid] == Running) { 4972292SN/A ++renameRunCycles; 4982292SN/A } 4991858SN/A 5002292SN/A DynInstPtr inst; 5012292SN/A 5022292SN/A // Will have to do a different calculation for the number of free 5032292SN/A // entries. 5042292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5052292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5062292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5072292SN/A int min_free_entries = free_rob_entries; 5082292SN/A 5092292SN/A FullSource source = ROB; 5102292SN/A 5112292SN/A if (free_iq_entries < min_free_entries) { 5122292SN/A min_free_entries = free_iq_entries; 5132292SN/A source = IQ; 5142292SN/A } 5152292SN/A 5162292SN/A if (free_lsq_entries < min_free_entries) { 5172292SN/A min_free_entries = free_lsq_entries; 5182292SN/A source = LSQ; 5192292SN/A } 5202292SN/A 5212292SN/A // Check if there's any space left. 5222292SN/A if (min_free_entries <= 0) { 5232292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5242292SN/A "entries.\n" 5252292SN/A "ROB has %i free entries.\n" 5262292SN/A "IQ has %i free entries.\n" 5272292SN/A "LSQ has %i free entries.\n", 5282292SN/A tid, 5292292SN/A free_rob_entries, 5302292SN/A free_iq_entries, 5312292SN/A free_lsq_entries); 5322292SN/A 5332292SN/A blockThisCycle = true; 5342292SN/A 5352292SN/A block(tid); 5362292SN/A 5372292SN/A incrFullStat(source); 5382292SN/A 5392292SN/A return; 5402292SN/A } else if (min_free_entries < insts_available) { 5412292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5422292SN/A "%i insts available, but only %i insts can be " 5432292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5442292SN/A tid, insts_available, min_free_entries); 5452292SN/A 5462292SN/A insts_available = min_free_entries; 5472292SN/A 5482292SN/A blockThisCycle = true; 5492292SN/A 5502292SN/A incrFullStat(source); 5512292SN/A } 5522292SN/A 5532292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5542292SN/A skidBuffer[tid] : insts[tid]; 5552292SN/A 5562292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5572292SN/A "send iew.\n", tid, insts_available); 5582292SN/A 5592292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5602292SN/A "dispatched to IQ last cycle.\n", 5612292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5622292SN/A 5632292SN/A // Handle serializing the next instruction if necessary. 5642292SN/A if (serializeOnNextInst[tid]) { 5652292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5662292SN/A // ROB already empty; no need to serialize. 5672292SN/A serializeOnNextInst[tid] = false; 5682292SN/A } else if (!insts_to_rename.empty()) { 5692292SN/A insts_to_rename.front()->setSerializeBefore(); 5702292SN/A } 5712292SN/A } 5722292SN/A 5732292SN/A int renamed_insts = 0; 5742292SN/A 5752292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5762292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5772292SN/A 5782292SN/A assert(!insts_to_rename.empty()); 5792292SN/A 5802292SN/A inst = insts_to_rename.front(); 5812292SN/A 5822292SN/A insts_to_rename.pop_front(); 5832292SN/A 5842292SN/A if (renameStatus[tid] == Unblocking) { 5857720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 5867720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 5872292SN/A } 5882292SN/A 5892292SN/A if (inst->isSquashed()) { 5907720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 5917720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 5927720Sgblack@eecs.umich.edu inst->pcState()); 5932292SN/A 5942292SN/A ++renameSquashedInsts; 5952292SN/A 5962292SN/A // Decrement how many instructions are available. 5972292SN/A --insts_available; 5982292SN/A 5992292SN/A continue; 6002292SN/A } 6012292SN/A 6022292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6037720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6042292SN/A 6059531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6069531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 6079531Sgeoffrey.blake@arm.com if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6089531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6099531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6109531Sgeoffrey.blake@arm.com blockThisCycle = true; 6119531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6129531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6139531Sgeoffrey.blake@arm.com 6149531Sgeoffrey.blake@arm.com break; 6159531Sgeoffrey.blake@arm.com } 6169531Sgeoffrey.blake@arm.com 6172292SN/A // Handle serializeAfter/serializeBefore instructions. 6182292SN/A // serializeAfter marks the next instruction as serializeBefore. 6192292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6202292SN/A // is empty. 6212336SN/A 6222336SN/A // In this model, IPR accesses are serialize before 6232336SN/A // instructions, and store conditionals are serialize after 6242336SN/A // instructions. This is mainly due to lack of support for 6252336SN/A // out-of-order operations of either of those classes of 6262336SN/A // instructions. 6272336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6282336SN/A !inst->isSerializeHandled()) { 6292292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6302292SN/A 6312301SN/A if (!inst->isTempSerializeBefore()) { 6322301SN/A renamedSerializing++; 6332292SN/A inst->setSerializeHandled(); 6342301SN/A } else { 6352301SN/A renamedTempSerializing++; 6362301SN/A } 6372292SN/A 6382301SN/A // Change status over to SerializeStall so that other stages know 6392292SN/A // what this is blocked on. 6402301SN/A renameStatus[tid] = SerializeStall; 6412292SN/A 6422301SN/A serializeInst[tid] = inst; 6432292SN/A 6442292SN/A blockThisCycle = true; 6452292SN/A 6462292SN/A break; 6472336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6482336SN/A !inst->isSerializeHandled()) { 6492292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6502292SN/A 6512307SN/A renamedSerializing++; 6522307SN/A 6532292SN/A inst->setSerializeHandled(); 6542292SN/A 6552292SN/A serializeAfter(insts_to_rename, tid); 6562292SN/A } 6572292SN/A 6582292SN/A renameSrcRegs(inst, inst->threadNumber); 6592292SN/A 6602292SN/A renameDestRegs(inst, inst->threadNumber); 6612292SN/A 6622292SN/A ++renamed_insts; 6632292SN/A 6648471SGiacomo.Gabrielli@arm.com 6652292SN/A // Put instruction in rename queue. 6662292SN/A toIEW->insts[toIEWIndex] = inst; 6672292SN/A ++(toIEW->size); 6682292SN/A 6692292SN/A // Increment which instruction we're on. 6702292SN/A ++toIEWIndex; 6712292SN/A 6722292SN/A // Decrement how many instructions are available. 6732292SN/A --insts_available; 6742292SN/A } 6752292SN/A 6762292SN/A instsInProgress[tid] += renamed_insts; 6772307SN/A renameRenamedInsts += renamed_insts; 6782292SN/A 6792292SN/A // If we wrote to the time buffer, record this. 6802292SN/A if (toIEWIndex) { 6812292SN/A wroteToTimeBuffer = true; 6822292SN/A } 6832292SN/A 6842292SN/A // Check if there's any instructions left that haven't yet been renamed. 6852292SN/A // If so then block. 6862292SN/A if (insts_available) { 6872292SN/A blockThisCycle = true; 6882292SN/A } 6892292SN/A 6902292SN/A if (blockThisCycle) { 6912292SN/A block(tid); 6922292SN/A toDecode->renameUnblock[tid] = false; 6932292SN/A } 6942292SN/A} 6952292SN/A 6962292SN/Atemplate<class Impl> 6972292SN/Avoid 6986221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 6992292SN/A{ 7002292SN/A DynInstPtr inst = NULL; 7012292SN/A 7022292SN/A while (!insts[tid].empty()) { 7032292SN/A inst = insts[tid].front(); 7042292SN/A 7052292SN/A insts[tid].pop_front(); 7062292SN/A 7072292SN/A assert(tid == inst->threadNumber); 7082292SN/A 7097720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7107720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7112292SN/A 7122307SN/A ++renameSkidInsts; 7132307SN/A 7142292SN/A skidBuffer[tid].push_back(inst); 7152292SN/A } 7162292SN/A 7172292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7183798Sgblack@eecs.umich.edu { 7193798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7203798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7213798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7223798Sgblack@eecs.umich.edu { 7233798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7247720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7253798Sgblack@eecs.umich.edu (*it)->seqNum); 7263798Sgblack@eecs.umich.edu } 7272292SN/A panic("Skidbuffer Exceeded Max Size"); 7283798Sgblack@eecs.umich.edu } 7292292SN/A} 7302292SN/A 7312292SN/Atemplate <class Impl> 7322292SN/Avoid 7332292SN/ADefaultRename<Impl>::sortInsts() 7342292SN/A{ 7352292SN/A int insts_from_decode = fromDecode->size; 7362292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7372292SN/A DynInstPtr inst = fromDecode->insts[i]; 7382292SN/A insts[inst->threadNumber].push_back(inst); 7399527SMatt.Horsnell@arm.com#if TRACING_ON 7409527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7419527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 7429527SMatt.Horsnell@arm.com } 7439527SMatt.Horsnell@arm.com#endif 7442292SN/A } 7452292SN/A} 7462292SN/A 7472292SN/Atemplate<class Impl> 7482292SN/Abool 7492292SN/ADefaultRename<Impl>::skidsEmpty() 7502292SN/A{ 7516221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7526221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7532292SN/A 7543867Sbinkertn@umich.edu while (threads != end) { 7556221Snate@binkert.org ThreadID tid = *threads++; 7563867Sbinkertn@umich.edu 7573867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7582292SN/A return false; 7592292SN/A } 7602292SN/A 7612292SN/A return true; 7622292SN/A} 7632292SN/A 7642292SN/Atemplate<class Impl> 7652292SN/Avoid 7662292SN/ADefaultRename<Impl>::updateStatus() 7672292SN/A{ 7682292SN/A bool any_unblocking = false; 7692292SN/A 7706221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7716221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7722292SN/A 7733867Sbinkertn@umich.edu while (threads != end) { 7746221Snate@binkert.org ThreadID tid = *threads++; 7752292SN/A 7762292SN/A if (renameStatus[tid] == Unblocking) { 7772292SN/A any_unblocking = true; 7782292SN/A break; 7792292SN/A } 7802292SN/A } 7812292SN/A 7822292SN/A // Rename will have activity if it's unblocking. 7832292SN/A if (any_unblocking) { 7842292SN/A if (_status == Inactive) { 7852292SN/A _status = Active; 7862292SN/A 7872292SN/A DPRINTF(Activity, "Activating stage.\n"); 7882292SN/A 7892733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7902292SN/A } 7912292SN/A } else { 7922292SN/A // If it's not unblocking, then rename will not have any internal 7932292SN/A // activity. Switch it to inactive. 7942292SN/A if (_status == Active) { 7952292SN/A _status = Inactive; 7962292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 7972292SN/A 7982733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 7992292SN/A } 8002292SN/A } 8012292SN/A} 8022292SN/A 8032292SN/Atemplate <class Impl> 8042292SN/Abool 8056221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8062292SN/A{ 8072292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8082292SN/A 8092292SN/A // Add the current inputs onto the skid buffer, so they can be 8102292SN/A // reprocessed when this stage unblocks. 8112292SN/A skidInsert(tid); 8122292SN/A 8132292SN/A // Only signal backwards to block if the previous stages do not think 8142292SN/A // rename is already blocked. 8152292SN/A if (renameStatus[tid] != Blocked) { 8163798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8173798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8183798Sgblack@eecs.umich.edu // stages to block. 8193798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8202292SN/A toDecode->renameBlock[tid] = true; 8212292SN/A toDecode->renameUnblock[tid] = false; 8222292SN/A wroteToTimeBuffer = true; 8232292SN/A } 8242292SN/A 8252329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8262329SN/A // it would not know to complete the serialize stall. 8272301SN/A if (renameStatus[tid] != SerializeStall) { 8282292SN/A // Set status to Blocked. 8292292SN/A renameStatus[tid] = Blocked; 8302292SN/A return true; 8312292SN/A } 8322292SN/A } 8332292SN/A 8342292SN/A return false; 8352292SN/A} 8362292SN/A 8372292SN/Atemplate <class Impl> 8382292SN/Abool 8396221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8402292SN/A{ 8412292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8422292SN/A 8432292SN/A // Rename is done unblocking if the skid buffer is empty. 8442301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8452292SN/A 8462292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8472292SN/A 8482292SN/A toDecode->renameUnblock[tid] = true; 8492292SN/A wroteToTimeBuffer = true; 8502292SN/A 8512292SN/A renameStatus[tid] = Running; 8522292SN/A return true; 8532292SN/A } 8542292SN/A 8552292SN/A return false; 8562292SN/A} 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Avoid 8606221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8612292SN/A{ 8622980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8632980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8642292SN/A 8651060SN/A // After a syscall squashes everything, the history buffer may be empty 8661060SN/A // but the ROB may still be squashing instructions. 8672292SN/A if (historyBuffer[tid].empty()) { 8681060SN/A return; 8691060SN/A } 8701060SN/A 8711060SN/A // Go through the most recent instructions, undoing the mappings 8721060SN/A // they did and freeing up the registers. 8732292SN/A while (!historyBuffer[tid].empty() && 8742292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8752292SN/A assert(hb_it != historyBuffer[tid].end()); 8761062SN/A 8772292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8782292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8791060SN/A 8802292SN/A // Tell the rename map to set the architected register to the 8812292SN/A // previous physical register that it was renamed to. 8822292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8831060SN/A 8842292SN/A // Put the renamed physical register back on the free list. 8852292SN/A freeList->addReg(hb_it->newPhysReg); 8861062SN/A 8872367SN/A // Be sure to mark its register as ready if it's a misc register. 8882367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 8892367SN/A scoreboard->setReg(hb_it->newPhysReg); 8902367SN/A } 8912367SN/A 8922292SN/A historyBuffer[tid].erase(hb_it++); 8931061SN/A 8941062SN/A ++renameUndoneMaps; 8951060SN/A } 8961060SN/A} 8971060SN/A 8981060SN/Atemplate<class Impl> 8991060SN/Avoid 9006221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9011060SN/A{ 9022292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9032292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9042292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9052292SN/A 9062980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9072980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9081060SN/A 9091061SN/A --hb_it; 9101060SN/A 9112292SN/A if (historyBuffer[tid].empty()) { 9122292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9132292SN/A return; 9142292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9152292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9162292SN/A "that a syscall happened recently.\n", tid); 9171060SN/A return; 9181060SN/A } 9191060SN/A 9202292SN/A // Commit all the renames up until (and including) the committed sequence 9212292SN/A // number. Some or even all of the committed instructions may not have 9222292SN/A // rename histories if they did not have destination registers that were 9232292SN/A // renamed. 9242292SN/A while (!historyBuffer[tid].empty() && 9252292SN/A hb_it != historyBuffer[tid].end() && 9262292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9271060SN/A 9282329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9292329SN/A "[sn:%lli].\n", 9302292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9311061SN/A 9322292SN/A freeList->addReg((*hb_it).prevPhysReg); 9332292SN/A ++renameCommittedMaps; 9341061SN/A 9352292SN/A historyBuffer[tid].erase(hb_it--); 9361060SN/A } 9371060SN/A} 9381060SN/A 9391061SN/Atemplate <class Impl> 9401061SN/Ainline void 9416221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9421061SN/A{ 9432292SN/A assert(renameMap[tid] != 0); 9442292SN/A 9451061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9461061SN/A 9471061SN/A // Get the architectual register numbers from the source and 9481061SN/A // destination operands, and redirect them to the right register. 9491061SN/A // Will need to mark dependencies though. 9502292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9511061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9523773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9539913Ssteve.reinhardt@amd.com switch (regIdxToClass(src_reg)) { 9549913Ssteve.reinhardt@amd.com case IntRegClass: 9556313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 9567767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9577767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9589913Ssteve.reinhardt@amd.com break; 9599913Ssteve.reinhardt@amd.com 9609913Ssteve.reinhardt@amd.com case FloatRegClass: 9615082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9626313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 9637767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9647767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9655082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9669913Ssteve.reinhardt@amd.com break; 9679913Ssteve.reinhardt@amd.com 9689913Ssteve.reinhardt@amd.com case MiscRegClass: 9697767Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 9707767Sgblack@eecs.umich.edu TheISA::NumFloatRegs + TheISA::NumIntRegs; 9717767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 9727767Sgblack@eecs.umich.edu src_reg, flat_src_reg); 9739913Ssteve.reinhardt@amd.com break; 9749913Ssteve.reinhardt@amd.com 9759913Ssteve.reinhardt@amd.com default: 9767649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9773773Sgblack@eecs.umich.edu } 9784352Sgblack@eecs.umich.edu 9791061SN/A // Look up the source registers to get the phys. register they've 9801061SN/A // been renamed to, and set the sources to those registers. 9813773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 9821061SN/A 9832292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9843773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 9852292SN/A (int)renamed_reg); 9861061SN/A 9871061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9881061SN/A 9892292SN/A // See if the register is ready or not. 9902292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9917767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 9927767Sgblack@eecs.umich.edu tid, renamed_reg); 9931061SN/A 9941061SN/A inst->markSrcRegReady(src_idx); 9954636Sgblack@eecs.umich.edu } else { 9967767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 9977767Sgblack@eecs.umich.edu tid, renamed_reg); 9981061SN/A } 9991062SN/A 10001062SN/A ++renameRenameLookups; 10017897Shestness@cs.utexas.edu inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 10021061SN/A } 10031061SN/A} 10041061SN/A 10051061SN/Atemplate <class Impl> 10061061SN/Ainline void 10076221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10081061SN/A{ 10092292SN/A typename RenameMap::RenameInfo rename_result; 10101061SN/A 10111061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10121061SN/A 10132292SN/A // Rename the destination registers. 10142292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10152292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10163773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10179913Ssteve.reinhardt@amd.com switch (regIdxToClass(dest_reg)) { 10189913Ssteve.reinhardt@amd.com case IntRegClass: 10194352Sgblack@eecs.umich.edu // Integer registers are flattened. 10206313Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 10217767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10227767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10239913Ssteve.reinhardt@amd.com break; 10249913Ssteve.reinhardt@amd.com 10259913Ssteve.reinhardt@amd.com case FloatRegClass: 10267767Sgblack@eecs.umich.edu dest_reg = dest_reg - TheISA::FP_Base_DepTag; 10277767Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 10287767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10297767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10307767Sgblack@eecs.umich.edu flat_dest_reg += TheISA::NumIntRegs; 10319913Ssteve.reinhardt@amd.com break; 10329913Ssteve.reinhardt@amd.com 10339913Ssteve.reinhardt@amd.com case MiscRegClass: 10344352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10354352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10367767Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 10377767Sgblack@eecs.umich.edu TheISA::NumIntRegs + TheISA::NumFloatRegs; 10387767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 10397767Sgblack@eecs.umich.edu dest_reg, flat_dest_reg); 10409913Ssteve.reinhardt@amd.com break; 10419913Ssteve.reinhardt@amd.com 10429913Ssteve.reinhardt@amd.com default: 10437649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10443773Sgblack@eecs.umich.edu } 10453773Sgblack@eecs.umich.edu 10463773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10471061SN/A 10482292SN/A // Get the physical register that the destination will be 10492292SN/A // renamed to. 10503773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10511061SN/A 10522292SN/A //Mark Scoreboard entry as not ready 10539913Ssteve.reinhardt@amd.com if (regIdxToClass(dest_reg) != MiscRegClass) 10547854SAli.Saidi@ARM.com scoreboard->unsetReg(rename_result.first); 10551062SN/A 10562292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10573773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10582292SN/A (int)rename_result.first); 10591062SN/A 10602292SN/A // Record the rename information so that a history can be kept. 10613773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10622292SN/A rename_result.first, 10632292SN/A rename_result.second); 10641062SN/A 10652292SN/A historyBuffer[tid].push_front(hb_entry); 10661062SN/A 10672935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10682935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10692935Sksewell@umich.edu historyBuffer[tid].size(), 10702292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10711062SN/A 10722292SN/A // Tell the instruction to rename the appropriate destination 10732292SN/A // register (dest_idx) to the new physical register 10742292SN/A // (rename_result.first), and record the previous physical 10752292SN/A // register that the same logical register was renamed to 10762292SN/A // (rename_result.second). 10772292SN/A inst->renameDestReg(dest_idx, 10782292SN/A rename_result.first, 10792292SN/A rename_result.second); 10801062SN/A 10812292SN/A ++renameRenamedOperands; 10821061SN/A } 10831061SN/A} 10841061SN/A 10851061SN/Atemplate <class Impl> 10861061SN/Ainline int 10876221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 10881061SN/A{ 10892292SN/A int num_free = freeEntries[tid].robEntries - 10902292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10912292SN/A 10922292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10932292SN/A 10942292SN/A return num_free; 10951061SN/A} 10961061SN/A 10971061SN/Atemplate <class Impl> 10981061SN/Ainline int 10996221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11001061SN/A{ 11012292SN/A int num_free = freeEntries[tid].iqEntries - 11022292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11032292SN/A 11042292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11052292SN/A 11062292SN/A return num_free; 11072292SN/A} 11082292SN/A 11092292SN/Atemplate <class Impl> 11102292SN/Ainline int 11116221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 11122292SN/A{ 11132292SN/A int num_free = freeEntries[tid].lsqEntries - 11142292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11152292SN/A 11162292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11172292SN/A 11182292SN/A return num_free; 11192292SN/A} 11202292SN/A 11212292SN/Atemplate <class Impl> 11222292SN/Aunsigned 11232292SN/ADefaultRename<Impl>::validInsts() 11242292SN/A{ 11252292SN/A unsigned inst_count = 0; 11262292SN/A 11272292SN/A for (int i=0; i<fromDecode->size; i++) { 11282731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11292292SN/A inst_count++; 11302292SN/A } 11312292SN/A 11322292SN/A return inst_count; 11332292SN/A} 11342292SN/A 11352292SN/Atemplate <class Impl> 11362292SN/Avoid 11376221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11382292SN/A{ 11392292SN/A if (fromIEW->iewBlock[tid]) { 11402292SN/A stalls[tid].iew = true; 11412292SN/A } 11422292SN/A 11432292SN/A if (fromIEW->iewUnblock[tid]) { 11442292SN/A assert(stalls[tid].iew); 11452292SN/A stalls[tid].iew = false; 11462292SN/A } 11472292SN/A 11482292SN/A if (fromCommit->commitBlock[tid]) { 11492292SN/A stalls[tid].commit = true; 11502292SN/A } 11512292SN/A 11522292SN/A if (fromCommit->commitUnblock[tid]) { 11532292SN/A assert(stalls[tid].commit); 11542292SN/A stalls[tid].commit = false; 11552292SN/A } 11562292SN/A} 11572292SN/A 11582292SN/Atemplate <class Impl> 11592292SN/Abool 11606221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11612292SN/A{ 11622292SN/A bool ret_val = false; 11632292SN/A 11642292SN/A if (stalls[tid].iew) { 11652292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11662292SN/A ret_val = true; 11672292SN/A } else if (stalls[tid].commit) { 11682292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11692292SN/A ret_val = true; 11702292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11712292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11722292SN/A ret_val = true; 11732292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11742292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11752292SN/A ret_val = true; 11762292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11772292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11782292SN/A ret_val = true; 11792292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11802292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11812292SN/A ret_val = true; 11822301SN/A } else if (renameStatus[tid] == SerializeStall && 11832292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11842301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11852292SN/A "empty.\n", 11862292SN/A tid); 11872292SN/A ret_val = true; 11882292SN/A } 11892292SN/A 11902292SN/A return ret_val; 11912292SN/A} 11922292SN/A 11932292SN/Atemplate <class Impl> 11942292SN/Avoid 11956221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 11962292SN/A{ 11978607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 11988607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 11992292SN/A 12008607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedLSQ) 12018607Sgblack@eecs.umich.edu freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 12022292SN/A 12032292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12042292SN/A freeEntries[tid].robEntries = 12052292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12062292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12072292SN/A } 12082292SN/A 12092292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12102292SN/A tid, 12112292SN/A freeEntries[tid].iqEntries, 12122292SN/A freeEntries[tid].robEntries, 12132292SN/A freeEntries[tid].lsqEntries); 12142292SN/A 12152292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12162292SN/A tid, instsInProgress[tid]); 12172292SN/A} 12182292SN/A 12192292SN/Atemplate <class Impl> 12202292SN/Abool 12216221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12222292SN/A{ 12232292SN/A // Check if there's a squash signal, squash if there is 12242292SN/A // Check stall signals, block if necessary. 12252292SN/A // If status was blocked 12262292SN/A // check if stall conditions have passed 12272292SN/A // if so then go to unblocking 12282292SN/A // If status was Squashing 12292292SN/A // check if squashing is not high. Switch to running this cycle. 12302301SN/A // If status was serialize stall 12312292SN/A // check if ROB is empty and no insts are in flight to the ROB 12322292SN/A 12332292SN/A readFreeEntries(tid); 12342292SN/A readStallSignals(tid); 12352292SN/A 12362292SN/A if (fromCommit->commitInfo[tid].squash) { 12372292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12382292SN/A "commit.\n", tid); 12392292SN/A 12404632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12412292SN/A 12422292SN/A return true; 12432292SN/A } 12442292SN/A 12452292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12462292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12472292SN/A 12482292SN/A renameStatus[tid] = Squashing; 12492292SN/A 12502292SN/A return true; 12512292SN/A } 12522292SN/A 12532292SN/A if (checkStall(tid)) { 12542292SN/A return block(tid); 12552292SN/A } 12562292SN/A 12572292SN/A if (renameStatus[tid] == Blocked) { 12582292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12592292SN/A tid); 12602292SN/A 12612292SN/A renameStatus[tid] = Unblocking; 12622292SN/A 12632292SN/A unblock(tid); 12642292SN/A 12652292SN/A return true; 12662292SN/A } 12672292SN/A 12682292SN/A if (renameStatus[tid] == Squashing) { 12692292SN/A // Switch status to running if rename isn't being told to block or 12702292SN/A // squash this cycle. 12713798Sgblack@eecs.umich.edu if (resumeSerialize) { 12723798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12733798Sgblack@eecs.umich.edu tid); 12742292SN/A 12753798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12763798Sgblack@eecs.umich.edu return true; 12773798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12783798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12793798Sgblack@eecs.umich.edu tid); 12803798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12813798Sgblack@eecs.umich.edu return true; 12823798Sgblack@eecs.umich.edu } else { 12833788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12843788Sgblack@eecs.umich.edu tid); 12852292SN/A 12863788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 12873788Sgblack@eecs.umich.edu return false; 12883788Sgblack@eecs.umich.edu } 12892292SN/A } 12902292SN/A 12912301SN/A if (renameStatus[tid] == SerializeStall) { 12922292SN/A // Stall ends once the ROB is free. 12932301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 12942292SN/A "unblocking.\n", tid); 12952292SN/A 12962301SN/A DynInstPtr serial_inst = serializeInst[tid]; 12972292SN/A 12982292SN/A renameStatus[tid] = Unblocking; 12992292SN/A 13002292SN/A unblock(tid); 13012292SN/A 13022292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13037720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13042292SN/A 13052292SN/A // Put instruction into queue here. 13062301SN/A serial_inst->clearSerializeBefore(); 13072292SN/A 13082292SN/A if (!skidBuffer[tid].empty()) { 13092301SN/A skidBuffer[tid].push_front(serial_inst); 13102292SN/A } else { 13112301SN/A insts[tid].push_front(serial_inst); 13122292SN/A } 13132292SN/A 13142292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13152703Sktlim@umich.edu " Adding to front of list.\n", tid); 13162292SN/A 13172301SN/A serializeInst[tid] = NULL; 13182292SN/A 13192292SN/A return true; 13202292SN/A } 13212292SN/A 13222292SN/A // If we've reached this point, we have not gotten any signals that 13232292SN/A // cause rename to change its status. Rename remains the same as before. 13242292SN/A return false; 13251061SN/A} 13261061SN/A 13271060SN/Atemplate<class Impl> 13281060SN/Avoid 13296221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13301060SN/A{ 13312292SN/A if (inst_list.empty()) { 13322292SN/A // Mark a bit to say that I must serialize on the next instruction. 13332292SN/A serializeOnNextInst[tid] = true; 13341060SN/A return; 13351060SN/A } 13361060SN/A 13372292SN/A // Set the next instruction as serializing. 13382292SN/A inst_list.front()->setSerializeBefore(); 13392292SN/A} 13402292SN/A 13412292SN/Atemplate <class Impl> 13422292SN/Ainline void 13432292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13442292SN/A{ 13452292SN/A switch (source) { 13462292SN/A case ROB: 13472292SN/A ++renameROBFullEvents; 13482292SN/A break; 13492292SN/A case IQ: 13502292SN/A ++renameIQFullEvents; 13512292SN/A break; 13522292SN/A case LSQ: 13532292SN/A ++renameLSQFullEvents; 13542292SN/A break; 13552292SN/A default: 13562292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13572292SN/A break; 13581060SN/A } 13592292SN/A} 13601060SN/A 13612292SN/Atemplate <class Impl> 13622292SN/Avoid 13632292SN/ADefaultRename<Impl>::dumpHistory() 13642292SN/A{ 13652980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13661060SN/A 13676221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13681060SN/A 13696221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13701060SN/A 13716221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13722292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13732292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13742292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13751060SN/A 13762292SN/A buf_it++; 13771062SN/A } 13781060SN/A } 13791060SN/A} 1380