rename_impl.hh revision 8907
12SN/A/* 21762SN/A * Copyright (c) 2010 ARM Limited 32SN/A * All rights reserved. 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292439SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30146SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31146SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32146SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33146SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34146SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35146SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361717SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37146SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381717SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392190SN/A * 40146SN/A * Authors: Kevin Lim 41146SN/A * Korey Sewell 421977SN/A */ 431717SN/A 442623SN/A#include <list> 451717SN/A 46146SN/A#include "arch/isa_traits.hh" 471917SN/A#include "arch/registers.hh" 482592SN/A#include "config/the_isa.hh" 492036SN/A#include "cpu/o3/rename.hh" 50146SN/A#include "debug/Activity.hh" 51146SN/A#include "debug/Rename.hh" 5256SN/A#include "params/DerivO3CPU.hh" 5356SN/A 5456SN/Ausing namespace std; 55695SN/A 562SN/Atemplate <class Impl> 571858SN/ADefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 5856SN/A : cpu(_cpu), 59146SN/A iewToRenameDelay(params->iewToRenameDelay), 602171SN/A decodeToRenameDelay(params->decodeToRenameDelay), 612170SN/A commitToRenameDelay(params->commitToRenameDelay), 622170SN/A renameWidth(params->renameWidth), 63146SN/A commitWidth(params->commitWidth), 642462SN/A resumeSerialize(false), 65146SN/A resumeUnblocking(false), 662SN/A numThreads(params->numThreads), 672SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 682449SN/A{ 691355SN/A _status = Inactive; 702623SN/A 712623SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 72224SN/A renameStatus[tid] = Idle; 731858SN/A 742518SN/A freeEntries[tid].iqEntries = 0; 752420SN/A freeEntries[tid].lsqEntries = 0; 762519SN/A freeEntries[tid].robEntries = 0; 772520SN/A 782420SN/A stalls[tid].iew = false; 792SN/A stalls[tid].commit = false; 802190SN/A serializeInst[tid] = NULL; 812SN/A 822SN/A instsInProgress[tid] = 0; 83334SN/A 84140SN/A emptyROB[tid] = true; 85334SN/A 862SN/A serializeOnNextInst[tid] = false; 872SN/A } 882SN/A 892190SN/A // @todo: Make into a parameter. 902SN/A skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 912SN/A} 922623SN/A 932SN/Atemplate <class Impl> 942SN/Astd::string 952SN/ADefaultRename<Impl>::name() const 96180SN/A{ 972623SN/A return cpu->name() + ".rename"; 98393SN/A} 99393SN/A 100393SN/Atemplate <class Impl> 101393SN/Avoid 102384SN/ADefaultRename<Impl>::regStats() 103384SN/A{ 104393SN/A renameSquashCycles 1052623SN/A .name(name() + ".SquashCycles") 106393SN/A .desc("Number of cycles rename is squashing") 107393SN/A .prereq(renameSquashCycles); 108393SN/A renameIdleCycles 109393SN/A .name(name() + ".IdleCycles") 110384SN/A .desc("Number of cycles rename is idle") 111189SN/A .prereq(renameIdleCycles); 112189SN/A renameBlockCycles 1132623SN/A .name(name() + ".BlockCycles") 1142SN/A .desc("Number of cycles rename is blocking") 115729SN/A .prereq(renameBlockCycles); 116334SN/A renameSerializeStallCycles 1172SN/A .name(name() + ".serializeStallCycles") 1182SN/A .desc("count of cycles rename stalled for serializing inst") 1192SN/A .flags(Stats::total); 1202SN/A renameRunCycles 1212SN/A .name(name() + ".RunCycles") 1222SN/A .desc("Number of cycles rename is running") 1232SN/A .prereq(renameIdleCycles); 1242SN/A renameUnblockCycles 1252SN/A .name(name() + ".UnblockCycles") 1262SN/A .desc("Number of cycles rename is unblocking") 1272SN/A .prereq(renameUnblockCycles); 1282SN/A renameRenamedInsts 1291001SN/A .name(name() + ".RenamedInsts") 1301001SN/A .desc("Number of instructions processed by rename") 1311001SN/A .prereq(renameRenamedInsts); 1321001SN/A renameSquashedInsts 1331001SN/A .name(name() + ".SquashedInsts") 1342SN/A .desc("Number of squashed instructions processed by rename") 1352SN/A .prereq(renameSquashedInsts); 1362SN/A renameROBFullEvents 1372SN/A .name(name() + ".ROBFullEvents") 1382SN/A .desc("Number of times rename has blocked due to ROB full") 1392SN/A .prereq(renameROBFullEvents); 1402SN/A renameIQFullEvents 1412SN/A .name(name() + ".IQFullEvents") 1422SN/A .desc("Number of times rename has blocked due to IQ full") 1432SN/A .prereq(renameIQFullEvents); 1442SN/A renameLSQFullEvents 1452SN/A .name(name() + ".LSQFullEvents") 1462SN/A .desc("Number of times rename has blocked due to LSQ full") 1472SN/A .prereq(renameLSQFullEvents); 1482SN/A renameFullRegistersEvents 1492SN/A .name(name() + ".FullRegisterEvents") 1502SN/A .desc("Number of times there has been no free registers") 1512390SN/A .prereq(renameFullRegistersEvents); 1522390SN/A renameRenamedOperands 1532390SN/A .name(name() + ".RenamedOperands") 1542390SN/A .desc("Number of destination operands rename has renamed") 1552390SN/A .prereq(renameRenamedOperands); 1562390SN/A renameRenameLookups 1572390SN/A .name(name() + ".RenameLookups") 1582390SN/A .desc("Number of register rename lookups that rename has made") 1592390SN/A .prereq(renameRenameLookups); 1602390SN/A renameCommittedMaps 1612390SN/A .name(name() + ".CommittedMaps") 1622390SN/A .desc("Number of HB maps that are committed") 163385SN/A .prereq(renameCommittedMaps); 1642SN/A renameUndoneMaps 1652SN/A .name(name() + ".UndoneMaps") 1662SN/A .desc("Number of HB maps that are undone due to squashing") 1672623SN/A .prereq(renameUndoneMaps); 168334SN/A renamedSerializing 169334SN/A .name(name() + ".serializingInsts") 1702623SN/A .desc("count of serializing insts renamed") 171334SN/A .flags(Stats::total) 172334SN/A ; 173334SN/A renamedTempSerializing 1742623SN/A .name(name() + ".tempSerializingInsts") 1752SN/A .desc("count of temporary serializing insts renamed") 176921SN/A .flags(Stats::total) 177224SN/A ; 178237SN/A renameSkidInsts 1792190SN/A .name(name() + ".skidInsts") 1802SN/A .desc("count of insts added to the skid buffer") 1812SN/A .flags(Stats::total) 1822SN/A ; 1832623SN/A intRenameLookups 1842SN/A .name(name() + ".int_rename_lookups") 185921SN/A .desc("Number of integer rename lookups") 186224SN/A .prereq(intRenameLookups); 1872190SN/A fpRenameLookups 1882SN/A .name(name() + ".fp_rename_lookups") 1892SN/A .desc("Number of floating rename lookups") 1902SN/A .prereq(fpRenameLookups); 1912SN/A} 1922SN/A 1932SN/Atemplate <class Impl> 1942SN/Avoid 195595SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1962623SN/A{ 197595SN/A timeBuffer = tb_ptr; 1982390SN/A 1991080SN/A // Setup wire to read information from time buffer, from IEW stage. 2001080SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2011080SN/A 2021080SN/A // Setup wire to read infromation from time buffer, from commit stage. 2031080SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2041080SN/A 2051080SN/A // Setup wire to write information to previous stages. 2061121SN/A toDecode = timeBuffer->getWire(0); 2072107SN/A} 2081089SN/A 2091089SN/Atemplate <class Impl> 2101080SN/Avoid 2111080SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2121080SN/A{ 2131080SN/A renameQueue = rq_ptr; 214595SN/A 2152623SN/A // Setup wire to write information to future stages. 2162623SN/A toIEW = renameQueue->getWire(0); 217595SN/A} 2182090SN/A 2192190SN/Atemplate <class Impl> 2202190SN/Avoid 221595SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2222205SN/A{ 2232205SN/A decodeQueue = dq_ptr; 2242190SN/A 2252190SN/A // Setup wire to get information from decode. 226595SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 227595SN/A} 2282390SN/A 2292423SN/Atemplate <class Impl> 2302390SN/Avoid 231595SN/ADefaultRename<Impl>::initStage() 232595SN/A{ 233595SN/A // Grab the number of free entries directly from the stages. 2342623SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 235595SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2362390SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2371080SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 238595SN/A emptyROB[tid] = true; 2391080SN/A } 2401080SN/A} 241595SN/A 2422190SN/Atemplate<class Impl> 2431080SN/Avoid 2441080SN/ADefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2451080SN/A{ 2461121SN/A activeThreads = at_ptr; 2472107SN/A} 2481089SN/A 2491080SN/A 2501089SN/Atemplate <class Impl> 2511080SN/Avoid 2521080SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2531080SN/A{ 254595SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 2552422SN/A renameMap[tid] = &rm_ptr[tid]; 2561080SN/A} 2572090SN/A 2581080SN/Atemplate <class Impl> 259595SN/Avoid 2602190SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2612190SN/A{ 262595SN/A freeList = fl_ptr; 2632190SN/A} 2641098SN/A 2651098SN/Atemplate<class Impl> 2661098SN/Avoid 2672190SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2681098SN/A{ 2691098SN/A scoreboard = _scoreboard; 2701098SN/A} 2712012SN/A 2721098SN/Atemplate <class Impl> 2731098SN/Abool 274595SN/ADefaultRename<Impl>::drain() 2752205SN/A{ 2762205SN/A // Rename is ready to switch out at any time. 2772205SN/A cpu->signalDrained(); 278595SN/A return true; 2792390SN/A} 2802420SN/A 2812423SN/Atemplate <class Impl> 2822390SN/Avoid 283595SN/ADefaultRename<Impl>::switchOut() 284595SN/A{ 2851858SN/A // Clear any state, fix up the rename map. 2862SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2872623SN/A typename std::list<RenameHistory>::iterator hb_it = 2882SN/A historyBuffer[tid].begin(); 2892190SN/A 2902SN/A while (!historyBuffer[tid].empty()) { 2912SN/A assert(hb_it != historyBuffer[tid].end()); 2922SN/A 2931858SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2942SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 2952623SN/A 2962SN/A // Tell the rename map to set the architected register to the 2972SN/A // previous physical register that it was renamed to. 2982SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2992190SN/A 3002SN/A // Put the renamed physical register back on the free list. 3012190SN/A freeList->addReg(hb_it->newPhysReg); 3022SN/A 3032SN/A // Be sure to mark its register as ready if it's a misc register. 3042SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 3052SN/A scoreboard->setReg(hb_it->newPhysReg); 3062SN/A } 3072623SN/A 3082SN/A historyBuffer[tid].erase(hb_it++); 3091858SN/A } 3102626SN/A insts[tid].clear(); 3112SN/A skidBuffer[tid].clear(); 3122SN/A } 3131133SN/A} 3142SN/A 3152190SN/Atemplate <class Impl> 3162107SN/Avoid 3172107SN/ADefaultRename<Impl>::takeOverFrom() 3182190SN/A{ 3192SN/A _status = Inactive; 3202107SN/A initStage(); 3212SN/A 3222SN/A // Reset all state prior to taking over from the other CPU. 3232SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3242SN/A renameStatus[tid] = Idle; 3252SN/A 3262190SN/A stalls[tid].iew = false; 3272107SN/A stalls[tid].commit = false; 3282107SN/A serializeInst[tid] = NULL; 3292SN/A 3302SN/A instsInProgress[tid] = 0; 3312SN/A 3322SN/A emptyROB[tid] = true; 3332SN/A 3342SN/A serializeOnNextInst[tid] = false; 3352SN/A } 3362190SN/A} 3372SN/A 3382SN/Atemplate <class Impl> 3392190SN/Avoid 3402190SN/ADefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3412190SN/A{ 3422234SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3432234SN/A 3442SN/A // Clear the stall signal if rename was blocked or unblocking before. 3452SN/A // If it still needs to block, the blocking should happen the next 3462190SN/A // cycle and there should be space to hold everything due to the squash. 3472SN/A if (renameStatus[tid] == Blocked || 3482SN/A renameStatus[tid] == Unblocking) { 3492SN/A toDecode->renameUnblock[tid] = 1; 3502623SN/A 3512SN/A resumeSerialize = false; 3522623SN/A serializeInst[tid] = NULL; 3532623SN/A } else if (renameStatus[tid] == SerializeStall) { 3542623SN/A if (serializeInst[tid]->seqNum <= squash_seq_num) { 3552623SN/A DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3562623SN/A resumeSerialize = true; 3572623SN/A assert(serializeInst[tid]); 3582623SN/A } else { 3592623SN/A resumeSerialize = false; 3602623SN/A toDecode->renameUnblock[tid] = 1; 3612623SN/A 3622623SN/A serializeInst[tid] = NULL; 3632623SN/A } 3642623SN/A } 3652623SN/A 3662623SN/A // Set the status to Squashing. 3672623SN/A renameStatus[tid] = Squashing; 3682623SN/A 3692623SN/A // Squash any instructions from decode. 3702623SN/A unsigned squashCount = 0; 3712623SN/A 3722623SN/A for (int i=0; i<fromDecode->size; i++) { 3732623SN/A if (fromDecode->insts[i]->threadNumber == tid && 3742623SN/A fromDecode->insts[i]->seqNum > squash_seq_num) { 3752641Sstever@eecs.umich.edu fromDecode->insts[i]->setSquashed(); 3762623SN/A wroteToTimeBuffer = true; 3772623SN/A squashCount++; 3782623SN/A } 3792623SN/A 3802623SN/A } 3812623SN/A 3822623SN/A // Clear the instruction list and skid buffer in case they have any 3832623SN/A // insts in them. 3842623SN/A insts[tid].clear(); 3852SN/A 3862190SN/A // Clear the skid buffer in case it has any data in it. 3872427SN/A skidBuffer[tid].clear(); 3882455SN/A 3892427SN/A doSquash(squash_seq_num, tid); 3902SN/A} 3912623SN/A 3922623SN/Atemplate <class Impl> 3932623SN/Avoid 3942SN/ADefaultRename<Impl>::tick() 3952623SN/A{ 3962SN/A wroteToTimeBuffer = false; 3972623SN/A 3982623SN/A blockThisCycle = false; 3992SN/A 4002623SN/A bool status_change = false; 4012623SN/A 4022623SN/A toIEWIndex = 0; 4032470SN/A 4042623SN/A sortInsts(); 4052623SN/A 4062623SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 4072623SN/A list<ThreadID>::iterator end = activeThreads->end(); 4082623SN/A 4092623SN/A // Check stall and squash signals. 4102623SN/A while (threads != end) { 4112623SN/A ThreadID tid = *threads++; 4122623SN/A 4132623SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4142623SN/A 4152623SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4162623SN/A 4172623SN/A rename(status_change, tid); 4182623SN/A } 4192623SN/A 4202623SN/A if (status_change) { 4212623SN/A updateStatus(); 4222623SN/A } 4232623SN/A 4242623SN/A if (wroteToTimeBuffer) { 4252623SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4262623SN/A cpu->activityThisCycle(); 4272623SN/A } 4282623SN/A 4292623SN/A threads = activeThreads->begin(); 4302623SN/A 4312623SN/A while (threads != end) { 4322623SN/A ThreadID tid = *threads++; 4332420SN/A 4342SN/A // If we committed this cycle then doneSeqNum will be > 0 4352623SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4362623SN/A !fromCommit->commitInfo[tid].squash && 4372SN/A renameStatus[tid] != Squashing) { 4382SN/A 4392623SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4402623SN/A tid); 4412623SN/A } 4422623SN/A } 4432SN/A 4442623SN/A // @todo: make into updateProgress function 4452623SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4462SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4472SN/A 4482623SN/A assert(instsInProgress[tid] >=0); 4492623SN/A } 4502623SN/A 4512090SN/A} 4521858SN/A 4532234SN/Atemplate<class Impl> 4542SN/Avoid 4552470SN/ADefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4562SN/A{ 4572SN/A // If status is Running or idle, 4582SN/A // call renameInsts() 4592SN/A // If status is Unblocking, 4602190SN/A // buffer any instructions coming from decode 4612623SN/A // continue trying to empty skid buffer 4622190SN/A // check if stall conditions have passed 4632251SN/A 4642262SN/A if (renameStatus[tid] == Blocked) { 4652262SN/A ++renameBlockCycles; 4662251SN/A } else if (renameStatus[tid] == Squashing) { 4672251SN/A ++renameSquashCycles; 4682SN/A } else if (renameStatus[tid] == SerializeStall) { 4692SN/A ++renameSerializeStallCycles; 4701858SN/A // If we are currently in SerializeStall and resumeSerialize 4712SN/A // was set, then that means that we are resuming serializing 4722SN/A // this cycle. Tell the previous stages to block. 4732190SN/A if (resumeSerialize) { 4742190SN/A resumeSerialize = false; 4752190SN/A block(tid); 4762SN/A toDecode->renameUnblock[tid] = false; 4772SN/A } 4782SN/A } else if (renameStatus[tid] == Unblocking) { 479 if (resumeUnblocking) { 480 block(tid); 481 resumeUnblocking = false; 482 toDecode->renameUnblock[tid] = false; 483 } 484 } 485 486 if (renameStatus[tid] == Running || 487 renameStatus[tid] == Idle) { 488 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 489 "stage.\n", tid); 490 491 renameInsts(tid); 492 } else if (renameStatus[tid] == Unblocking) { 493 renameInsts(tid); 494 495 if (validInsts()) { 496 // Add the current inputs to the skid buffer so they can be 497 // reprocessed when this stage unblocks. 498 skidInsert(tid); 499 } 500 501 // If we switched over to blocking, then there's a potential for 502 // an overall status change. 503 status_change = unblock(tid) || status_change || blockThisCycle; 504 } 505} 506 507template <class Impl> 508void 509DefaultRename<Impl>::renameInsts(ThreadID tid) 510{ 511 // Instructions can be either in the skid buffer or the queue of 512 // instructions coming from decode, depending on the status. 513 int insts_available = renameStatus[tid] == Unblocking ? 514 skidBuffer[tid].size() : insts[tid].size(); 515 516 // Check the decode queue to see if instructions are available. 517 // If there are no available instructions to rename, then do nothing. 518 if (insts_available == 0) { 519 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 520 tid); 521 // Should I change status to idle? 522 ++renameIdleCycles; 523 return; 524 } else if (renameStatus[tid] == Unblocking) { 525 ++renameUnblockCycles; 526 } else if (renameStatus[tid] == Running) { 527 ++renameRunCycles; 528 } 529 530 DynInstPtr inst; 531 532 // Will have to do a different calculation for the number of free 533 // entries. 534 int free_rob_entries = calcFreeROBEntries(tid); 535 int free_iq_entries = calcFreeIQEntries(tid); 536 int free_lsq_entries = calcFreeLSQEntries(tid); 537 int min_free_entries = free_rob_entries; 538 539 FullSource source = ROB; 540 541 if (free_iq_entries < min_free_entries) { 542 min_free_entries = free_iq_entries; 543 source = IQ; 544 } 545 546 if (free_lsq_entries < min_free_entries) { 547 min_free_entries = free_lsq_entries; 548 source = LSQ; 549 } 550 551 // Check if there's any space left. 552 if (min_free_entries <= 0) { 553 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 554 "entries.\n" 555 "ROB has %i free entries.\n" 556 "IQ has %i free entries.\n" 557 "LSQ has %i free entries.\n", 558 tid, 559 free_rob_entries, 560 free_iq_entries, 561 free_lsq_entries); 562 563 blockThisCycle = true; 564 565 block(tid); 566 567 incrFullStat(source); 568 569 return; 570 } else if (min_free_entries < insts_available) { 571 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 572 "%i insts available, but only %i insts can be " 573 "renamed due to ROB/IQ/LSQ limits.\n", 574 tid, insts_available, min_free_entries); 575 576 insts_available = min_free_entries; 577 578 blockThisCycle = true; 579 580 incrFullStat(source); 581 } 582 583 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 584 skidBuffer[tid] : insts[tid]; 585 586 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 587 "send iew.\n", tid, insts_available); 588 589 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 590 "dispatched to IQ last cycle.\n", 591 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 592 593 // Handle serializing the next instruction if necessary. 594 if (serializeOnNextInst[tid]) { 595 if (emptyROB[tid] && instsInProgress[tid] == 0) { 596 // ROB already empty; no need to serialize. 597 serializeOnNextInst[tid] = false; 598 } else if (!insts_to_rename.empty()) { 599 insts_to_rename.front()->setSerializeBefore(); 600 } 601 } 602 603 int renamed_insts = 0; 604 605 while (insts_available > 0 && toIEWIndex < renameWidth) { 606 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 607 608 assert(!insts_to_rename.empty()); 609 610 inst = insts_to_rename.front(); 611 612 insts_to_rename.pop_front(); 613 614 if (renameStatus[tid] == Unblocking) { 615 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 616 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 617 } 618 619 if (inst->isSquashed()) { 620 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 621 "squashed, skipping.\n", tid, inst->seqNum, 622 inst->pcState()); 623 624 ++renameSquashedInsts; 625 626 // Decrement how many instructions are available. 627 --insts_available; 628 629 continue; 630 } 631 632 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 633 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 634 635 // Handle serializeAfter/serializeBefore instructions. 636 // serializeAfter marks the next instruction as serializeBefore. 637 // serializeBefore makes the instruction wait in rename until the ROB 638 // is empty. 639 640 // In this model, IPR accesses are serialize before 641 // instructions, and store conditionals are serialize after 642 // instructions. This is mainly due to lack of support for 643 // out-of-order operations of either of those classes of 644 // instructions. 645 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 646 !inst->isSerializeHandled()) { 647 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 648 649 if (!inst->isTempSerializeBefore()) { 650 renamedSerializing++; 651 inst->setSerializeHandled(); 652 } else { 653 renamedTempSerializing++; 654 } 655 656 // Change status over to SerializeStall so that other stages know 657 // what this is blocked on. 658 renameStatus[tid] = SerializeStall; 659 660 serializeInst[tid] = inst; 661 662 blockThisCycle = true; 663 664 break; 665 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 666 !inst->isSerializeHandled()) { 667 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 668 669 renamedSerializing++; 670 671 inst->setSerializeHandled(); 672 673 serializeAfter(insts_to_rename, tid); 674 } 675 676 // Check here to make sure there are enough destination registers 677 // to rename to. Otherwise block. 678 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 679 DPRINTF(Rename, "Blocking due to lack of free " 680 "physical registers to rename to.\n"); 681 blockThisCycle = true; 682 insts_to_rename.push_front(inst); 683 ++renameFullRegistersEvents; 684 685 break; 686 } 687 688 renameSrcRegs(inst, inst->threadNumber); 689 690 renameDestRegs(inst, inst->threadNumber); 691 692 ++renamed_insts; 693 694#if TRACING_ON 695 inst->renameTick = curTick(); 696#endif 697 698 // Put instruction in rename queue. 699 toIEW->insts[toIEWIndex] = inst; 700 ++(toIEW->size); 701 702 // Increment which instruction we're on. 703 ++toIEWIndex; 704 705 // Decrement how many instructions are available. 706 --insts_available; 707 } 708 709 instsInProgress[tid] += renamed_insts; 710 renameRenamedInsts += renamed_insts; 711 712 // If we wrote to the time buffer, record this. 713 if (toIEWIndex) { 714 wroteToTimeBuffer = true; 715 } 716 717 // Check if there's any instructions left that haven't yet been renamed. 718 // If so then block. 719 if (insts_available) { 720 blockThisCycle = true; 721 } 722 723 if (blockThisCycle) { 724 block(tid); 725 toDecode->renameUnblock[tid] = false; 726 } 727} 728 729template<class Impl> 730void 731DefaultRename<Impl>::skidInsert(ThreadID tid) 732{ 733 DynInstPtr inst = NULL; 734 735 while (!insts[tid].empty()) { 736 inst = insts[tid].front(); 737 738 insts[tid].pop_front(); 739 740 assert(tid == inst->threadNumber); 741 742 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 743 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 744 745 ++renameSkidInsts; 746 747 skidBuffer[tid].push_back(inst); 748 } 749 750 if (skidBuffer[tid].size() > skidBufferMax) 751 { 752 typename InstQueue::iterator it; 753 warn("Skidbuffer contents:\n"); 754 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 755 { 756 warn("[tid:%u]: %s [sn:%i].\n", tid, 757 (*it)->staticInst->disassemble(inst->instAddr()), 758 (*it)->seqNum); 759 } 760 panic("Skidbuffer Exceeded Max Size"); 761 } 762} 763 764template <class Impl> 765void 766DefaultRename<Impl>::sortInsts() 767{ 768 int insts_from_decode = fromDecode->size; 769 for (int i = 0; i < insts_from_decode; ++i) { 770 DynInstPtr inst = fromDecode->insts[i]; 771 insts[inst->threadNumber].push_back(inst); 772 } 773} 774 775template<class Impl> 776bool 777DefaultRename<Impl>::skidsEmpty() 778{ 779 list<ThreadID>::iterator threads = activeThreads->begin(); 780 list<ThreadID>::iterator end = activeThreads->end(); 781 782 while (threads != end) { 783 ThreadID tid = *threads++; 784 785 if (!skidBuffer[tid].empty()) 786 return false; 787 } 788 789 return true; 790} 791 792template<class Impl> 793void 794DefaultRename<Impl>::updateStatus() 795{ 796 bool any_unblocking = false; 797 798 list<ThreadID>::iterator threads = activeThreads->begin(); 799 list<ThreadID>::iterator end = activeThreads->end(); 800 801 while (threads != end) { 802 ThreadID tid = *threads++; 803 804 if (renameStatus[tid] == Unblocking) { 805 any_unblocking = true; 806 break; 807 } 808 } 809 810 // Rename will have activity if it's unblocking. 811 if (any_unblocking) { 812 if (_status == Inactive) { 813 _status = Active; 814 815 DPRINTF(Activity, "Activating stage.\n"); 816 817 cpu->activateStage(O3CPU::RenameIdx); 818 } 819 } else { 820 // If it's not unblocking, then rename will not have any internal 821 // activity. Switch it to inactive. 822 if (_status == Active) { 823 _status = Inactive; 824 DPRINTF(Activity, "Deactivating stage.\n"); 825 826 cpu->deactivateStage(O3CPU::RenameIdx); 827 } 828 } 829} 830 831template <class Impl> 832bool 833DefaultRename<Impl>::block(ThreadID tid) 834{ 835 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 836 837 // Add the current inputs onto the skid buffer, so they can be 838 // reprocessed when this stage unblocks. 839 skidInsert(tid); 840 841 // Only signal backwards to block if the previous stages do not think 842 // rename is already blocked. 843 if (renameStatus[tid] != Blocked) { 844 // If resumeUnblocking is set, we unblocked during the squash, 845 // but now we're have unblocking status. We need to tell earlier 846 // stages to block. 847 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 848 toDecode->renameBlock[tid] = true; 849 toDecode->renameUnblock[tid] = false; 850 wroteToTimeBuffer = true; 851 } 852 853 // Rename can not go from SerializeStall to Blocked, otherwise 854 // it would not know to complete the serialize stall. 855 if (renameStatus[tid] != SerializeStall) { 856 // Set status to Blocked. 857 renameStatus[tid] = Blocked; 858 return true; 859 } 860 } 861 862 return false; 863} 864 865template <class Impl> 866bool 867DefaultRename<Impl>::unblock(ThreadID tid) 868{ 869 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 870 871 // Rename is done unblocking if the skid buffer is empty. 872 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 873 874 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 875 876 toDecode->renameUnblock[tid] = true; 877 wroteToTimeBuffer = true; 878 879 renameStatus[tid] = Running; 880 return true; 881 } 882 883 return false; 884} 885 886template <class Impl> 887void 888DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 889{ 890 typename std::list<RenameHistory>::iterator hb_it = 891 historyBuffer[tid].begin(); 892 893 // After a syscall squashes everything, the history buffer may be empty 894 // but the ROB may still be squashing instructions. 895 if (historyBuffer[tid].empty()) { 896 return; 897 } 898 899 // Go through the most recent instructions, undoing the mappings 900 // they did and freeing up the registers. 901 while (!historyBuffer[tid].empty() && 902 (*hb_it).instSeqNum > squashed_seq_num) { 903 assert(hb_it != historyBuffer[tid].end()); 904 905 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 906 "number %i.\n", tid, (*hb_it).instSeqNum); 907 908 // Tell the rename map to set the architected register to the 909 // previous physical register that it was renamed to. 910 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 911 912 // Put the renamed physical register back on the free list. 913 freeList->addReg(hb_it->newPhysReg); 914 915 // Be sure to mark its register as ready if it's a misc register. 916 if (hb_it->newPhysReg >= maxPhysicalRegs) { 917 scoreboard->setReg(hb_it->newPhysReg); 918 } 919 920 historyBuffer[tid].erase(hb_it++); 921 922 ++renameUndoneMaps; 923 } 924} 925 926template<class Impl> 927void 928DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 929{ 930 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 931 "history buffer %u (size=%i), until [sn:%lli].\n", 932 tid, tid, historyBuffer[tid].size(), inst_seq_num); 933 934 typename std::list<RenameHistory>::iterator hb_it = 935 historyBuffer[tid].end(); 936 937 --hb_it; 938 939 if (historyBuffer[tid].empty()) { 940 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 941 return; 942 } else if (hb_it->instSeqNum > inst_seq_num) { 943 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 944 "that a syscall happened recently.\n", tid); 945 return; 946 } 947 948 // Commit all the renames up until (and including) the committed sequence 949 // number. Some or even all of the committed instructions may not have 950 // rename histories if they did not have destination registers that were 951 // renamed. 952 while (!historyBuffer[tid].empty() && 953 hb_it != historyBuffer[tid].end() && 954 (*hb_it).instSeqNum <= inst_seq_num) { 955 956 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 957 "[sn:%lli].\n", 958 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 959 960 freeList->addReg((*hb_it).prevPhysReg); 961 ++renameCommittedMaps; 962 963 historyBuffer[tid].erase(hb_it--); 964 } 965} 966 967template <class Impl> 968inline void 969DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 970{ 971 assert(renameMap[tid] != 0); 972 973 unsigned num_src_regs = inst->numSrcRegs(); 974 975 // Get the architectual register numbers from the source and 976 // destination operands, and redirect them to the right register. 977 // Will need to mark dependencies though. 978 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 979 RegIndex src_reg = inst->srcRegIdx(src_idx); 980 RegIndex flat_src_reg = src_reg; 981 if (src_reg < TheISA::FP_Base_DepTag) { 982 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 983 DPRINTF(Rename, "Flattening index %d to %d.\n", 984 (int)src_reg, (int)flat_src_reg); 985 } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 986 src_reg = src_reg - TheISA::FP_Base_DepTag; 987 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 988 DPRINTF(Rename, "Flattening index %d to %d.\n", 989 (int)src_reg, (int)flat_src_reg); 990 flat_src_reg += TheISA::NumIntRegs; 991 } else if (src_reg < TheISA::Max_DepTag) { 992 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 993 TheISA::NumFloatRegs + TheISA::NumIntRegs; 994 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 995 src_reg, flat_src_reg); 996 } else { 997 panic("Reg index is out of bound: %d.", src_reg); 998 } 999 1000 inst->flattenSrcReg(src_idx, flat_src_reg); 1001 1002 // Look up the source registers to get the phys. register they've 1003 // been renamed to, and set the sources to those registers. 1004 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 1005 1006 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 1007 "physical reg %i.\n", tid, (int)flat_src_reg, 1008 (int)renamed_reg); 1009 1010 inst->renameSrcReg(src_idx, renamed_reg); 1011 1012 // See if the register is ready or not. 1013 if (scoreboard->getReg(renamed_reg) == true) { 1014 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1015 tid, renamed_reg); 1016 1017 inst->markSrcRegReady(src_idx); 1018 } else { 1019 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1020 tid, renamed_reg); 1021 } 1022 1023 ++renameRenameLookups; 1024 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 1025 } 1026} 1027 1028template <class Impl> 1029inline void 1030DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1031{ 1032 typename RenameMap::RenameInfo rename_result; 1033 1034 unsigned num_dest_regs = inst->numDestRegs(); 1035 1036 // Rename the destination registers. 1037 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1038 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1039 RegIndex flat_dest_reg = dest_reg; 1040 if (dest_reg < TheISA::FP_Base_DepTag) { 1041 // Integer registers are flattened. 1042 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 1043 DPRINTF(Rename, "Flattening index %d to %d.\n", 1044 (int)dest_reg, (int)flat_dest_reg); 1045 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { 1046 dest_reg = dest_reg - TheISA::FP_Base_DepTag; 1047 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 1048 DPRINTF(Rename, "Flattening index %d to %d.\n", 1049 (int)dest_reg, (int)flat_dest_reg); 1050 flat_dest_reg += TheISA::NumIntRegs; 1051 } else if (dest_reg < TheISA::Max_DepTag) { 1052 // Floating point and Miscellaneous registers need their indexes 1053 // adjusted to account for the expanded number of flattened int regs. 1054 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 1055 TheISA::NumIntRegs + TheISA::NumFloatRegs; 1056 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 1057 dest_reg, flat_dest_reg); 1058 } else { 1059 panic("Reg index is out of bound: %d.", dest_reg); 1060 } 1061 1062 inst->flattenDestReg(dest_idx, flat_dest_reg); 1063 1064 // Get the physical register that the destination will be 1065 // renamed to. 1066 rename_result = renameMap[tid]->rename(flat_dest_reg); 1067 1068 //Mark Scoreboard entry as not ready 1069 if (dest_reg < TheISA::Ctrl_Base_DepTag) 1070 scoreboard->unsetReg(rename_result.first); 1071 1072 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1073 "reg %i.\n", tid, (int)flat_dest_reg, 1074 (int)rename_result.first); 1075 1076 // Record the rename information so that a history can be kept. 1077 RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 1078 rename_result.first, 1079 rename_result.second); 1080 1081 historyBuffer[tid].push_front(hb_entry); 1082 1083 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1084 "(size=%i), [sn:%lli].\n",tid, 1085 historyBuffer[tid].size(), 1086 (*historyBuffer[tid].begin()).instSeqNum); 1087 1088 // Tell the instruction to rename the appropriate destination 1089 // register (dest_idx) to the new physical register 1090 // (rename_result.first), and record the previous physical 1091 // register that the same logical register was renamed to 1092 // (rename_result.second). 1093 inst->renameDestReg(dest_idx, 1094 rename_result.first, 1095 rename_result.second); 1096 1097 ++renameRenamedOperands; 1098 } 1099} 1100 1101template <class Impl> 1102inline int 1103DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1104{ 1105 int num_free = freeEntries[tid].robEntries - 1106 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1107 1108 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1109 1110 return num_free; 1111} 1112 1113template <class Impl> 1114inline int 1115DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1116{ 1117 int num_free = freeEntries[tid].iqEntries - 1118 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1119 1120 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1121 1122 return num_free; 1123} 1124 1125template <class Impl> 1126inline int 1127DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 1128{ 1129 int num_free = freeEntries[tid].lsqEntries - 1130 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1131 1132 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1133 1134 return num_free; 1135} 1136 1137template <class Impl> 1138unsigned 1139DefaultRename<Impl>::validInsts() 1140{ 1141 unsigned inst_count = 0; 1142 1143 for (int i=0; i<fromDecode->size; i++) { 1144 if (!fromDecode->insts[i]->isSquashed()) 1145 inst_count++; 1146 } 1147 1148 return inst_count; 1149} 1150 1151template <class Impl> 1152void 1153DefaultRename<Impl>::readStallSignals(ThreadID tid) 1154{ 1155 if (fromIEW->iewBlock[tid]) { 1156 stalls[tid].iew = true; 1157 } 1158 1159 if (fromIEW->iewUnblock[tid]) { 1160 assert(stalls[tid].iew); 1161 stalls[tid].iew = false; 1162 } 1163 1164 if (fromCommit->commitBlock[tid]) { 1165 stalls[tid].commit = true; 1166 } 1167 1168 if (fromCommit->commitUnblock[tid]) { 1169 assert(stalls[tid].commit); 1170 stalls[tid].commit = false; 1171 } 1172} 1173 1174template <class Impl> 1175bool 1176DefaultRename<Impl>::checkStall(ThreadID tid) 1177{ 1178 bool ret_val = false; 1179 1180 if (stalls[tid].iew) { 1181 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1182 ret_val = true; 1183 } else if (stalls[tid].commit) { 1184 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1185 ret_val = true; 1186 } else if (calcFreeROBEntries(tid) <= 0) { 1187 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1188 ret_val = true; 1189 } else if (calcFreeIQEntries(tid) <= 0) { 1190 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1191 ret_val = true; 1192 } else if (calcFreeLSQEntries(tid) <= 0) { 1193 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1194 ret_val = true; 1195 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1196 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1197 ret_val = true; 1198 } else if (renameStatus[tid] == SerializeStall && 1199 (!emptyROB[tid] || instsInProgress[tid])) { 1200 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1201 "empty.\n", 1202 tid); 1203 ret_val = true; 1204 } 1205 1206 return ret_val; 1207} 1208 1209template <class Impl> 1210void 1211DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1212{ 1213 if (fromIEW->iewInfo[tid].usedIQ) 1214 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1215 1216 if (fromIEW->iewInfo[tid].usedLSQ) 1217 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 1218 1219 if (fromCommit->commitInfo[tid].usedROB) { 1220 freeEntries[tid].robEntries = 1221 fromCommit->commitInfo[tid].freeROBEntries; 1222 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1223 } 1224 1225 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1226 tid, 1227 freeEntries[tid].iqEntries, 1228 freeEntries[tid].robEntries, 1229 freeEntries[tid].lsqEntries); 1230 1231 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1232 tid, instsInProgress[tid]); 1233} 1234 1235template <class Impl> 1236bool 1237DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1238{ 1239 // Check if there's a squash signal, squash if there is 1240 // Check stall signals, block if necessary. 1241 // If status was blocked 1242 // check if stall conditions have passed 1243 // if so then go to unblocking 1244 // If status was Squashing 1245 // check if squashing is not high. Switch to running this cycle. 1246 // If status was serialize stall 1247 // check if ROB is empty and no insts are in flight to the ROB 1248 1249 readFreeEntries(tid); 1250 readStallSignals(tid); 1251 1252 if (fromCommit->commitInfo[tid].squash) { 1253 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1254 "commit.\n", tid); 1255 1256 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1257 1258 return true; 1259 } 1260 1261 if (fromCommit->commitInfo[tid].robSquashing) { 1262 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1263 1264 renameStatus[tid] = Squashing; 1265 1266 return true; 1267 } 1268 1269 if (checkStall(tid)) { 1270 return block(tid); 1271 } 1272 1273 if (renameStatus[tid] == Blocked) { 1274 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1275 tid); 1276 1277 renameStatus[tid] = Unblocking; 1278 1279 unblock(tid); 1280 1281 return true; 1282 } 1283 1284 if (renameStatus[tid] == Squashing) { 1285 // Switch status to running if rename isn't being told to block or 1286 // squash this cycle. 1287 if (resumeSerialize) { 1288 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1289 tid); 1290 1291 renameStatus[tid] = SerializeStall; 1292 return true; 1293 } else if (resumeUnblocking) { 1294 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1295 tid); 1296 renameStatus[tid] = Unblocking; 1297 return true; 1298 } else { 1299 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1300 tid); 1301 1302 renameStatus[tid] = Running; 1303 return false; 1304 } 1305 } 1306 1307 if (renameStatus[tid] == SerializeStall) { 1308 // Stall ends once the ROB is free. 1309 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1310 "unblocking.\n", tid); 1311 1312 DynInstPtr serial_inst = serializeInst[tid]; 1313 1314 renameStatus[tid] = Unblocking; 1315 1316 unblock(tid); 1317 1318 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1319 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1320 1321 // Put instruction into queue here. 1322 serial_inst->clearSerializeBefore(); 1323 1324 if (!skidBuffer[tid].empty()) { 1325 skidBuffer[tid].push_front(serial_inst); 1326 } else { 1327 insts[tid].push_front(serial_inst); 1328 } 1329 1330 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1331 " Adding to front of list.\n", tid); 1332 1333 serializeInst[tid] = NULL; 1334 1335 return true; 1336 } 1337 1338 // If we've reached this point, we have not gotten any signals that 1339 // cause rename to change its status. Rename remains the same as before. 1340 return false; 1341} 1342 1343template<class Impl> 1344void 1345DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1346{ 1347 if (inst_list.empty()) { 1348 // Mark a bit to say that I must serialize on the next instruction. 1349 serializeOnNextInst[tid] = true; 1350 return; 1351 } 1352 1353 // Set the next instruction as serializing. 1354 inst_list.front()->setSerializeBefore(); 1355} 1356 1357template <class Impl> 1358inline void 1359DefaultRename<Impl>::incrFullStat(const FullSource &source) 1360{ 1361 switch (source) { 1362 case ROB: 1363 ++renameROBFullEvents; 1364 break; 1365 case IQ: 1366 ++renameIQFullEvents; 1367 break; 1368 case LSQ: 1369 ++renameLSQFullEvents; 1370 break; 1371 default: 1372 panic("Rename full stall stat should be incremented for a reason!"); 1373 break; 1374 } 1375} 1376 1377template <class Impl> 1378void 1379DefaultRename<Impl>::dumpHistory() 1380{ 1381 typename std::list<RenameHistory>::iterator buf_it; 1382 1383 for (ThreadID tid = 0; tid < numThreads; tid++) { 1384 1385 buf_it = historyBuffer[tid].begin(); 1386 1387 while (buf_it != historyBuffer[tid].end()) { 1388 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1389 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1390 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1391 1392 buf_it++; 1393 } 1394 } 1395} 1396