rename_impl.hh revision 8471
11689SN/A/* 27854SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37854SAli.Saidi@ARM.com * All rights reserved. 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412935Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 441060SN/A#include <list> 451060SN/A 463773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 476329Sgblack@eecs.umich.edu#include "arch/registers.hh" 481858SN/A#include "config/full_system.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 501717SN/A#include "cpu/o3/rename.hh" 518232Snate@binkert.org#include "debug/Activity.hh" 528232Snate@binkert.org#include "debug/Rename.hh" 535529Snate@binkert.org#include "params/DerivO3CPU.hh" 541060SN/A 556221Snate@binkert.orgusing namespace std; 566221Snate@binkert.org 571061SN/Atemplate <class Impl> 585529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 594329Sktlim@umich.edu : cpu(_cpu), 604329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 612292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 622292SN/A commitToRenameDelay(params->commitToRenameDelay), 632292SN/A renameWidth(params->renameWidth), 642292SN/A commitWidth(params->commitWidth), 653788Sgblack@eecs.umich.edu resumeSerialize(false), 663798Sgblack@eecs.umich.edu resumeUnblocking(false), 675529Snate@binkert.org numThreads(params->numThreads), 682361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 691060SN/A{ 702292SN/A _status = Inactive; 712292SN/A 726221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 736221Snate@binkert.org renameStatus[tid] = Idle; 742292SN/A 756221Snate@binkert.org freeEntries[tid].iqEntries = 0; 766221Snate@binkert.org freeEntries[tid].lsqEntries = 0; 776221Snate@binkert.org freeEntries[tid].robEntries = 0; 782292SN/A 796221Snate@binkert.org stalls[tid].iew = false; 806221Snate@binkert.org stalls[tid].commit = false; 816221Snate@binkert.org serializeInst[tid] = NULL; 822292SN/A 836221Snate@binkert.org instsInProgress[tid] = 0; 842292SN/A 856221Snate@binkert.org emptyROB[tid] = true; 862292SN/A 876221Snate@binkert.org serializeOnNextInst[tid] = false; 882292SN/A } 892292SN/A 902292SN/A // @todo: Make into a parameter. 912292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 922292SN/A} 932292SN/A 942292SN/Atemplate <class Impl> 952292SN/Astd::string 962292SN/ADefaultRename<Impl>::name() const 972292SN/A{ 982292SN/A return cpu->name() + ".rename"; 991060SN/A} 1001060SN/A 1011061SN/Atemplate <class Impl> 1021060SN/Avoid 1032292SN/ADefaultRename<Impl>::regStats() 1041062SN/A{ 1051062SN/A renameSquashCycles 1068240Snate@binkert.org .name(name() + ".SquashCycles") 1071062SN/A .desc("Number of cycles rename is squashing") 1081062SN/A .prereq(renameSquashCycles); 1091062SN/A renameIdleCycles 1108240Snate@binkert.org .name(name() + ".IdleCycles") 1111062SN/A .desc("Number of cycles rename is idle") 1121062SN/A .prereq(renameIdleCycles); 1131062SN/A renameBlockCycles 1148240Snate@binkert.org .name(name() + ".BlockCycles") 1151062SN/A .desc("Number of cycles rename is blocking") 1161062SN/A .prereq(renameBlockCycles); 1172301SN/A renameSerializeStallCycles 1188240Snate@binkert.org .name(name() + ".serializeStallCycles") 1192301SN/A .desc("count of cycles rename stalled for serializing inst") 1202301SN/A .flags(Stats::total); 1212292SN/A renameRunCycles 1228240Snate@binkert.org .name(name() + ".RunCycles") 1232292SN/A .desc("Number of cycles rename is running") 1242292SN/A .prereq(renameIdleCycles); 1251062SN/A renameUnblockCycles 1268240Snate@binkert.org .name(name() + ".UnblockCycles") 1271062SN/A .desc("Number of cycles rename is unblocking") 1281062SN/A .prereq(renameUnblockCycles); 1291062SN/A renameRenamedInsts 1308240Snate@binkert.org .name(name() + ".RenamedInsts") 1311062SN/A .desc("Number of instructions processed by rename") 1321062SN/A .prereq(renameRenamedInsts); 1331062SN/A renameSquashedInsts 1348240Snate@binkert.org .name(name() + ".SquashedInsts") 1351062SN/A .desc("Number of squashed instructions processed by rename") 1361062SN/A .prereq(renameSquashedInsts); 1371062SN/A renameROBFullEvents 1388240Snate@binkert.org .name(name() + ".ROBFullEvents") 1392292SN/A .desc("Number of times rename has blocked due to ROB full") 1401062SN/A .prereq(renameROBFullEvents); 1411062SN/A renameIQFullEvents 1428240Snate@binkert.org .name(name() + ".IQFullEvents") 1432292SN/A .desc("Number of times rename has blocked due to IQ full") 1441062SN/A .prereq(renameIQFullEvents); 1452292SN/A renameLSQFullEvents 1468240Snate@binkert.org .name(name() + ".LSQFullEvents") 1472292SN/A .desc("Number of times rename has blocked due to LSQ full") 1482292SN/A .prereq(renameLSQFullEvents); 1491062SN/A renameFullRegistersEvents 1508240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1511062SN/A .desc("Number of times there has been no free registers") 1521062SN/A .prereq(renameFullRegistersEvents); 1531062SN/A renameRenamedOperands 1548240Snate@binkert.org .name(name() + ".RenamedOperands") 1551062SN/A .desc("Number of destination operands rename has renamed") 1561062SN/A .prereq(renameRenamedOperands); 1571062SN/A renameRenameLookups 1588240Snate@binkert.org .name(name() + ".RenameLookups") 1591062SN/A .desc("Number of register rename lookups that rename has made") 1601062SN/A .prereq(renameRenameLookups); 1611062SN/A renameCommittedMaps 1628240Snate@binkert.org .name(name() + ".CommittedMaps") 1631062SN/A .desc("Number of HB maps that are committed") 1641062SN/A .prereq(renameCommittedMaps); 1651062SN/A renameUndoneMaps 1668240Snate@binkert.org .name(name() + ".UndoneMaps") 1671062SN/A .desc("Number of HB maps that are undone due to squashing") 1681062SN/A .prereq(renameUndoneMaps); 1692301SN/A renamedSerializing 1708240Snate@binkert.org .name(name() + ".serializingInsts") 1712301SN/A .desc("count of serializing insts renamed") 1722301SN/A .flags(Stats::total) 1732301SN/A ; 1742301SN/A renamedTempSerializing 1758240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1762301SN/A .desc("count of temporary serializing insts renamed") 1772301SN/A .flags(Stats::total) 1782301SN/A ; 1792307SN/A renameSkidInsts 1808240Snate@binkert.org .name(name() + ".skidInsts") 1812307SN/A .desc("count of insts added to the skid buffer") 1822307SN/A .flags(Stats::total) 1832307SN/A ; 1847897Shestness@cs.utexas.edu intRenameLookups 1858240Snate@binkert.org .name(name() + ".int_rename_lookups") 1867897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1877897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1887897Shestness@cs.utexas.edu fpRenameLookups 1898240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1907897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1917897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1921062SN/A} 1931062SN/A 1941062SN/Atemplate <class Impl> 1951062SN/Avoid 1962292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1971060SN/A{ 1981060SN/A timeBuffer = tb_ptr; 1991060SN/A 2001060SN/A // Setup wire to read information from time buffer, from IEW stage. 2011060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2021060SN/A 2031060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2041060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2051060SN/A 2061060SN/A // Setup wire to write information to previous stages. 2071060SN/A toDecode = timeBuffer->getWire(0); 2081060SN/A} 2091060SN/A 2101061SN/Atemplate <class Impl> 2111060SN/Avoid 2122292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2131060SN/A{ 2141060SN/A renameQueue = rq_ptr; 2151060SN/A 2161060SN/A // Setup wire to write information to future stages. 2171060SN/A toIEW = renameQueue->getWire(0); 2181060SN/A} 2191060SN/A 2201061SN/Atemplate <class Impl> 2211060SN/Avoid 2222292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2231060SN/A{ 2241060SN/A decodeQueue = dq_ptr; 2251060SN/A 2261060SN/A // Setup wire to get information from decode. 2271060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2281060SN/A} 2291060SN/A 2301061SN/Atemplate <class Impl> 2311060SN/Avoid 2322292SN/ADefaultRename<Impl>::initStage() 2331060SN/A{ 2342329SN/A // Grab the number of free entries directly from the stages. 2356221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2362292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2372292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2382292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2392292SN/A emptyROB[tid] = true; 2402292SN/A } 2411060SN/A} 2421060SN/A 2432292SN/Atemplate<class Impl> 2442292SN/Avoid 2456221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2462292SN/A{ 2472292SN/A activeThreads = at_ptr; 2482292SN/A} 2492292SN/A 2502292SN/A 2511061SN/Atemplate <class Impl> 2521060SN/Avoid 2532292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2541060SN/A{ 2556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2566221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2571060SN/A} 2581060SN/A 2591061SN/Atemplate <class Impl> 2601060SN/Avoid 2612292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2621060SN/A{ 2632292SN/A freeList = fl_ptr; 2642292SN/A} 2651060SN/A 2662292SN/Atemplate<class Impl> 2672292SN/Avoid 2682292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2692292SN/A{ 2702292SN/A scoreboard = _scoreboard; 2711060SN/A} 2721060SN/A 2731061SN/Atemplate <class Impl> 2742863Sktlim@umich.edubool 2752843Sktlim@umich.eduDefaultRename<Impl>::drain() 2761060SN/A{ 2772348SN/A // Rename is ready to switch out at any time. 2782843Sktlim@umich.edu cpu->signalDrained(); 2792863Sktlim@umich.edu return true; 2802316SN/A} 2811060SN/A 2822316SN/Atemplate <class Impl> 2832316SN/Avoid 2842843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2852316SN/A{ 2862348SN/A // Clear any state, fix up the rename map. 2876221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2882980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2896221Snate@binkert.org historyBuffer[tid].begin(); 2902307SN/A 2916221Snate@binkert.org while (!historyBuffer[tid].empty()) { 2926221Snate@binkert.org assert(hb_it != historyBuffer[tid].end()); 2932307SN/A 2942307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2956221Snate@binkert.org "number %i.\n", tid, (*hb_it).instSeqNum); 2962307SN/A 2972307SN/A // Tell the rename map to set the architected register to the 2982307SN/A // previous physical register that it was renamed to. 2996221Snate@binkert.org renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 3002307SN/A 3012307SN/A // Put the renamed physical register back on the free list. 3022307SN/A freeList->addReg(hb_it->newPhysReg); 3032307SN/A 3042361SN/A // Be sure to mark its register as ready if it's a misc register. 3052361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 3062361SN/A scoreboard->setReg(hb_it->newPhysReg); 3072361SN/A } 3082361SN/A 3096221Snate@binkert.org historyBuffer[tid].erase(hb_it++); 3102307SN/A } 3116221Snate@binkert.org insts[tid].clear(); 3126221Snate@binkert.org skidBuffer[tid].clear(); 3131060SN/A } 3141060SN/A} 3151060SN/A 3161061SN/Atemplate <class Impl> 3171060SN/Avoid 3182307SN/ADefaultRename<Impl>::takeOverFrom() 3191060SN/A{ 3202307SN/A _status = Inactive; 3212307SN/A initStage(); 3221060SN/A 3232329SN/A // Reset all state prior to taking over from the other CPU. 3246221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3256221Snate@binkert.org renameStatus[tid] = Idle; 3261060SN/A 3276221Snate@binkert.org stalls[tid].iew = false; 3286221Snate@binkert.org stalls[tid].commit = false; 3296221Snate@binkert.org serializeInst[tid] = NULL; 3302307SN/A 3316221Snate@binkert.org instsInProgress[tid] = 0; 3322307SN/A 3336221Snate@binkert.org emptyROB[tid] = true; 3342307SN/A 3356221Snate@binkert.org serializeOnNextInst[tid] = false; 3362307SN/A } 3372307SN/A} 3382307SN/A 3392307SN/Atemplate <class Impl> 3402307SN/Avoid 3416221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3421858SN/A{ 3432292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3441858SN/A 3452292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3462292SN/A // If it still needs to block, the blocking should happen the next 3472292SN/A // cycle and there should be space to hold everything due to the squash. 3482292SN/A if (renameStatus[tid] == Blocked || 3493788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3502292SN/A toDecode->renameUnblock[tid] = 1; 3512698Sktlim@umich.edu 3523788Sgblack@eecs.umich.edu resumeSerialize = false; 3532301SN/A serializeInst[tid] = NULL; 3543788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3553788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3563788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3573788Sgblack@eecs.umich.edu resumeSerialize = true; 3583788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3593788Sgblack@eecs.umich.edu } else { 3603788Sgblack@eecs.umich.edu resumeSerialize = false; 3613788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3623788Sgblack@eecs.umich.edu 3633788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3643788Sgblack@eecs.umich.edu } 3652292SN/A } 3662292SN/A 3672292SN/A // Set the status to Squashing. 3682292SN/A renameStatus[tid] = Squashing; 3692292SN/A 3702329SN/A // Squash any instructions from decode. 3712292SN/A unsigned squashCount = 0; 3722292SN/A 3732292SN/A for (int i=0; i<fromDecode->size; i++) { 3742935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3752935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3762731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3772292SN/A wroteToTimeBuffer = true; 3782292SN/A squashCount++; 3792292SN/A } 3802935Sksewell@umich.edu 3812292SN/A } 3822292SN/A 3832935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3844632Sgblack@eecs.umich.edu // insts in them. 3853093Sksewell@umich.edu insts[tid].clear(); 3862292SN/A 3872292SN/A // Clear the skid buffer in case it has any data in it. 3883093Sksewell@umich.edu skidBuffer[tid].clear(); 3894632Sgblack@eecs.umich.edu 3902935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3912292SN/A} 3922292SN/A 3932292SN/Atemplate <class Impl> 3942292SN/Avoid 3952292SN/ADefaultRename<Impl>::tick() 3962292SN/A{ 3972292SN/A wroteToTimeBuffer = false; 3982292SN/A 3992292SN/A blockThisCycle = false; 4002292SN/A 4012292SN/A bool status_change = false; 4022292SN/A 4032292SN/A toIEWIndex = 0; 4042292SN/A 4052292SN/A sortInsts(); 4062292SN/A 4076221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4086221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4092292SN/A 4102292SN/A // Check stall and squash signals. 4113867Sbinkertn@umich.edu while (threads != end) { 4126221Snate@binkert.org ThreadID tid = *threads++; 4132292SN/A 4142292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4152292SN/A 4162292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4172292SN/A 4182292SN/A rename(status_change, tid); 4192292SN/A } 4202292SN/A 4212292SN/A if (status_change) { 4222292SN/A updateStatus(); 4232292SN/A } 4242292SN/A 4252292SN/A if (wroteToTimeBuffer) { 4262292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4272292SN/A cpu->activityThisCycle(); 4282292SN/A } 4292292SN/A 4303867Sbinkertn@umich.edu threads = activeThreads->begin(); 4312292SN/A 4323867Sbinkertn@umich.edu while (threads != end) { 4336221Snate@binkert.org ThreadID tid = *threads++; 4342292SN/A 4352292SN/A // If we committed this cycle then doneSeqNum will be > 0 4362292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4372292SN/A !fromCommit->commitInfo[tid].squash && 4382292SN/A renameStatus[tid] != Squashing) { 4392292SN/A 4402292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4412292SN/A tid); 4422292SN/A } 4432292SN/A } 4442292SN/A 4452292SN/A // @todo: make into updateProgress function 4466221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4472292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4482292SN/A 4492292SN/A assert(instsInProgress[tid] >=0); 4502292SN/A } 4512292SN/A 4522292SN/A} 4532292SN/A 4542292SN/Atemplate<class Impl> 4552292SN/Avoid 4566221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4572292SN/A{ 4582292SN/A // If status is Running or idle, 4592292SN/A // call renameInsts() 4602292SN/A // If status is Unblocking, 4612292SN/A // buffer any instructions coming from decode 4622292SN/A // continue trying to empty skid buffer 4632292SN/A // check if stall conditions have passed 4642292SN/A 4652292SN/A if (renameStatus[tid] == Blocked) { 4662292SN/A ++renameBlockCycles; 4672292SN/A } else if (renameStatus[tid] == Squashing) { 4682292SN/A ++renameSquashCycles; 4692301SN/A } else if (renameStatus[tid] == SerializeStall) { 4702301SN/A ++renameSerializeStallCycles; 4713788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4723788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4733788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4743788Sgblack@eecs.umich.edu if (resumeSerialize) { 4753788Sgblack@eecs.umich.edu resumeSerialize = false; 4763788Sgblack@eecs.umich.edu block(tid); 4773788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4783788Sgblack@eecs.umich.edu } 4793798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4803798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4813798Sgblack@eecs.umich.edu block(tid); 4823798Sgblack@eecs.umich.edu resumeUnblocking = false; 4833798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4843798Sgblack@eecs.umich.edu } 4852292SN/A } 4862292SN/A 4872292SN/A if (renameStatus[tid] == Running || 4882292SN/A renameStatus[tid] == Idle) { 4892292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4902292SN/A "stage.\n", tid); 4912292SN/A 4922292SN/A renameInsts(tid); 4932292SN/A } else if (renameStatus[tid] == Unblocking) { 4942292SN/A renameInsts(tid); 4952292SN/A 4962292SN/A if (validInsts()) { 4972292SN/A // Add the current inputs to the skid buffer so they can be 4982292SN/A // reprocessed when this stage unblocks. 4992292SN/A skidInsert(tid); 5002292SN/A } 5012292SN/A 5022292SN/A // If we switched over to blocking, then there's a potential for 5032292SN/A // an overall status change. 5042292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5051858SN/A } 5061858SN/A} 5071858SN/A 5081858SN/Atemplate <class Impl> 5091858SN/Avoid 5106221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5111858SN/A{ 5122292SN/A // Instructions can be either in the skid buffer or the queue of 5132292SN/A // instructions coming from decode, depending on the status. 5142292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5152292SN/A skidBuffer[tid].size() : insts[tid].size(); 5161858SN/A 5172292SN/A // Check the decode queue to see if instructions are available. 5182292SN/A // If there are no available instructions to rename, then do nothing. 5192292SN/A if (insts_available == 0) { 5202292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5212292SN/A tid); 5222292SN/A // Should I change status to idle? 5232292SN/A ++renameIdleCycles; 5242292SN/A return; 5252292SN/A } else if (renameStatus[tid] == Unblocking) { 5262292SN/A ++renameUnblockCycles; 5272292SN/A } else if (renameStatus[tid] == Running) { 5282292SN/A ++renameRunCycles; 5292292SN/A } 5301858SN/A 5312292SN/A DynInstPtr inst; 5322292SN/A 5332292SN/A // Will have to do a different calculation for the number of free 5342292SN/A // entries. 5352292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5362292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5372292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5382292SN/A int min_free_entries = free_rob_entries; 5392292SN/A 5402292SN/A FullSource source = ROB; 5412292SN/A 5422292SN/A if (free_iq_entries < min_free_entries) { 5432292SN/A min_free_entries = free_iq_entries; 5442292SN/A source = IQ; 5452292SN/A } 5462292SN/A 5472292SN/A if (free_lsq_entries < min_free_entries) { 5482292SN/A min_free_entries = free_lsq_entries; 5492292SN/A source = LSQ; 5502292SN/A } 5512292SN/A 5522292SN/A // Check if there's any space left. 5532292SN/A if (min_free_entries <= 0) { 5542292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5552292SN/A "entries.\n" 5562292SN/A "ROB has %i free entries.\n" 5572292SN/A "IQ has %i free entries.\n" 5582292SN/A "LSQ has %i free entries.\n", 5592292SN/A tid, 5602292SN/A free_rob_entries, 5612292SN/A free_iq_entries, 5622292SN/A free_lsq_entries); 5632292SN/A 5642292SN/A blockThisCycle = true; 5652292SN/A 5662292SN/A block(tid); 5672292SN/A 5682292SN/A incrFullStat(source); 5692292SN/A 5702292SN/A return; 5712292SN/A } else if (min_free_entries < insts_available) { 5722292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5732292SN/A "%i insts available, but only %i insts can be " 5742292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5752292SN/A tid, insts_available, min_free_entries); 5762292SN/A 5772292SN/A insts_available = min_free_entries; 5782292SN/A 5792292SN/A blockThisCycle = true; 5802292SN/A 5812292SN/A incrFullStat(source); 5822292SN/A } 5832292SN/A 5842292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5852292SN/A skidBuffer[tid] : insts[tid]; 5862292SN/A 5872292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5882292SN/A "send iew.\n", tid, insts_available); 5892292SN/A 5902292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5912292SN/A "dispatched to IQ last cycle.\n", 5922292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5932292SN/A 5942292SN/A // Handle serializing the next instruction if necessary. 5952292SN/A if (serializeOnNextInst[tid]) { 5962292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5972292SN/A // ROB already empty; no need to serialize. 5982292SN/A serializeOnNextInst[tid] = false; 5992292SN/A } else if (!insts_to_rename.empty()) { 6002292SN/A insts_to_rename.front()->setSerializeBefore(); 6012292SN/A } 6022292SN/A } 6032292SN/A 6042292SN/A int renamed_insts = 0; 6052292SN/A 6062292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6072292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6082292SN/A 6092292SN/A assert(!insts_to_rename.empty()); 6102292SN/A 6112292SN/A inst = insts_to_rename.front(); 6122292SN/A 6132292SN/A insts_to_rename.pop_front(); 6142292SN/A 6152292SN/A if (renameStatus[tid] == Unblocking) { 6167720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6177720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6182292SN/A } 6192292SN/A 6202292SN/A if (inst->isSquashed()) { 6217720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6227720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6237720Sgblack@eecs.umich.edu inst->pcState()); 6242292SN/A 6252292SN/A ++renameSquashedInsts; 6262292SN/A 6272292SN/A // Decrement how many instructions are available. 6282292SN/A --insts_available; 6292292SN/A 6302292SN/A continue; 6312292SN/A } 6322292SN/A 6332292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6347720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6352292SN/A 6362292SN/A // Handle serializeAfter/serializeBefore instructions. 6372292SN/A // serializeAfter marks the next instruction as serializeBefore. 6382292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6392292SN/A // is empty. 6402336SN/A 6412336SN/A // In this model, IPR accesses are serialize before 6422336SN/A // instructions, and store conditionals are serialize after 6432336SN/A // instructions. This is mainly due to lack of support for 6442336SN/A // out-of-order operations of either of those classes of 6452336SN/A // instructions. 6462336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6472336SN/A !inst->isSerializeHandled()) { 6482292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6492292SN/A 6502301SN/A if (!inst->isTempSerializeBefore()) { 6512301SN/A renamedSerializing++; 6522292SN/A inst->setSerializeHandled(); 6532301SN/A } else { 6542301SN/A renamedTempSerializing++; 6552301SN/A } 6562292SN/A 6572301SN/A // Change status over to SerializeStall so that other stages know 6582292SN/A // what this is blocked on. 6592301SN/A renameStatus[tid] = SerializeStall; 6602292SN/A 6612301SN/A serializeInst[tid] = inst; 6622292SN/A 6632292SN/A blockThisCycle = true; 6642292SN/A 6652292SN/A break; 6662336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6672336SN/A !inst->isSerializeHandled()) { 6682292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6692292SN/A 6702307SN/A renamedSerializing++; 6712307SN/A 6722292SN/A inst->setSerializeHandled(); 6732292SN/A 6742292SN/A serializeAfter(insts_to_rename, tid); 6752292SN/A } 6762292SN/A 6772292SN/A // Check here to make sure there are enough destination registers 6782292SN/A // to rename to. Otherwise block. 6792292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6802292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6812292SN/A "physical registers to rename to.\n"); 6822292SN/A blockThisCycle = true; 6834345Sktlim@umich.edu insts_to_rename.push_front(inst); 6842292SN/A ++renameFullRegistersEvents; 6852292SN/A 6862292SN/A break; 6872292SN/A } 6882292SN/A 6892292SN/A renameSrcRegs(inst, inst->threadNumber); 6902292SN/A 6912292SN/A renameDestRegs(inst, inst->threadNumber); 6922292SN/A 6932292SN/A ++renamed_insts; 6942292SN/A 6958471SGiacomo.Gabrielli@arm.com#if TRACING_ON 6968471SGiacomo.Gabrielli@arm.com inst->renameTick = curTick(); 6978471SGiacomo.Gabrielli@arm.com#endif 6988471SGiacomo.Gabrielli@arm.com 6992292SN/A // Put instruction in rename queue. 7002292SN/A toIEW->insts[toIEWIndex] = inst; 7012292SN/A ++(toIEW->size); 7022292SN/A 7032292SN/A // Increment which instruction we're on. 7042292SN/A ++toIEWIndex; 7052292SN/A 7062292SN/A // Decrement how many instructions are available. 7072292SN/A --insts_available; 7082292SN/A } 7092292SN/A 7102292SN/A instsInProgress[tid] += renamed_insts; 7112307SN/A renameRenamedInsts += renamed_insts; 7122292SN/A 7132292SN/A // If we wrote to the time buffer, record this. 7142292SN/A if (toIEWIndex) { 7152292SN/A wroteToTimeBuffer = true; 7162292SN/A } 7172292SN/A 7182292SN/A // Check if there's any instructions left that haven't yet been renamed. 7192292SN/A // If so then block. 7202292SN/A if (insts_available) { 7212292SN/A blockThisCycle = true; 7222292SN/A } 7232292SN/A 7242292SN/A if (blockThisCycle) { 7252292SN/A block(tid); 7262292SN/A toDecode->renameUnblock[tid] = false; 7272292SN/A } 7282292SN/A} 7292292SN/A 7302292SN/Atemplate<class Impl> 7312292SN/Avoid 7326221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7332292SN/A{ 7342292SN/A DynInstPtr inst = NULL; 7352292SN/A 7362292SN/A while (!insts[tid].empty()) { 7372292SN/A inst = insts[tid].front(); 7382292SN/A 7392292SN/A insts[tid].pop_front(); 7402292SN/A 7412292SN/A assert(tid == inst->threadNumber); 7422292SN/A 7437720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7447720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7452292SN/A 7462307SN/A ++renameSkidInsts; 7472307SN/A 7482292SN/A skidBuffer[tid].push_back(inst); 7492292SN/A } 7502292SN/A 7512292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7523798Sgblack@eecs.umich.edu { 7533798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7543798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7553798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7563798Sgblack@eecs.umich.edu { 7573798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7587720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7593798Sgblack@eecs.umich.edu (*it)->seqNum); 7603798Sgblack@eecs.umich.edu } 7612292SN/A panic("Skidbuffer Exceeded Max Size"); 7623798Sgblack@eecs.umich.edu } 7632292SN/A} 7642292SN/A 7652292SN/Atemplate <class Impl> 7662292SN/Avoid 7672292SN/ADefaultRename<Impl>::sortInsts() 7682292SN/A{ 7692292SN/A int insts_from_decode = fromDecode->size; 7702329SN/A#ifdef DEBUG 7716221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 7726221Snate@binkert.org assert(insts[tid].empty()); 7732329SN/A#endif 7742292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7752292SN/A DynInstPtr inst = fromDecode->insts[i]; 7762292SN/A insts[inst->threadNumber].push_back(inst); 7772292SN/A } 7782292SN/A} 7792292SN/A 7802292SN/Atemplate<class Impl> 7812292SN/Abool 7822292SN/ADefaultRename<Impl>::skidsEmpty() 7832292SN/A{ 7846221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7856221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7862292SN/A 7873867Sbinkertn@umich.edu while (threads != end) { 7886221Snate@binkert.org ThreadID tid = *threads++; 7893867Sbinkertn@umich.edu 7903867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7912292SN/A return false; 7922292SN/A } 7932292SN/A 7942292SN/A return true; 7952292SN/A} 7962292SN/A 7972292SN/Atemplate<class Impl> 7982292SN/Avoid 7992292SN/ADefaultRename<Impl>::updateStatus() 8002292SN/A{ 8012292SN/A bool any_unblocking = false; 8022292SN/A 8036221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8046221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8052292SN/A 8063867Sbinkertn@umich.edu while (threads != end) { 8076221Snate@binkert.org ThreadID tid = *threads++; 8082292SN/A 8092292SN/A if (renameStatus[tid] == Unblocking) { 8102292SN/A any_unblocking = true; 8112292SN/A break; 8122292SN/A } 8132292SN/A } 8142292SN/A 8152292SN/A // Rename will have activity if it's unblocking. 8162292SN/A if (any_unblocking) { 8172292SN/A if (_status == Inactive) { 8182292SN/A _status = Active; 8192292SN/A 8202292SN/A DPRINTF(Activity, "Activating stage.\n"); 8212292SN/A 8222733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8232292SN/A } 8242292SN/A } else { 8252292SN/A // If it's not unblocking, then rename will not have any internal 8262292SN/A // activity. Switch it to inactive. 8272292SN/A if (_status == Active) { 8282292SN/A _status = Inactive; 8292292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8302292SN/A 8312733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8322292SN/A } 8332292SN/A } 8342292SN/A} 8352292SN/A 8362292SN/Atemplate <class Impl> 8372292SN/Abool 8386221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8392292SN/A{ 8402292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8412292SN/A 8422292SN/A // Add the current inputs onto the skid buffer, so they can be 8432292SN/A // reprocessed when this stage unblocks. 8442292SN/A skidInsert(tid); 8452292SN/A 8462292SN/A // Only signal backwards to block if the previous stages do not think 8472292SN/A // rename is already blocked. 8482292SN/A if (renameStatus[tid] != Blocked) { 8493798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8503798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8513798Sgblack@eecs.umich.edu // stages to block. 8523798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8532292SN/A toDecode->renameBlock[tid] = true; 8542292SN/A toDecode->renameUnblock[tid] = false; 8552292SN/A wroteToTimeBuffer = true; 8562292SN/A } 8572292SN/A 8582329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8592329SN/A // it would not know to complete the serialize stall. 8602301SN/A if (renameStatus[tid] != SerializeStall) { 8612292SN/A // Set status to Blocked. 8622292SN/A renameStatus[tid] = Blocked; 8632292SN/A return true; 8642292SN/A } 8652292SN/A } 8662292SN/A 8672292SN/A return false; 8682292SN/A} 8692292SN/A 8702292SN/Atemplate <class Impl> 8712292SN/Abool 8726221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8732292SN/A{ 8742292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8752292SN/A 8762292SN/A // Rename is done unblocking if the skid buffer is empty. 8772301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8782292SN/A 8792292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8802292SN/A 8812292SN/A toDecode->renameUnblock[tid] = true; 8822292SN/A wroteToTimeBuffer = true; 8832292SN/A 8842292SN/A renameStatus[tid] = Running; 8852292SN/A return true; 8862292SN/A } 8872292SN/A 8882292SN/A return false; 8892292SN/A} 8902292SN/A 8912292SN/Atemplate <class Impl> 8922292SN/Avoid 8936221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8942292SN/A{ 8952980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8962980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8972292SN/A 8981060SN/A // After a syscall squashes everything, the history buffer may be empty 8991060SN/A // but the ROB may still be squashing instructions. 9002292SN/A if (historyBuffer[tid].empty()) { 9011060SN/A return; 9021060SN/A } 9031060SN/A 9041060SN/A // Go through the most recent instructions, undoing the mappings 9051060SN/A // they did and freeing up the registers. 9062292SN/A while (!historyBuffer[tid].empty() && 9072292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 9082292SN/A assert(hb_it != historyBuffer[tid].end()); 9091062SN/A 9102292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9112292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 9121060SN/A 9132292SN/A // Tell the rename map to set the architected register to the 9142292SN/A // previous physical register that it was renamed to. 9152292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9161060SN/A 9172292SN/A // Put the renamed physical register back on the free list. 9182292SN/A freeList->addReg(hb_it->newPhysReg); 9191062SN/A 9202367SN/A // Be sure to mark its register as ready if it's a misc register. 9212367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9222367SN/A scoreboard->setReg(hb_it->newPhysReg); 9232367SN/A } 9242367SN/A 9252292SN/A historyBuffer[tid].erase(hb_it++); 9261061SN/A 9271062SN/A ++renameUndoneMaps; 9281060SN/A } 9291060SN/A} 9301060SN/A 9311060SN/Atemplate<class Impl> 9321060SN/Avoid 9336221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9341060SN/A{ 9352292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9362292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9372292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9382292SN/A 9392980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9402980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9411060SN/A 9421061SN/A --hb_it; 9431060SN/A 9442292SN/A if (historyBuffer[tid].empty()) { 9452292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9462292SN/A return; 9472292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9482292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9492292SN/A "that a syscall happened recently.\n", tid); 9501060SN/A return; 9511060SN/A } 9521060SN/A 9532292SN/A // Commit all the renames up until (and including) the committed sequence 9542292SN/A // number. Some or even all of the committed instructions may not have 9552292SN/A // rename histories if they did not have destination registers that were 9562292SN/A // renamed. 9572292SN/A while (!historyBuffer[tid].empty() && 9582292SN/A hb_it != historyBuffer[tid].end() && 9592292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9601060SN/A 9612329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9622329SN/A "[sn:%lli].\n", 9632292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9641061SN/A 9652292SN/A freeList->addReg((*hb_it).prevPhysReg); 9662292SN/A ++renameCommittedMaps; 9671061SN/A 9682292SN/A historyBuffer[tid].erase(hb_it--); 9691060SN/A } 9701060SN/A} 9711060SN/A 9721061SN/Atemplate <class Impl> 9731061SN/Ainline void 9746221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9751061SN/A{ 9762292SN/A assert(renameMap[tid] != 0); 9772292SN/A 9781061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9791061SN/A 9801061SN/A // Get the architectual register numbers from the source and 9811061SN/A // destination operands, and redirect them to the right register. 9821061SN/A // Will need to mark dependencies though. 9832292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9841061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9853773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9863773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9876313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 9887767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9897767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9905082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9915082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9926313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 9937767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9947767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9955082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9967649Sminkyu.jeong@arm.com } else if (src_reg < TheISA::Max_DepTag) { 9977767Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 9987767Sgblack@eecs.umich.edu TheISA::NumFloatRegs + TheISA::NumIntRegs; 9997767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 10007767Sgblack@eecs.umich.edu src_reg, flat_src_reg); 10017649Sminkyu.jeong@arm.com } else { 10027649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 10033773Sgblack@eecs.umich.edu } 10044352Sgblack@eecs.umich.edu 10053773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 10061061SN/A 10071061SN/A // Look up the source registers to get the phys. register they've 10081061SN/A // been renamed to, and set the sources to those registers. 10093773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 10101061SN/A 10112292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 10123773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 10132292SN/A (int)renamed_reg); 10141061SN/A 10151061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10161061SN/A 10172292SN/A // See if the register is ready or not. 10182292SN/A if (scoreboard->getReg(renamed_reg) == true) { 10197767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10207767Sgblack@eecs.umich.edu tid, renamed_reg); 10211061SN/A 10221061SN/A inst->markSrcRegReady(src_idx); 10234636Sgblack@eecs.umich.edu } else { 10247767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10257767Sgblack@eecs.umich.edu tid, renamed_reg); 10261061SN/A } 10271062SN/A 10281062SN/A ++renameRenameLookups; 10297897Shestness@cs.utexas.edu inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 10301061SN/A } 10311061SN/A} 10321061SN/A 10331061SN/Atemplate <class Impl> 10341061SN/Ainline void 10356221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10361061SN/A{ 10372292SN/A typename RenameMap::RenameInfo rename_result; 10381061SN/A 10391061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10401061SN/A 10412292SN/A // Rename the destination registers. 10422292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10432292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10443773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10453773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10464352Sgblack@eecs.umich.edu // Integer registers are flattened. 10476313Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 10487767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10497767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10507767Sgblack@eecs.umich.edu } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { 10517767Sgblack@eecs.umich.edu dest_reg = dest_reg - TheISA::FP_Base_DepTag; 10527767Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 10537767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10547767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10557767Sgblack@eecs.umich.edu flat_dest_reg += TheISA::NumIntRegs; 10567649Sminkyu.jeong@arm.com } else if (dest_reg < TheISA::Max_DepTag) { 10574352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10584352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10597767Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 10607767Sgblack@eecs.umich.edu TheISA::NumIntRegs + TheISA::NumFloatRegs; 10617767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 10627767Sgblack@eecs.umich.edu dest_reg, flat_dest_reg); 10637649Sminkyu.jeong@arm.com } else { 10647649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10653773Sgblack@eecs.umich.edu } 10663773Sgblack@eecs.umich.edu 10673773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10681061SN/A 10692292SN/A // Get the physical register that the destination will be 10702292SN/A // renamed to. 10713773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10721061SN/A 10732292SN/A //Mark Scoreboard entry as not ready 10747854SAli.Saidi@ARM.com if (dest_reg < TheISA::Ctrl_Base_DepTag) 10757854SAli.Saidi@ARM.com scoreboard->unsetReg(rename_result.first); 10761062SN/A 10772292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10783773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10792292SN/A (int)rename_result.first); 10801062SN/A 10812292SN/A // Record the rename information so that a history can be kept. 10823773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10832292SN/A rename_result.first, 10842292SN/A rename_result.second); 10851062SN/A 10862292SN/A historyBuffer[tid].push_front(hb_entry); 10871062SN/A 10882935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10892935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10902935Sksewell@umich.edu historyBuffer[tid].size(), 10912292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10921062SN/A 10932292SN/A // Tell the instruction to rename the appropriate destination 10942292SN/A // register (dest_idx) to the new physical register 10952292SN/A // (rename_result.first), and record the previous physical 10962292SN/A // register that the same logical register was renamed to 10972292SN/A // (rename_result.second). 10982292SN/A inst->renameDestReg(dest_idx, 10992292SN/A rename_result.first, 11002292SN/A rename_result.second); 11011062SN/A 11022292SN/A ++renameRenamedOperands; 11031061SN/A } 11041061SN/A} 11051061SN/A 11061061SN/Atemplate <class Impl> 11071061SN/Ainline int 11086221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11091061SN/A{ 11102292SN/A int num_free = freeEntries[tid].robEntries - 11112292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11122292SN/A 11132292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11142292SN/A 11152292SN/A return num_free; 11161061SN/A} 11171061SN/A 11181061SN/Atemplate <class Impl> 11191061SN/Ainline int 11206221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11211061SN/A{ 11222292SN/A int num_free = freeEntries[tid].iqEntries - 11232292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11242292SN/A 11252292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11262292SN/A 11272292SN/A return num_free; 11282292SN/A} 11292292SN/A 11302292SN/Atemplate <class Impl> 11312292SN/Ainline int 11326221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 11332292SN/A{ 11342292SN/A int num_free = freeEntries[tid].lsqEntries - 11352292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11362292SN/A 11372292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11382292SN/A 11392292SN/A return num_free; 11402292SN/A} 11412292SN/A 11422292SN/Atemplate <class Impl> 11432292SN/Aunsigned 11442292SN/ADefaultRename<Impl>::validInsts() 11452292SN/A{ 11462292SN/A unsigned inst_count = 0; 11472292SN/A 11482292SN/A for (int i=0; i<fromDecode->size; i++) { 11492731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11502292SN/A inst_count++; 11512292SN/A } 11522292SN/A 11532292SN/A return inst_count; 11542292SN/A} 11552292SN/A 11562292SN/Atemplate <class Impl> 11572292SN/Avoid 11586221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11592292SN/A{ 11602292SN/A if (fromIEW->iewBlock[tid]) { 11612292SN/A stalls[tid].iew = true; 11622292SN/A } 11632292SN/A 11642292SN/A if (fromIEW->iewUnblock[tid]) { 11652292SN/A assert(stalls[tid].iew); 11662292SN/A stalls[tid].iew = false; 11672292SN/A } 11682292SN/A 11692292SN/A if (fromCommit->commitBlock[tid]) { 11702292SN/A stalls[tid].commit = true; 11712292SN/A } 11722292SN/A 11732292SN/A if (fromCommit->commitUnblock[tid]) { 11742292SN/A assert(stalls[tid].commit); 11752292SN/A stalls[tid].commit = false; 11762292SN/A } 11772292SN/A} 11782292SN/A 11792292SN/Atemplate <class Impl> 11802292SN/Abool 11816221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11822292SN/A{ 11832292SN/A bool ret_val = false; 11842292SN/A 11852292SN/A if (stalls[tid].iew) { 11862292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11872292SN/A ret_val = true; 11882292SN/A } else if (stalls[tid].commit) { 11892292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11902292SN/A ret_val = true; 11912292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11922292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11932292SN/A ret_val = true; 11942292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11952292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11962292SN/A ret_val = true; 11972292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11982292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11992292SN/A ret_val = true; 12002292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 12012292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 12022292SN/A ret_val = true; 12032301SN/A } else if (renameStatus[tid] == SerializeStall && 12042292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12052301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12062292SN/A "empty.\n", 12072292SN/A tid); 12082292SN/A ret_val = true; 12092292SN/A } 12102292SN/A 12112292SN/A return ret_val; 12122292SN/A} 12132292SN/A 12142292SN/Atemplate <class Impl> 12152292SN/Avoid 12166221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12172292SN/A{ 12182292SN/A bool updated = false; 12192292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 12202292SN/A freeEntries[tid].iqEntries = 12212292SN/A fromIEW->iewInfo[tid].freeIQEntries; 12222292SN/A updated = true; 12232292SN/A } 12242292SN/A 12252292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 12262292SN/A freeEntries[tid].lsqEntries = 12272292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 12282292SN/A updated = true; 12292292SN/A } 12302292SN/A 12312292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12322292SN/A freeEntries[tid].robEntries = 12332292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12342292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12352292SN/A updated = true; 12362292SN/A } 12372292SN/A 12382292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12392292SN/A tid, 12402292SN/A freeEntries[tid].iqEntries, 12412292SN/A freeEntries[tid].robEntries, 12422292SN/A freeEntries[tid].lsqEntries); 12432292SN/A 12442292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12452292SN/A tid, instsInProgress[tid]); 12462292SN/A} 12472292SN/A 12482292SN/Atemplate <class Impl> 12492292SN/Abool 12506221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12512292SN/A{ 12522292SN/A // Check if there's a squash signal, squash if there is 12532292SN/A // Check stall signals, block if necessary. 12542292SN/A // If status was blocked 12552292SN/A // check if stall conditions have passed 12562292SN/A // if so then go to unblocking 12572292SN/A // If status was Squashing 12582292SN/A // check if squashing is not high. Switch to running this cycle. 12592301SN/A // If status was serialize stall 12602292SN/A // check if ROB is empty and no insts are in flight to the ROB 12612292SN/A 12622292SN/A readFreeEntries(tid); 12632292SN/A readStallSignals(tid); 12642292SN/A 12652292SN/A if (fromCommit->commitInfo[tid].squash) { 12662292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12672292SN/A "commit.\n", tid); 12682292SN/A 12694632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12702292SN/A 12712292SN/A return true; 12722292SN/A } 12732292SN/A 12742292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12752292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12762292SN/A 12772292SN/A renameStatus[tid] = Squashing; 12782292SN/A 12792292SN/A return true; 12802292SN/A } 12812292SN/A 12822292SN/A if (checkStall(tid)) { 12832292SN/A return block(tid); 12842292SN/A } 12852292SN/A 12862292SN/A if (renameStatus[tid] == Blocked) { 12872292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12882292SN/A tid); 12892292SN/A 12902292SN/A renameStatus[tid] = Unblocking; 12912292SN/A 12922292SN/A unblock(tid); 12932292SN/A 12942292SN/A return true; 12952292SN/A } 12962292SN/A 12972292SN/A if (renameStatus[tid] == Squashing) { 12982292SN/A // Switch status to running if rename isn't being told to block or 12992292SN/A // squash this cycle. 13003798Sgblack@eecs.umich.edu if (resumeSerialize) { 13013798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 13023798Sgblack@eecs.umich.edu tid); 13032292SN/A 13043798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13053798Sgblack@eecs.umich.edu return true; 13063798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13073798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13083798Sgblack@eecs.umich.edu tid); 13093798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13103798Sgblack@eecs.umich.edu return true; 13113798Sgblack@eecs.umich.edu } else { 13123788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13133788Sgblack@eecs.umich.edu tid); 13142292SN/A 13153788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13163788Sgblack@eecs.umich.edu return false; 13173788Sgblack@eecs.umich.edu } 13182292SN/A } 13192292SN/A 13202301SN/A if (renameStatus[tid] == SerializeStall) { 13212292SN/A // Stall ends once the ROB is free. 13222301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13232292SN/A "unblocking.\n", tid); 13242292SN/A 13252301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13262292SN/A 13272292SN/A renameStatus[tid] = Unblocking; 13282292SN/A 13292292SN/A unblock(tid); 13302292SN/A 13312292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13327720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13332292SN/A 13342292SN/A // Put instruction into queue here. 13352301SN/A serial_inst->clearSerializeBefore(); 13362292SN/A 13372292SN/A if (!skidBuffer[tid].empty()) { 13382301SN/A skidBuffer[tid].push_front(serial_inst); 13392292SN/A } else { 13402301SN/A insts[tid].push_front(serial_inst); 13412292SN/A } 13422292SN/A 13432292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13442703Sktlim@umich.edu " Adding to front of list.\n", tid); 13452292SN/A 13462301SN/A serializeInst[tid] = NULL; 13472292SN/A 13482292SN/A return true; 13492292SN/A } 13502292SN/A 13512292SN/A // If we've reached this point, we have not gotten any signals that 13522292SN/A // cause rename to change its status. Rename remains the same as before. 13532292SN/A return false; 13541061SN/A} 13551061SN/A 13561060SN/Atemplate<class Impl> 13571060SN/Avoid 13586221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13591060SN/A{ 13602292SN/A if (inst_list.empty()) { 13612292SN/A // Mark a bit to say that I must serialize on the next instruction. 13622292SN/A serializeOnNextInst[tid] = true; 13631060SN/A return; 13641060SN/A } 13651060SN/A 13662292SN/A // Set the next instruction as serializing. 13672292SN/A inst_list.front()->setSerializeBefore(); 13682292SN/A} 13692292SN/A 13702292SN/Atemplate <class Impl> 13712292SN/Ainline void 13722292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13732292SN/A{ 13742292SN/A switch (source) { 13752292SN/A case ROB: 13762292SN/A ++renameROBFullEvents; 13772292SN/A break; 13782292SN/A case IQ: 13792292SN/A ++renameIQFullEvents; 13802292SN/A break; 13812292SN/A case LSQ: 13822292SN/A ++renameLSQFullEvents; 13832292SN/A break; 13842292SN/A default: 13852292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13862292SN/A break; 13871060SN/A } 13882292SN/A} 13891060SN/A 13902292SN/Atemplate <class Impl> 13912292SN/Avoid 13922292SN/ADefaultRename<Impl>::dumpHistory() 13932292SN/A{ 13942980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13951060SN/A 13966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13971060SN/A 13986221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13991060SN/A 14006221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 14012292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 14022292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 14032292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 14041060SN/A 14052292SN/A buf_it++; 14061062SN/A } 14071060SN/A } 14081060SN/A} 1409