rename_impl.hh revision 7897
11689SN/A/* 27854SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37854SAli.Saidi@ARM.com * All rights reserved. 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412935Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 441060SN/A#include <list> 451060SN/A 463773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 476329Sgblack@eecs.umich.edu#include "arch/registers.hh" 481858SN/A#include "config/full_system.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 501717SN/A#include "cpu/o3/rename.hh" 515529Snate@binkert.org#include "params/DerivO3CPU.hh" 521060SN/A 536221Snate@binkert.orgusing namespace std; 546221Snate@binkert.org 551061SN/Atemplate <class Impl> 565529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 574329Sktlim@umich.edu : cpu(_cpu), 584329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 592292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 602292SN/A commitToRenameDelay(params->commitToRenameDelay), 612292SN/A renameWidth(params->renameWidth), 622292SN/A commitWidth(params->commitWidth), 633788Sgblack@eecs.umich.edu resumeSerialize(false), 643798Sgblack@eecs.umich.edu resumeUnblocking(false), 655529Snate@binkert.org numThreads(params->numThreads), 662361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 671060SN/A{ 682292SN/A _status = Inactive; 692292SN/A 706221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 716221Snate@binkert.org renameStatus[tid] = Idle; 722292SN/A 736221Snate@binkert.org freeEntries[tid].iqEntries = 0; 746221Snate@binkert.org freeEntries[tid].lsqEntries = 0; 756221Snate@binkert.org freeEntries[tid].robEntries = 0; 762292SN/A 776221Snate@binkert.org stalls[tid].iew = false; 786221Snate@binkert.org stalls[tid].commit = false; 796221Snate@binkert.org serializeInst[tid] = NULL; 802292SN/A 816221Snate@binkert.org instsInProgress[tid] = 0; 822292SN/A 836221Snate@binkert.org emptyROB[tid] = true; 842292SN/A 856221Snate@binkert.org serializeOnNextInst[tid] = false; 862292SN/A } 872292SN/A 882292SN/A // @todo: Make into a parameter. 892292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 902292SN/A} 912292SN/A 922292SN/Atemplate <class Impl> 932292SN/Astd::string 942292SN/ADefaultRename<Impl>::name() const 952292SN/A{ 962292SN/A return cpu->name() + ".rename"; 971060SN/A} 981060SN/A 991061SN/Atemplate <class Impl> 1001060SN/Avoid 1012292SN/ADefaultRename<Impl>::regStats() 1021062SN/A{ 1031062SN/A renameSquashCycles 1042301SN/A .name(name() + ".RENAME:SquashCycles") 1051062SN/A .desc("Number of cycles rename is squashing") 1061062SN/A .prereq(renameSquashCycles); 1071062SN/A renameIdleCycles 1082301SN/A .name(name() + ".RENAME:IdleCycles") 1091062SN/A .desc("Number of cycles rename is idle") 1101062SN/A .prereq(renameIdleCycles); 1111062SN/A renameBlockCycles 1122301SN/A .name(name() + ".RENAME:BlockCycles") 1131062SN/A .desc("Number of cycles rename is blocking") 1141062SN/A .prereq(renameBlockCycles); 1152301SN/A renameSerializeStallCycles 1162301SN/A .name(name() + ".RENAME:serializeStallCycles") 1172301SN/A .desc("count of cycles rename stalled for serializing inst") 1182301SN/A .flags(Stats::total); 1192292SN/A renameRunCycles 1202301SN/A .name(name() + ".RENAME:RunCycles") 1212292SN/A .desc("Number of cycles rename is running") 1222292SN/A .prereq(renameIdleCycles); 1231062SN/A renameUnblockCycles 1242301SN/A .name(name() + ".RENAME:UnblockCycles") 1251062SN/A .desc("Number of cycles rename is unblocking") 1261062SN/A .prereq(renameUnblockCycles); 1271062SN/A renameRenamedInsts 1282301SN/A .name(name() + ".RENAME:RenamedInsts") 1291062SN/A .desc("Number of instructions processed by rename") 1301062SN/A .prereq(renameRenamedInsts); 1311062SN/A renameSquashedInsts 1322301SN/A .name(name() + ".RENAME:SquashedInsts") 1331062SN/A .desc("Number of squashed instructions processed by rename") 1341062SN/A .prereq(renameSquashedInsts); 1351062SN/A renameROBFullEvents 1362301SN/A .name(name() + ".RENAME:ROBFullEvents") 1372292SN/A .desc("Number of times rename has blocked due to ROB full") 1381062SN/A .prereq(renameROBFullEvents); 1391062SN/A renameIQFullEvents 1402301SN/A .name(name() + ".RENAME:IQFullEvents") 1412292SN/A .desc("Number of times rename has blocked due to IQ full") 1421062SN/A .prereq(renameIQFullEvents); 1432292SN/A renameLSQFullEvents 1442301SN/A .name(name() + ".RENAME:LSQFullEvents") 1452292SN/A .desc("Number of times rename has blocked due to LSQ full") 1462292SN/A .prereq(renameLSQFullEvents); 1471062SN/A renameFullRegistersEvents 1482301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1491062SN/A .desc("Number of times there has been no free registers") 1501062SN/A .prereq(renameFullRegistersEvents); 1511062SN/A renameRenamedOperands 1522301SN/A .name(name() + ".RENAME:RenamedOperands") 1531062SN/A .desc("Number of destination operands rename has renamed") 1541062SN/A .prereq(renameRenamedOperands); 1551062SN/A renameRenameLookups 1562301SN/A .name(name() + ".RENAME:RenameLookups") 1571062SN/A .desc("Number of register rename lookups that rename has made") 1581062SN/A .prereq(renameRenameLookups); 1591062SN/A renameCommittedMaps 1602301SN/A .name(name() + ".RENAME:CommittedMaps") 1611062SN/A .desc("Number of HB maps that are committed") 1621062SN/A .prereq(renameCommittedMaps); 1631062SN/A renameUndoneMaps 1642301SN/A .name(name() + ".RENAME:UndoneMaps") 1651062SN/A .desc("Number of HB maps that are undone due to squashing") 1661062SN/A .prereq(renameUndoneMaps); 1672301SN/A renamedSerializing 1682301SN/A .name(name() + ".RENAME:serializingInsts") 1692301SN/A .desc("count of serializing insts renamed") 1702301SN/A .flags(Stats::total) 1712301SN/A ; 1722301SN/A renamedTempSerializing 1732301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1742301SN/A .desc("count of temporary serializing insts renamed") 1752301SN/A .flags(Stats::total) 1762301SN/A ; 1772307SN/A renameSkidInsts 1782307SN/A .name(name() + ".RENAME:skidInsts") 1792307SN/A .desc("count of insts added to the skid buffer") 1802307SN/A .flags(Stats::total) 1812307SN/A ; 1827897Shestness@cs.utexas.edu intRenameLookups 1837897Shestness@cs.utexas.edu .name(name() + ".RENAME:int_rename_lookups") 1847897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1857897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1867897Shestness@cs.utexas.edu fpRenameLookups 1877897Shestness@cs.utexas.edu .name(name() + ".RENAME:fp_rename_lookups") 1887897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1897897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1901062SN/A} 1911062SN/A 1921062SN/Atemplate <class Impl> 1931062SN/Avoid 1942292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1951060SN/A{ 1961060SN/A timeBuffer = tb_ptr; 1971060SN/A 1981060SN/A // Setup wire to read information from time buffer, from IEW stage. 1991060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2001060SN/A 2011060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2021060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2031060SN/A 2041060SN/A // Setup wire to write information to previous stages. 2051060SN/A toDecode = timeBuffer->getWire(0); 2061060SN/A} 2071060SN/A 2081061SN/Atemplate <class Impl> 2091060SN/Avoid 2102292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2111060SN/A{ 2121060SN/A renameQueue = rq_ptr; 2131060SN/A 2141060SN/A // Setup wire to write information to future stages. 2151060SN/A toIEW = renameQueue->getWire(0); 2161060SN/A} 2171060SN/A 2181061SN/Atemplate <class Impl> 2191060SN/Avoid 2202292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2211060SN/A{ 2221060SN/A decodeQueue = dq_ptr; 2231060SN/A 2241060SN/A // Setup wire to get information from decode. 2251060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2261060SN/A} 2271060SN/A 2281061SN/Atemplate <class Impl> 2291060SN/Avoid 2302292SN/ADefaultRename<Impl>::initStage() 2311060SN/A{ 2322329SN/A // Grab the number of free entries directly from the stages. 2336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2342292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2352292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2362292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2372292SN/A emptyROB[tid] = true; 2382292SN/A } 2391060SN/A} 2401060SN/A 2412292SN/Atemplate<class Impl> 2422292SN/Avoid 2436221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2442292SN/A{ 2452292SN/A activeThreads = at_ptr; 2462292SN/A} 2472292SN/A 2482292SN/A 2491061SN/Atemplate <class Impl> 2501060SN/Avoid 2512292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2521060SN/A{ 2536221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2546221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2551060SN/A} 2561060SN/A 2571061SN/Atemplate <class Impl> 2581060SN/Avoid 2592292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2601060SN/A{ 2612292SN/A freeList = fl_ptr; 2622292SN/A} 2631060SN/A 2642292SN/Atemplate<class Impl> 2652292SN/Avoid 2662292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2672292SN/A{ 2682292SN/A scoreboard = _scoreboard; 2691060SN/A} 2701060SN/A 2711061SN/Atemplate <class Impl> 2722863Sktlim@umich.edubool 2732843Sktlim@umich.eduDefaultRename<Impl>::drain() 2741060SN/A{ 2752348SN/A // Rename is ready to switch out at any time. 2762843Sktlim@umich.edu cpu->signalDrained(); 2772863Sktlim@umich.edu return true; 2782316SN/A} 2791060SN/A 2802316SN/Atemplate <class Impl> 2812316SN/Avoid 2822843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2832316SN/A{ 2842348SN/A // Clear any state, fix up the rename map. 2856221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2862980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2876221Snate@binkert.org historyBuffer[tid].begin(); 2882307SN/A 2896221Snate@binkert.org while (!historyBuffer[tid].empty()) { 2906221Snate@binkert.org assert(hb_it != historyBuffer[tid].end()); 2912307SN/A 2922307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2936221Snate@binkert.org "number %i.\n", tid, (*hb_it).instSeqNum); 2942307SN/A 2952307SN/A // Tell the rename map to set the architected register to the 2962307SN/A // previous physical register that it was renamed to. 2976221Snate@binkert.org renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2982307SN/A 2992307SN/A // Put the renamed physical register back on the free list. 3002307SN/A freeList->addReg(hb_it->newPhysReg); 3012307SN/A 3022361SN/A // Be sure to mark its register as ready if it's a misc register. 3032361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 3042361SN/A scoreboard->setReg(hb_it->newPhysReg); 3052361SN/A } 3062361SN/A 3076221Snate@binkert.org historyBuffer[tid].erase(hb_it++); 3082307SN/A } 3096221Snate@binkert.org insts[tid].clear(); 3106221Snate@binkert.org skidBuffer[tid].clear(); 3111060SN/A } 3121060SN/A} 3131060SN/A 3141061SN/Atemplate <class Impl> 3151060SN/Avoid 3162307SN/ADefaultRename<Impl>::takeOverFrom() 3171060SN/A{ 3182307SN/A _status = Inactive; 3192307SN/A initStage(); 3201060SN/A 3212329SN/A // Reset all state prior to taking over from the other CPU. 3226221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3236221Snate@binkert.org renameStatus[tid] = Idle; 3241060SN/A 3256221Snate@binkert.org stalls[tid].iew = false; 3266221Snate@binkert.org stalls[tid].commit = false; 3276221Snate@binkert.org serializeInst[tid] = NULL; 3282307SN/A 3296221Snate@binkert.org instsInProgress[tid] = 0; 3302307SN/A 3316221Snate@binkert.org emptyROB[tid] = true; 3322307SN/A 3336221Snate@binkert.org serializeOnNextInst[tid] = false; 3342307SN/A } 3352307SN/A} 3362307SN/A 3372307SN/Atemplate <class Impl> 3382307SN/Avoid 3396221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3401858SN/A{ 3412292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3421858SN/A 3432292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3442292SN/A // If it still needs to block, the blocking should happen the next 3452292SN/A // cycle and there should be space to hold everything due to the squash. 3462292SN/A if (renameStatus[tid] == Blocked || 3473788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3482292SN/A toDecode->renameUnblock[tid] = 1; 3492698Sktlim@umich.edu 3503788Sgblack@eecs.umich.edu resumeSerialize = false; 3512301SN/A serializeInst[tid] = NULL; 3523788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3533788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3543788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3553788Sgblack@eecs.umich.edu resumeSerialize = true; 3563788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3573788Sgblack@eecs.umich.edu } else { 3583788Sgblack@eecs.umich.edu resumeSerialize = false; 3593788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3603788Sgblack@eecs.umich.edu 3613788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3623788Sgblack@eecs.umich.edu } 3632292SN/A } 3642292SN/A 3652292SN/A // Set the status to Squashing. 3662292SN/A renameStatus[tid] = Squashing; 3672292SN/A 3682329SN/A // Squash any instructions from decode. 3692292SN/A unsigned squashCount = 0; 3702292SN/A 3712292SN/A for (int i=0; i<fromDecode->size; i++) { 3722935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3732935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3742731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3752292SN/A wroteToTimeBuffer = true; 3762292SN/A squashCount++; 3772292SN/A } 3782935Sksewell@umich.edu 3792292SN/A } 3802292SN/A 3812935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3824632Sgblack@eecs.umich.edu // insts in them. 3833093Sksewell@umich.edu insts[tid].clear(); 3842292SN/A 3852292SN/A // Clear the skid buffer in case it has any data in it. 3863093Sksewell@umich.edu skidBuffer[tid].clear(); 3874632Sgblack@eecs.umich.edu 3882935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3892292SN/A} 3902292SN/A 3912292SN/Atemplate <class Impl> 3922292SN/Avoid 3932292SN/ADefaultRename<Impl>::tick() 3942292SN/A{ 3952292SN/A wroteToTimeBuffer = false; 3962292SN/A 3972292SN/A blockThisCycle = false; 3982292SN/A 3992292SN/A bool status_change = false; 4002292SN/A 4012292SN/A toIEWIndex = 0; 4022292SN/A 4032292SN/A sortInsts(); 4042292SN/A 4056221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4066221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4072292SN/A 4082292SN/A // Check stall and squash signals. 4093867Sbinkertn@umich.edu while (threads != end) { 4106221Snate@binkert.org ThreadID tid = *threads++; 4112292SN/A 4122292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4132292SN/A 4142292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4152292SN/A 4162292SN/A rename(status_change, tid); 4172292SN/A } 4182292SN/A 4192292SN/A if (status_change) { 4202292SN/A updateStatus(); 4212292SN/A } 4222292SN/A 4232292SN/A if (wroteToTimeBuffer) { 4242292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4252292SN/A cpu->activityThisCycle(); 4262292SN/A } 4272292SN/A 4283867Sbinkertn@umich.edu threads = activeThreads->begin(); 4292292SN/A 4303867Sbinkertn@umich.edu while (threads != end) { 4316221Snate@binkert.org ThreadID tid = *threads++; 4322292SN/A 4332292SN/A // If we committed this cycle then doneSeqNum will be > 0 4342292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4352292SN/A !fromCommit->commitInfo[tid].squash && 4362292SN/A renameStatus[tid] != Squashing) { 4372292SN/A 4382292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4392292SN/A tid); 4402292SN/A } 4412292SN/A } 4422292SN/A 4432292SN/A // @todo: make into updateProgress function 4446221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4452292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4462292SN/A 4472292SN/A assert(instsInProgress[tid] >=0); 4482292SN/A } 4492292SN/A 4502292SN/A} 4512292SN/A 4522292SN/Atemplate<class Impl> 4532292SN/Avoid 4546221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4552292SN/A{ 4562292SN/A // If status is Running or idle, 4572292SN/A // call renameInsts() 4582292SN/A // If status is Unblocking, 4592292SN/A // buffer any instructions coming from decode 4602292SN/A // continue trying to empty skid buffer 4612292SN/A // check if stall conditions have passed 4622292SN/A 4632292SN/A if (renameStatus[tid] == Blocked) { 4642292SN/A ++renameBlockCycles; 4652292SN/A } else if (renameStatus[tid] == Squashing) { 4662292SN/A ++renameSquashCycles; 4672301SN/A } else if (renameStatus[tid] == SerializeStall) { 4682301SN/A ++renameSerializeStallCycles; 4693788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4703788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4713788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4723788Sgblack@eecs.umich.edu if (resumeSerialize) { 4733788Sgblack@eecs.umich.edu resumeSerialize = false; 4743788Sgblack@eecs.umich.edu block(tid); 4753788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4763788Sgblack@eecs.umich.edu } 4773798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4783798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4793798Sgblack@eecs.umich.edu block(tid); 4803798Sgblack@eecs.umich.edu resumeUnblocking = false; 4813798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4823798Sgblack@eecs.umich.edu } 4832292SN/A } 4842292SN/A 4852292SN/A if (renameStatus[tid] == Running || 4862292SN/A renameStatus[tid] == Idle) { 4872292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4882292SN/A "stage.\n", tid); 4892292SN/A 4902292SN/A renameInsts(tid); 4912292SN/A } else if (renameStatus[tid] == Unblocking) { 4922292SN/A renameInsts(tid); 4932292SN/A 4942292SN/A if (validInsts()) { 4952292SN/A // Add the current inputs to the skid buffer so they can be 4962292SN/A // reprocessed when this stage unblocks. 4972292SN/A skidInsert(tid); 4982292SN/A } 4992292SN/A 5002292SN/A // If we switched over to blocking, then there's a potential for 5012292SN/A // an overall status change. 5022292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5031858SN/A } 5041858SN/A} 5051858SN/A 5061858SN/Atemplate <class Impl> 5071858SN/Avoid 5086221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5091858SN/A{ 5102292SN/A // Instructions can be either in the skid buffer or the queue of 5112292SN/A // instructions coming from decode, depending on the status. 5122292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5132292SN/A skidBuffer[tid].size() : insts[tid].size(); 5141858SN/A 5152292SN/A // Check the decode queue to see if instructions are available. 5162292SN/A // If there are no available instructions to rename, then do nothing. 5172292SN/A if (insts_available == 0) { 5182292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5192292SN/A tid); 5202292SN/A // Should I change status to idle? 5212292SN/A ++renameIdleCycles; 5222292SN/A return; 5232292SN/A } else if (renameStatus[tid] == Unblocking) { 5242292SN/A ++renameUnblockCycles; 5252292SN/A } else if (renameStatus[tid] == Running) { 5262292SN/A ++renameRunCycles; 5272292SN/A } 5281858SN/A 5292292SN/A DynInstPtr inst; 5302292SN/A 5312292SN/A // Will have to do a different calculation for the number of free 5322292SN/A // entries. 5332292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5342292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5352292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5362292SN/A int min_free_entries = free_rob_entries; 5372292SN/A 5382292SN/A FullSource source = ROB; 5392292SN/A 5402292SN/A if (free_iq_entries < min_free_entries) { 5412292SN/A min_free_entries = free_iq_entries; 5422292SN/A source = IQ; 5432292SN/A } 5442292SN/A 5452292SN/A if (free_lsq_entries < min_free_entries) { 5462292SN/A min_free_entries = free_lsq_entries; 5472292SN/A source = LSQ; 5482292SN/A } 5492292SN/A 5502292SN/A // Check if there's any space left. 5512292SN/A if (min_free_entries <= 0) { 5522292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5532292SN/A "entries.\n" 5542292SN/A "ROB has %i free entries.\n" 5552292SN/A "IQ has %i free entries.\n" 5562292SN/A "LSQ has %i free entries.\n", 5572292SN/A tid, 5582292SN/A free_rob_entries, 5592292SN/A free_iq_entries, 5602292SN/A free_lsq_entries); 5612292SN/A 5622292SN/A blockThisCycle = true; 5632292SN/A 5642292SN/A block(tid); 5652292SN/A 5662292SN/A incrFullStat(source); 5672292SN/A 5682292SN/A return; 5692292SN/A } else if (min_free_entries < insts_available) { 5702292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5712292SN/A "%i insts available, but only %i insts can be " 5722292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5732292SN/A tid, insts_available, min_free_entries); 5742292SN/A 5752292SN/A insts_available = min_free_entries; 5762292SN/A 5772292SN/A blockThisCycle = true; 5782292SN/A 5792292SN/A incrFullStat(source); 5802292SN/A } 5812292SN/A 5822292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5832292SN/A skidBuffer[tid] : insts[tid]; 5842292SN/A 5852292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5862292SN/A "send iew.\n", tid, insts_available); 5872292SN/A 5882292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5892292SN/A "dispatched to IQ last cycle.\n", 5902292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5912292SN/A 5922292SN/A // Handle serializing the next instruction if necessary. 5932292SN/A if (serializeOnNextInst[tid]) { 5942292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5952292SN/A // ROB already empty; no need to serialize. 5962292SN/A serializeOnNextInst[tid] = false; 5972292SN/A } else if (!insts_to_rename.empty()) { 5982292SN/A insts_to_rename.front()->setSerializeBefore(); 5992292SN/A } 6002292SN/A } 6012292SN/A 6022292SN/A int renamed_insts = 0; 6032292SN/A 6042292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6052292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6062292SN/A 6072292SN/A assert(!insts_to_rename.empty()); 6082292SN/A 6092292SN/A inst = insts_to_rename.front(); 6102292SN/A 6112292SN/A insts_to_rename.pop_front(); 6122292SN/A 6132292SN/A if (renameStatus[tid] == Unblocking) { 6147720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6157720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6162292SN/A } 6172292SN/A 6182292SN/A if (inst->isSquashed()) { 6197720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6207720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6217720Sgblack@eecs.umich.edu inst->pcState()); 6222292SN/A 6232292SN/A ++renameSquashedInsts; 6242292SN/A 6252292SN/A // Decrement how many instructions are available. 6262292SN/A --insts_available; 6272292SN/A 6282292SN/A continue; 6292292SN/A } 6302292SN/A 6312292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6327720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6332292SN/A 6342292SN/A // Handle serializeAfter/serializeBefore instructions. 6352292SN/A // serializeAfter marks the next instruction as serializeBefore. 6362292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6372292SN/A // is empty. 6382336SN/A 6392336SN/A // In this model, IPR accesses are serialize before 6402336SN/A // instructions, and store conditionals are serialize after 6412336SN/A // instructions. This is mainly due to lack of support for 6422336SN/A // out-of-order operations of either of those classes of 6432336SN/A // instructions. 6442336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6452336SN/A !inst->isSerializeHandled()) { 6462292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6472292SN/A 6482301SN/A if (!inst->isTempSerializeBefore()) { 6492301SN/A renamedSerializing++; 6502292SN/A inst->setSerializeHandled(); 6512301SN/A } else { 6522301SN/A renamedTempSerializing++; 6532301SN/A } 6542292SN/A 6552301SN/A // Change status over to SerializeStall so that other stages know 6562292SN/A // what this is blocked on. 6572301SN/A renameStatus[tid] = SerializeStall; 6582292SN/A 6592301SN/A serializeInst[tid] = inst; 6602292SN/A 6612292SN/A blockThisCycle = true; 6622292SN/A 6632292SN/A break; 6642336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6652336SN/A !inst->isSerializeHandled()) { 6662292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6672292SN/A 6682307SN/A renamedSerializing++; 6692307SN/A 6702292SN/A inst->setSerializeHandled(); 6712292SN/A 6722292SN/A serializeAfter(insts_to_rename, tid); 6732292SN/A } 6742292SN/A 6752292SN/A // Check here to make sure there are enough destination registers 6762292SN/A // to rename to. Otherwise block. 6772292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6782292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6792292SN/A "physical registers to rename to.\n"); 6802292SN/A blockThisCycle = true; 6814345Sktlim@umich.edu insts_to_rename.push_front(inst); 6822292SN/A ++renameFullRegistersEvents; 6832292SN/A 6842292SN/A break; 6852292SN/A } 6862292SN/A 6872292SN/A renameSrcRegs(inst, inst->threadNumber); 6882292SN/A 6892292SN/A renameDestRegs(inst, inst->threadNumber); 6902292SN/A 6912292SN/A ++renamed_insts; 6922292SN/A 6932292SN/A // Put instruction in rename queue. 6942292SN/A toIEW->insts[toIEWIndex] = inst; 6952292SN/A ++(toIEW->size); 6962292SN/A 6972292SN/A // Increment which instruction we're on. 6982292SN/A ++toIEWIndex; 6992292SN/A 7002292SN/A // Decrement how many instructions are available. 7012292SN/A --insts_available; 7022292SN/A } 7032292SN/A 7042292SN/A instsInProgress[tid] += renamed_insts; 7052307SN/A renameRenamedInsts += renamed_insts; 7062292SN/A 7072292SN/A // If we wrote to the time buffer, record this. 7082292SN/A if (toIEWIndex) { 7092292SN/A wroteToTimeBuffer = true; 7102292SN/A } 7112292SN/A 7122292SN/A // Check if there's any instructions left that haven't yet been renamed. 7132292SN/A // If so then block. 7142292SN/A if (insts_available) { 7152292SN/A blockThisCycle = true; 7162292SN/A } 7172292SN/A 7182292SN/A if (blockThisCycle) { 7192292SN/A block(tid); 7202292SN/A toDecode->renameUnblock[tid] = false; 7212292SN/A } 7222292SN/A} 7232292SN/A 7242292SN/Atemplate<class Impl> 7252292SN/Avoid 7266221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7272292SN/A{ 7282292SN/A DynInstPtr inst = NULL; 7292292SN/A 7302292SN/A while (!insts[tid].empty()) { 7312292SN/A inst = insts[tid].front(); 7322292SN/A 7332292SN/A insts[tid].pop_front(); 7342292SN/A 7352292SN/A assert(tid == inst->threadNumber); 7362292SN/A 7377720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7387720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7392292SN/A 7402307SN/A ++renameSkidInsts; 7412307SN/A 7422292SN/A skidBuffer[tid].push_back(inst); 7432292SN/A } 7442292SN/A 7452292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7463798Sgblack@eecs.umich.edu { 7473798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7483798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7493798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7503798Sgblack@eecs.umich.edu { 7513798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7527720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7533798Sgblack@eecs.umich.edu (*it)->seqNum); 7543798Sgblack@eecs.umich.edu } 7552292SN/A panic("Skidbuffer Exceeded Max Size"); 7563798Sgblack@eecs.umich.edu } 7572292SN/A} 7582292SN/A 7592292SN/Atemplate <class Impl> 7602292SN/Avoid 7612292SN/ADefaultRename<Impl>::sortInsts() 7622292SN/A{ 7632292SN/A int insts_from_decode = fromDecode->size; 7642329SN/A#ifdef DEBUG 7656221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 7666221Snate@binkert.org assert(insts[tid].empty()); 7672329SN/A#endif 7682292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7692292SN/A DynInstPtr inst = fromDecode->insts[i]; 7702292SN/A insts[inst->threadNumber].push_back(inst); 7712292SN/A } 7722292SN/A} 7732292SN/A 7742292SN/Atemplate<class Impl> 7752292SN/Abool 7762292SN/ADefaultRename<Impl>::skidsEmpty() 7772292SN/A{ 7786221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7796221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7802292SN/A 7813867Sbinkertn@umich.edu while (threads != end) { 7826221Snate@binkert.org ThreadID tid = *threads++; 7833867Sbinkertn@umich.edu 7843867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7852292SN/A return false; 7862292SN/A } 7872292SN/A 7882292SN/A return true; 7892292SN/A} 7902292SN/A 7912292SN/Atemplate<class Impl> 7922292SN/Avoid 7932292SN/ADefaultRename<Impl>::updateStatus() 7942292SN/A{ 7952292SN/A bool any_unblocking = false; 7962292SN/A 7976221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7986221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7992292SN/A 8003867Sbinkertn@umich.edu while (threads != end) { 8016221Snate@binkert.org ThreadID tid = *threads++; 8022292SN/A 8032292SN/A if (renameStatus[tid] == Unblocking) { 8042292SN/A any_unblocking = true; 8052292SN/A break; 8062292SN/A } 8072292SN/A } 8082292SN/A 8092292SN/A // Rename will have activity if it's unblocking. 8102292SN/A if (any_unblocking) { 8112292SN/A if (_status == Inactive) { 8122292SN/A _status = Active; 8132292SN/A 8142292SN/A DPRINTF(Activity, "Activating stage.\n"); 8152292SN/A 8162733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8172292SN/A } 8182292SN/A } else { 8192292SN/A // If it's not unblocking, then rename will not have any internal 8202292SN/A // activity. Switch it to inactive. 8212292SN/A if (_status == Active) { 8222292SN/A _status = Inactive; 8232292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8242292SN/A 8252733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8262292SN/A } 8272292SN/A } 8282292SN/A} 8292292SN/A 8302292SN/Atemplate <class Impl> 8312292SN/Abool 8326221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8332292SN/A{ 8342292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8352292SN/A 8362292SN/A // Add the current inputs onto the skid buffer, so they can be 8372292SN/A // reprocessed when this stage unblocks. 8382292SN/A skidInsert(tid); 8392292SN/A 8402292SN/A // Only signal backwards to block if the previous stages do not think 8412292SN/A // rename is already blocked. 8422292SN/A if (renameStatus[tid] != Blocked) { 8433798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8443798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8453798Sgblack@eecs.umich.edu // stages to block. 8463798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8472292SN/A toDecode->renameBlock[tid] = true; 8482292SN/A toDecode->renameUnblock[tid] = false; 8492292SN/A wroteToTimeBuffer = true; 8502292SN/A } 8512292SN/A 8522329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8532329SN/A // it would not know to complete the serialize stall. 8542301SN/A if (renameStatus[tid] != SerializeStall) { 8552292SN/A // Set status to Blocked. 8562292SN/A renameStatus[tid] = Blocked; 8572292SN/A return true; 8582292SN/A } 8592292SN/A } 8602292SN/A 8612292SN/A return false; 8622292SN/A} 8632292SN/A 8642292SN/Atemplate <class Impl> 8652292SN/Abool 8666221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8672292SN/A{ 8682292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8692292SN/A 8702292SN/A // Rename is done unblocking if the skid buffer is empty. 8712301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8722292SN/A 8732292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8742292SN/A 8752292SN/A toDecode->renameUnblock[tid] = true; 8762292SN/A wroteToTimeBuffer = true; 8772292SN/A 8782292SN/A renameStatus[tid] = Running; 8792292SN/A return true; 8802292SN/A } 8812292SN/A 8822292SN/A return false; 8832292SN/A} 8842292SN/A 8852292SN/Atemplate <class Impl> 8862292SN/Avoid 8876221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8882292SN/A{ 8892980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8902980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8912292SN/A 8921060SN/A // After a syscall squashes everything, the history buffer may be empty 8931060SN/A // but the ROB may still be squashing instructions. 8942292SN/A if (historyBuffer[tid].empty()) { 8951060SN/A return; 8961060SN/A } 8971060SN/A 8981060SN/A // Go through the most recent instructions, undoing the mappings 8991060SN/A // they did and freeing up the registers. 9002292SN/A while (!historyBuffer[tid].empty() && 9012292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 9022292SN/A assert(hb_it != historyBuffer[tid].end()); 9031062SN/A 9042292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9052292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 9061060SN/A 9072292SN/A // Tell the rename map to set the architected register to the 9082292SN/A // previous physical register that it was renamed to. 9092292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9101060SN/A 9112292SN/A // Put the renamed physical register back on the free list. 9122292SN/A freeList->addReg(hb_it->newPhysReg); 9131062SN/A 9142367SN/A // Be sure to mark its register as ready if it's a misc register. 9152367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9162367SN/A scoreboard->setReg(hb_it->newPhysReg); 9172367SN/A } 9182367SN/A 9192292SN/A historyBuffer[tid].erase(hb_it++); 9201061SN/A 9211062SN/A ++renameUndoneMaps; 9221060SN/A } 9231060SN/A} 9241060SN/A 9251060SN/Atemplate<class Impl> 9261060SN/Avoid 9276221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9281060SN/A{ 9292292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9302292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9312292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9322292SN/A 9332980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9342980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9351060SN/A 9361061SN/A --hb_it; 9371060SN/A 9382292SN/A if (historyBuffer[tid].empty()) { 9392292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9402292SN/A return; 9412292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9422292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9432292SN/A "that a syscall happened recently.\n", tid); 9441060SN/A return; 9451060SN/A } 9461060SN/A 9472292SN/A // Commit all the renames up until (and including) the committed sequence 9482292SN/A // number. Some or even all of the committed instructions may not have 9492292SN/A // rename histories if they did not have destination registers that were 9502292SN/A // renamed. 9512292SN/A while (!historyBuffer[tid].empty() && 9522292SN/A hb_it != historyBuffer[tid].end() && 9532292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9541060SN/A 9552329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9562329SN/A "[sn:%lli].\n", 9572292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9581061SN/A 9592292SN/A freeList->addReg((*hb_it).prevPhysReg); 9602292SN/A ++renameCommittedMaps; 9611061SN/A 9622292SN/A historyBuffer[tid].erase(hb_it--); 9631060SN/A } 9641060SN/A} 9651060SN/A 9661061SN/Atemplate <class Impl> 9671061SN/Ainline void 9686221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9691061SN/A{ 9702292SN/A assert(renameMap[tid] != 0); 9712292SN/A 9721061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9731061SN/A 9741061SN/A // Get the architectual register numbers from the source and 9751061SN/A // destination operands, and redirect them to the right register. 9761061SN/A // Will need to mark dependencies though. 9772292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9781061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9793773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9803773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9816313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 9827767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9837767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9845082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9855082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9866313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 9877767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9887767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9895082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9907649Sminkyu.jeong@arm.com } else if (src_reg < TheISA::Max_DepTag) { 9917767Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 9927767Sgblack@eecs.umich.edu TheISA::NumFloatRegs + TheISA::NumIntRegs; 9937767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 9947767Sgblack@eecs.umich.edu src_reg, flat_src_reg); 9957649Sminkyu.jeong@arm.com } else { 9967649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9973773Sgblack@eecs.umich.edu } 9984352Sgblack@eecs.umich.edu 9993773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 10001061SN/A 10011061SN/A // Look up the source registers to get the phys. register they've 10021061SN/A // been renamed to, and set the sources to those registers. 10033773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 10041061SN/A 10052292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 10063773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 10072292SN/A (int)renamed_reg); 10081061SN/A 10091061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10101061SN/A 10112292SN/A // See if the register is ready or not. 10122292SN/A if (scoreboard->getReg(renamed_reg) == true) { 10137767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10147767Sgblack@eecs.umich.edu tid, renamed_reg); 10151061SN/A 10161061SN/A inst->markSrcRegReady(src_idx); 10174636Sgblack@eecs.umich.edu } else { 10187767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10197767Sgblack@eecs.umich.edu tid, renamed_reg); 10201061SN/A } 10211062SN/A 10221062SN/A ++renameRenameLookups; 10237897Shestness@cs.utexas.edu inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 10241061SN/A } 10251061SN/A} 10261061SN/A 10271061SN/Atemplate <class Impl> 10281061SN/Ainline void 10296221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10301061SN/A{ 10312292SN/A typename RenameMap::RenameInfo rename_result; 10321061SN/A 10331061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10341061SN/A 10352292SN/A // Rename the destination registers. 10362292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10372292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10383773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10393773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10404352Sgblack@eecs.umich.edu // Integer registers are flattened. 10416313Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 10427767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10437767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10447767Sgblack@eecs.umich.edu } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { 10457767Sgblack@eecs.umich.edu dest_reg = dest_reg - TheISA::FP_Base_DepTag; 10467767Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 10477767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10487767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10497767Sgblack@eecs.umich.edu flat_dest_reg += TheISA::NumIntRegs; 10507649Sminkyu.jeong@arm.com } else if (dest_reg < TheISA::Max_DepTag) { 10514352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10524352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10537767Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 10547767Sgblack@eecs.umich.edu TheISA::NumIntRegs + TheISA::NumFloatRegs; 10557767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 10567767Sgblack@eecs.umich.edu dest_reg, flat_dest_reg); 10577649Sminkyu.jeong@arm.com } else { 10587649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10593773Sgblack@eecs.umich.edu } 10603773Sgblack@eecs.umich.edu 10613773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10621061SN/A 10632292SN/A // Get the physical register that the destination will be 10642292SN/A // renamed to. 10653773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10661061SN/A 10672292SN/A //Mark Scoreboard entry as not ready 10687854SAli.Saidi@ARM.com if (dest_reg < TheISA::Ctrl_Base_DepTag) 10697854SAli.Saidi@ARM.com scoreboard->unsetReg(rename_result.first); 10701062SN/A 10712292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10723773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10732292SN/A (int)rename_result.first); 10741062SN/A 10752292SN/A // Record the rename information so that a history can be kept. 10763773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10772292SN/A rename_result.first, 10782292SN/A rename_result.second); 10791062SN/A 10802292SN/A historyBuffer[tid].push_front(hb_entry); 10811062SN/A 10822935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10832935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10842935Sksewell@umich.edu historyBuffer[tid].size(), 10852292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10861062SN/A 10872292SN/A // Tell the instruction to rename the appropriate destination 10882292SN/A // register (dest_idx) to the new physical register 10892292SN/A // (rename_result.first), and record the previous physical 10902292SN/A // register that the same logical register was renamed to 10912292SN/A // (rename_result.second). 10922292SN/A inst->renameDestReg(dest_idx, 10932292SN/A rename_result.first, 10942292SN/A rename_result.second); 10951062SN/A 10962292SN/A ++renameRenamedOperands; 10971061SN/A } 10981061SN/A} 10991061SN/A 11001061SN/Atemplate <class Impl> 11011061SN/Ainline int 11026221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11031061SN/A{ 11042292SN/A int num_free = freeEntries[tid].robEntries - 11052292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11062292SN/A 11072292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11082292SN/A 11092292SN/A return num_free; 11101061SN/A} 11111061SN/A 11121061SN/Atemplate <class Impl> 11131061SN/Ainline int 11146221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11151061SN/A{ 11162292SN/A int num_free = freeEntries[tid].iqEntries - 11172292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11182292SN/A 11192292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11202292SN/A 11212292SN/A return num_free; 11222292SN/A} 11232292SN/A 11242292SN/Atemplate <class Impl> 11252292SN/Ainline int 11266221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 11272292SN/A{ 11282292SN/A int num_free = freeEntries[tid].lsqEntries - 11292292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11302292SN/A 11312292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11322292SN/A 11332292SN/A return num_free; 11342292SN/A} 11352292SN/A 11362292SN/Atemplate <class Impl> 11372292SN/Aunsigned 11382292SN/ADefaultRename<Impl>::validInsts() 11392292SN/A{ 11402292SN/A unsigned inst_count = 0; 11412292SN/A 11422292SN/A for (int i=0; i<fromDecode->size; i++) { 11432731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11442292SN/A inst_count++; 11452292SN/A } 11462292SN/A 11472292SN/A return inst_count; 11482292SN/A} 11492292SN/A 11502292SN/Atemplate <class Impl> 11512292SN/Avoid 11526221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11532292SN/A{ 11542292SN/A if (fromIEW->iewBlock[tid]) { 11552292SN/A stalls[tid].iew = true; 11562292SN/A } 11572292SN/A 11582292SN/A if (fromIEW->iewUnblock[tid]) { 11592292SN/A assert(stalls[tid].iew); 11602292SN/A stalls[tid].iew = false; 11612292SN/A } 11622292SN/A 11632292SN/A if (fromCommit->commitBlock[tid]) { 11642292SN/A stalls[tid].commit = true; 11652292SN/A } 11662292SN/A 11672292SN/A if (fromCommit->commitUnblock[tid]) { 11682292SN/A assert(stalls[tid].commit); 11692292SN/A stalls[tid].commit = false; 11702292SN/A } 11712292SN/A} 11722292SN/A 11732292SN/Atemplate <class Impl> 11742292SN/Abool 11756221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11762292SN/A{ 11772292SN/A bool ret_val = false; 11782292SN/A 11792292SN/A if (stalls[tid].iew) { 11802292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11812292SN/A ret_val = true; 11822292SN/A } else if (stalls[tid].commit) { 11832292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11842292SN/A ret_val = true; 11852292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11862292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11872292SN/A ret_val = true; 11882292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11892292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11902292SN/A ret_val = true; 11912292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11922292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11932292SN/A ret_val = true; 11942292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11952292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11962292SN/A ret_val = true; 11972301SN/A } else if (renameStatus[tid] == SerializeStall && 11982292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11992301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12002292SN/A "empty.\n", 12012292SN/A tid); 12022292SN/A ret_val = true; 12032292SN/A } 12042292SN/A 12052292SN/A return ret_val; 12062292SN/A} 12072292SN/A 12082292SN/Atemplate <class Impl> 12092292SN/Avoid 12106221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12112292SN/A{ 12122292SN/A bool updated = false; 12132292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 12142292SN/A freeEntries[tid].iqEntries = 12152292SN/A fromIEW->iewInfo[tid].freeIQEntries; 12162292SN/A updated = true; 12172292SN/A } 12182292SN/A 12192292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 12202292SN/A freeEntries[tid].lsqEntries = 12212292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 12222292SN/A updated = true; 12232292SN/A } 12242292SN/A 12252292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12262292SN/A freeEntries[tid].robEntries = 12272292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12282292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12292292SN/A updated = true; 12302292SN/A } 12312292SN/A 12322292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12332292SN/A tid, 12342292SN/A freeEntries[tid].iqEntries, 12352292SN/A freeEntries[tid].robEntries, 12362292SN/A freeEntries[tid].lsqEntries); 12372292SN/A 12382292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12392292SN/A tid, instsInProgress[tid]); 12402292SN/A} 12412292SN/A 12422292SN/Atemplate <class Impl> 12432292SN/Abool 12446221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12452292SN/A{ 12462292SN/A // Check if there's a squash signal, squash if there is 12472292SN/A // Check stall signals, block if necessary. 12482292SN/A // If status was blocked 12492292SN/A // check if stall conditions have passed 12502292SN/A // if so then go to unblocking 12512292SN/A // If status was Squashing 12522292SN/A // check if squashing is not high. Switch to running this cycle. 12532301SN/A // If status was serialize stall 12542292SN/A // check if ROB is empty and no insts are in flight to the ROB 12552292SN/A 12562292SN/A readFreeEntries(tid); 12572292SN/A readStallSignals(tid); 12582292SN/A 12592292SN/A if (fromCommit->commitInfo[tid].squash) { 12602292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12612292SN/A "commit.\n", tid); 12622292SN/A 12634632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12642292SN/A 12652292SN/A return true; 12662292SN/A } 12672292SN/A 12682292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12692292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12702292SN/A 12712292SN/A renameStatus[tid] = Squashing; 12722292SN/A 12732292SN/A return true; 12742292SN/A } 12752292SN/A 12762292SN/A if (checkStall(tid)) { 12772292SN/A return block(tid); 12782292SN/A } 12792292SN/A 12802292SN/A if (renameStatus[tid] == Blocked) { 12812292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12822292SN/A tid); 12832292SN/A 12842292SN/A renameStatus[tid] = Unblocking; 12852292SN/A 12862292SN/A unblock(tid); 12872292SN/A 12882292SN/A return true; 12892292SN/A } 12902292SN/A 12912292SN/A if (renameStatus[tid] == Squashing) { 12922292SN/A // Switch status to running if rename isn't being told to block or 12932292SN/A // squash this cycle. 12943798Sgblack@eecs.umich.edu if (resumeSerialize) { 12953798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12963798Sgblack@eecs.umich.edu tid); 12972292SN/A 12983798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12993798Sgblack@eecs.umich.edu return true; 13003798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13013798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13023798Sgblack@eecs.umich.edu tid); 13033798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13043798Sgblack@eecs.umich.edu return true; 13053798Sgblack@eecs.umich.edu } else { 13063788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13073788Sgblack@eecs.umich.edu tid); 13082292SN/A 13093788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13103788Sgblack@eecs.umich.edu return false; 13113788Sgblack@eecs.umich.edu } 13122292SN/A } 13132292SN/A 13142301SN/A if (renameStatus[tid] == SerializeStall) { 13152292SN/A // Stall ends once the ROB is free. 13162301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13172292SN/A "unblocking.\n", tid); 13182292SN/A 13192301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13202292SN/A 13212292SN/A renameStatus[tid] = Unblocking; 13222292SN/A 13232292SN/A unblock(tid); 13242292SN/A 13252292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13267720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13272292SN/A 13282292SN/A // Put instruction into queue here. 13292301SN/A serial_inst->clearSerializeBefore(); 13302292SN/A 13312292SN/A if (!skidBuffer[tid].empty()) { 13322301SN/A skidBuffer[tid].push_front(serial_inst); 13332292SN/A } else { 13342301SN/A insts[tid].push_front(serial_inst); 13352292SN/A } 13362292SN/A 13372292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13382703Sktlim@umich.edu " Adding to front of list.\n", tid); 13392292SN/A 13402301SN/A serializeInst[tid] = NULL; 13412292SN/A 13422292SN/A return true; 13432292SN/A } 13442292SN/A 13452292SN/A // If we've reached this point, we have not gotten any signals that 13462292SN/A // cause rename to change its status. Rename remains the same as before. 13472292SN/A return false; 13481061SN/A} 13491061SN/A 13501060SN/Atemplate<class Impl> 13511060SN/Avoid 13526221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13531060SN/A{ 13542292SN/A if (inst_list.empty()) { 13552292SN/A // Mark a bit to say that I must serialize on the next instruction. 13562292SN/A serializeOnNextInst[tid] = true; 13571060SN/A return; 13581060SN/A } 13591060SN/A 13602292SN/A // Set the next instruction as serializing. 13612292SN/A inst_list.front()->setSerializeBefore(); 13622292SN/A} 13632292SN/A 13642292SN/Atemplate <class Impl> 13652292SN/Ainline void 13662292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13672292SN/A{ 13682292SN/A switch (source) { 13692292SN/A case ROB: 13702292SN/A ++renameROBFullEvents; 13712292SN/A break; 13722292SN/A case IQ: 13732292SN/A ++renameIQFullEvents; 13742292SN/A break; 13752292SN/A case LSQ: 13762292SN/A ++renameLSQFullEvents; 13772292SN/A break; 13782292SN/A default: 13792292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13802292SN/A break; 13811060SN/A } 13822292SN/A} 13831060SN/A 13842292SN/Atemplate <class Impl> 13852292SN/Avoid 13862292SN/ADefaultRename<Impl>::dumpHistory() 13872292SN/A{ 13882980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13891060SN/A 13906221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13911060SN/A 13926221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13931060SN/A 13946221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13952292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13962292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13972292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13981060SN/A 13992292SN/A buf_it++; 14001062SN/A } 14011060SN/A } 14021060SN/A} 1403