rename_impl.hh revision 7649
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292935Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321060SN/A#include <list> 331060SN/A 343773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 356329Sgblack@eecs.umich.edu#include "arch/registers.hh" 361858SN/A#include "config/full_system.hh" 376658Snate@binkert.org#include "config/the_isa.hh" 381717SN/A#include "cpu/o3/rename.hh" 395529Snate@binkert.org#include "params/DerivO3CPU.hh" 401060SN/A 416221Snate@binkert.orgusing namespace std; 426221Snate@binkert.org 431061SN/Atemplate <class Impl> 445529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 454329Sktlim@umich.edu : cpu(_cpu), 464329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 472292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 482292SN/A commitToRenameDelay(params->commitToRenameDelay), 492292SN/A renameWidth(params->renameWidth), 502292SN/A commitWidth(params->commitWidth), 513788Sgblack@eecs.umich.edu resumeSerialize(false), 523798Sgblack@eecs.umich.edu resumeUnblocking(false), 535529Snate@binkert.org numThreads(params->numThreads), 542361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 551060SN/A{ 562292SN/A _status = Inactive; 572292SN/A 586221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 596221Snate@binkert.org renameStatus[tid] = Idle; 602292SN/A 616221Snate@binkert.org freeEntries[tid].iqEntries = 0; 626221Snate@binkert.org freeEntries[tid].lsqEntries = 0; 636221Snate@binkert.org freeEntries[tid].robEntries = 0; 642292SN/A 656221Snate@binkert.org stalls[tid].iew = false; 666221Snate@binkert.org stalls[tid].commit = false; 676221Snate@binkert.org serializeInst[tid] = NULL; 682292SN/A 696221Snate@binkert.org instsInProgress[tid] = 0; 702292SN/A 716221Snate@binkert.org emptyROB[tid] = true; 722292SN/A 736221Snate@binkert.org serializeOnNextInst[tid] = false; 742292SN/A } 752292SN/A 762292SN/A // @todo: Make into a parameter. 772292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 782292SN/A} 792292SN/A 802292SN/Atemplate <class Impl> 812292SN/Astd::string 822292SN/ADefaultRename<Impl>::name() const 832292SN/A{ 842292SN/A return cpu->name() + ".rename"; 851060SN/A} 861060SN/A 871061SN/Atemplate <class Impl> 881060SN/Avoid 892292SN/ADefaultRename<Impl>::regStats() 901062SN/A{ 911062SN/A renameSquashCycles 922301SN/A .name(name() + ".RENAME:SquashCycles") 931062SN/A .desc("Number of cycles rename is squashing") 941062SN/A .prereq(renameSquashCycles); 951062SN/A renameIdleCycles 962301SN/A .name(name() + ".RENAME:IdleCycles") 971062SN/A .desc("Number of cycles rename is idle") 981062SN/A .prereq(renameIdleCycles); 991062SN/A renameBlockCycles 1002301SN/A .name(name() + ".RENAME:BlockCycles") 1011062SN/A .desc("Number of cycles rename is blocking") 1021062SN/A .prereq(renameBlockCycles); 1032301SN/A renameSerializeStallCycles 1042301SN/A .name(name() + ".RENAME:serializeStallCycles") 1052301SN/A .desc("count of cycles rename stalled for serializing inst") 1062301SN/A .flags(Stats::total); 1072292SN/A renameRunCycles 1082301SN/A .name(name() + ".RENAME:RunCycles") 1092292SN/A .desc("Number of cycles rename is running") 1102292SN/A .prereq(renameIdleCycles); 1111062SN/A renameUnblockCycles 1122301SN/A .name(name() + ".RENAME:UnblockCycles") 1131062SN/A .desc("Number of cycles rename is unblocking") 1141062SN/A .prereq(renameUnblockCycles); 1151062SN/A renameRenamedInsts 1162301SN/A .name(name() + ".RENAME:RenamedInsts") 1171062SN/A .desc("Number of instructions processed by rename") 1181062SN/A .prereq(renameRenamedInsts); 1191062SN/A renameSquashedInsts 1202301SN/A .name(name() + ".RENAME:SquashedInsts") 1211062SN/A .desc("Number of squashed instructions processed by rename") 1221062SN/A .prereq(renameSquashedInsts); 1231062SN/A renameROBFullEvents 1242301SN/A .name(name() + ".RENAME:ROBFullEvents") 1252292SN/A .desc("Number of times rename has blocked due to ROB full") 1261062SN/A .prereq(renameROBFullEvents); 1271062SN/A renameIQFullEvents 1282301SN/A .name(name() + ".RENAME:IQFullEvents") 1292292SN/A .desc("Number of times rename has blocked due to IQ full") 1301062SN/A .prereq(renameIQFullEvents); 1312292SN/A renameLSQFullEvents 1322301SN/A .name(name() + ".RENAME:LSQFullEvents") 1332292SN/A .desc("Number of times rename has blocked due to LSQ full") 1342292SN/A .prereq(renameLSQFullEvents); 1351062SN/A renameFullRegistersEvents 1362301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1371062SN/A .desc("Number of times there has been no free registers") 1381062SN/A .prereq(renameFullRegistersEvents); 1391062SN/A renameRenamedOperands 1402301SN/A .name(name() + ".RENAME:RenamedOperands") 1411062SN/A .desc("Number of destination operands rename has renamed") 1421062SN/A .prereq(renameRenamedOperands); 1431062SN/A renameRenameLookups 1442301SN/A .name(name() + ".RENAME:RenameLookups") 1451062SN/A .desc("Number of register rename lookups that rename has made") 1461062SN/A .prereq(renameRenameLookups); 1471062SN/A renameCommittedMaps 1482301SN/A .name(name() + ".RENAME:CommittedMaps") 1491062SN/A .desc("Number of HB maps that are committed") 1501062SN/A .prereq(renameCommittedMaps); 1511062SN/A renameUndoneMaps 1522301SN/A .name(name() + ".RENAME:UndoneMaps") 1531062SN/A .desc("Number of HB maps that are undone due to squashing") 1541062SN/A .prereq(renameUndoneMaps); 1552301SN/A renamedSerializing 1562301SN/A .name(name() + ".RENAME:serializingInsts") 1572301SN/A .desc("count of serializing insts renamed") 1582301SN/A .flags(Stats::total) 1592301SN/A ; 1602301SN/A renamedTempSerializing 1612301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1622301SN/A .desc("count of temporary serializing insts renamed") 1632301SN/A .flags(Stats::total) 1642301SN/A ; 1652307SN/A renameSkidInsts 1662307SN/A .name(name() + ".RENAME:skidInsts") 1672307SN/A .desc("count of insts added to the skid buffer") 1682307SN/A .flags(Stats::total) 1692307SN/A ; 1701062SN/A} 1711062SN/A 1721062SN/Atemplate <class Impl> 1731062SN/Avoid 1742292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1751060SN/A{ 1761060SN/A timeBuffer = tb_ptr; 1771060SN/A 1781060SN/A // Setup wire to read information from time buffer, from IEW stage. 1791060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1801060SN/A 1811060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1821060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1831060SN/A 1841060SN/A // Setup wire to write information to previous stages. 1851060SN/A toDecode = timeBuffer->getWire(0); 1861060SN/A} 1871060SN/A 1881061SN/Atemplate <class Impl> 1891060SN/Avoid 1902292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1911060SN/A{ 1921060SN/A renameQueue = rq_ptr; 1931060SN/A 1941060SN/A // Setup wire to write information to future stages. 1951060SN/A toIEW = renameQueue->getWire(0); 1961060SN/A} 1971060SN/A 1981061SN/Atemplate <class Impl> 1991060SN/Avoid 2002292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2011060SN/A{ 2021060SN/A decodeQueue = dq_ptr; 2031060SN/A 2041060SN/A // Setup wire to get information from decode. 2051060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2061060SN/A} 2071060SN/A 2081061SN/Atemplate <class Impl> 2091060SN/Avoid 2102292SN/ADefaultRename<Impl>::initStage() 2111060SN/A{ 2122329SN/A // Grab the number of free entries directly from the stages. 2136221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2142292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2152292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2162292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2172292SN/A emptyROB[tid] = true; 2182292SN/A } 2191060SN/A} 2201060SN/A 2212292SN/Atemplate<class Impl> 2222292SN/Avoid 2236221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2242292SN/A{ 2252292SN/A activeThreads = at_ptr; 2262292SN/A} 2272292SN/A 2282292SN/A 2291061SN/Atemplate <class Impl> 2301060SN/Avoid 2312292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2321060SN/A{ 2336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2346221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2351060SN/A} 2361060SN/A 2371061SN/Atemplate <class Impl> 2381060SN/Avoid 2392292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2401060SN/A{ 2412292SN/A freeList = fl_ptr; 2422292SN/A} 2431060SN/A 2442292SN/Atemplate<class Impl> 2452292SN/Avoid 2462292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2472292SN/A{ 2482292SN/A scoreboard = _scoreboard; 2491060SN/A} 2501060SN/A 2511061SN/Atemplate <class Impl> 2522863Sktlim@umich.edubool 2532843Sktlim@umich.eduDefaultRename<Impl>::drain() 2541060SN/A{ 2552348SN/A // Rename is ready to switch out at any time. 2562843Sktlim@umich.edu cpu->signalDrained(); 2572863Sktlim@umich.edu return true; 2582316SN/A} 2591060SN/A 2602316SN/Atemplate <class Impl> 2612316SN/Avoid 2622843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2632316SN/A{ 2642348SN/A // Clear any state, fix up the rename map. 2656221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2662980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2676221Snate@binkert.org historyBuffer[tid].begin(); 2682307SN/A 2696221Snate@binkert.org while (!historyBuffer[tid].empty()) { 2706221Snate@binkert.org assert(hb_it != historyBuffer[tid].end()); 2712307SN/A 2722307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2736221Snate@binkert.org "number %i.\n", tid, (*hb_it).instSeqNum); 2742307SN/A 2752307SN/A // Tell the rename map to set the architected register to the 2762307SN/A // previous physical register that it was renamed to. 2776221Snate@binkert.org renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2782307SN/A 2792307SN/A // Put the renamed physical register back on the free list. 2802307SN/A freeList->addReg(hb_it->newPhysReg); 2812307SN/A 2822361SN/A // Be sure to mark its register as ready if it's a misc register. 2832361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2842361SN/A scoreboard->setReg(hb_it->newPhysReg); 2852361SN/A } 2862361SN/A 2876221Snate@binkert.org historyBuffer[tid].erase(hb_it++); 2882307SN/A } 2896221Snate@binkert.org insts[tid].clear(); 2906221Snate@binkert.org skidBuffer[tid].clear(); 2911060SN/A } 2921060SN/A} 2931060SN/A 2941061SN/Atemplate <class Impl> 2951060SN/Avoid 2962307SN/ADefaultRename<Impl>::takeOverFrom() 2971060SN/A{ 2982307SN/A _status = Inactive; 2992307SN/A initStage(); 3001060SN/A 3012329SN/A // Reset all state prior to taking over from the other CPU. 3026221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3036221Snate@binkert.org renameStatus[tid] = Idle; 3041060SN/A 3056221Snate@binkert.org stalls[tid].iew = false; 3066221Snate@binkert.org stalls[tid].commit = false; 3076221Snate@binkert.org serializeInst[tid] = NULL; 3082307SN/A 3096221Snate@binkert.org instsInProgress[tid] = 0; 3102307SN/A 3116221Snate@binkert.org emptyROB[tid] = true; 3122307SN/A 3136221Snate@binkert.org serializeOnNextInst[tid] = false; 3142307SN/A } 3152307SN/A} 3162307SN/A 3172307SN/Atemplate <class Impl> 3182307SN/Avoid 3196221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3201858SN/A{ 3212292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3221858SN/A 3232292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3242292SN/A // If it still needs to block, the blocking should happen the next 3252292SN/A // cycle and there should be space to hold everything due to the squash. 3262292SN/A if (renameStatus[tid] == Blocked || 3273788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3282292SN/A toDecode->renameUnblock[tid] = 1; 3292698Sktlim@umich.edu 3303788Sgblack@eecs.umich.edu resumeSerialize = false; 3312301SN/A serializeInst[tid] = NULL; 3323788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3333788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3343788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3353788Sgblack@eecs.umich.edu resumeSerialize = true; 3363788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3373788Sgblack@eecs.umich.edu } else { 3383788Sgblack@eecs.umich.edu resumeSerialize = false; 3393788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3403788Sgblack@eecs.umich.edu 3413788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3423788Sgblack@eecs.umich.edu } 3432292SN/A } 3442292SN/A 3452292SN/A // Set the status to Squashing. 3462292SN/A renameStatus[tid] = Squashing; 3472292SN/A 3482329SN/A // Squash any instructions from decode. 3492292SN/A unsigned squashCount = 0; 3502292SN/A 3512292SN/A for (int i=0; i<fromDecode->size; i++) { 3522935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3532935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3542731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3552292SN/A wroteToTimeBuffer = true; 3562292SN/A squashCount++; 3572292SN/A } 3582935Sksewell@umich.edu 3592292SN/A } 3602292SN/A 3612935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3624632Sgblack@eecs.umich.edu // insts in them. 3633093Sksewell@umich.edu insts[tid].clear(); 3642292SN/A 3652292SN/A // Clear the skid buffer in case it has any data in it. 3663093Sksewell@umich.edu skidBuffer[tid].clear(); 3674632Sgblack@eecs.umich.edu 3682935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3692292SN/A} 3702292SN/A 3712292SN/Atemplate <class Impl> 3722292SN/Avoid 3732292SN/ADefaultRename<Impl>::tick() 3742292SN/A{ 3752292SN/A wroteToTimeBuffer = false; 3762292SN/A 3772292SN/A blockThisCycle = false; 3782292SN/A 3792292SN/A bool status_change = false; 3802292SN/A 3812292SN/A toIEWIndex = 0; 3822292SN/A 3832292SN/A sortInsts(); 3842292SN/A 3856221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3866221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3872292SN/A 3882292SN/A // Check stall and squash signals. 3893867Sbinkertn@umich.edu while (threads != end) { 3906221Snate@binkert.org ThreadID tid = *threads++; 3912292SN/A 3922292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3932292SN/A 3942292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3952292SN/A 3962292SN/A rename(status_change, tid); 3972292SN/A } 3982292SN/A 3992292SN/A if (status_change) { 4002292SN/A updateStatus(); 4012292SN/A } 4022292SN/A 4032292SN/A if (wroteToTimeBuffer) { 4042292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4052292SN/A cpu->activityThisCycle(); 4062292SN/A } 4072292SN/A 4083867Sbinkertn@umich.edu threads = activeThreads->begin(); 4092292SN/A 4103867Sbinkertn@umich.edu while (threads != end) { 4116221Snate@binkert.org ThreadID tid = *threads++; 4122292SN/A 4132292SN/A // If we committed this cycle then doneSeqNum will be > 0 4142292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4152292SN/A !fromCommit->commitInfo[tid].squash && 4162292SN/A renameStatus[tid] != Squashing) { 4172292SN/A 4182292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4192292SN/A tid); 4202292SN/A } 4212292SN/A } 4222292SN/A 4232292SN/A // @todo: make into updateProgress function 4246221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4252292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4262292SN/A 4272292SN/A assert(instsInProgress[tid] >=0); 4282292SN/A } 4292292SN/A 4302292SN/A} 4312292SN/A 4322292SN/Atemplate<class Impl> 4332292SN/Avoid 4346221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4352292SN/A{ 4362292SN/A // If status is Running or idle, 4372292SN/A // call renameInsts() 4382292SN/A // If status is Unblocking, 4392292SN/A // buffer any instructions coming from decode 4402292SN/A // continue trying to empty skid buffer 4412292SN/A // check if stall conditions have passed 4422292SN/A 4432292SN/A if (renameStatus[tid] == Blocked) { 4442292SN/A ++renameBlockCycles; 4452292SN/A } else if (renameStatus[tid] == Squashing) { 4462292SN/A ++renameSquashCycles; 4472301SN/A } else if (renameStatus[tid] == SerializeStall) { 4482301SN/A ++renameSerializeStallCycles; 4493788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4503788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4513788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4523788Sgblack@eecs.umich.edu if (resumeSerialize) { 4533788Sgblack@eecs.umich.edu resumeSerialize = false; 4543788Sgblack@eecs.umich.edu block(tid); 4553788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4563788Sgblack@eecs.umich.edu } 4573798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4583798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4593798Sgblack@eecs.umich.edu block(tid); 4603798Sgblack@eecs.umich.edu resumeUnblocking = false; 4613798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4623798Sgblack@eecs.umich.edu } 4632292SN/A } 4642292SN/A 4652292SN/A if (renameStatus[tid] == Running || 4662292SN/A renameStatus[tid] == Idle) { 4672292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4682292SN/A "stage.\n", tid); 4692292SN/A 4702292SN/A renameInsts(tid); 4712292SN/A } else if (renameStatus[tid] == Unblocking) { 4722292SN/A renameInsts(tid); 4732292SN/A 4742292SN/A if (validInsts()) { 4752292SN/A // Add the current inputs to the skid buffer so they can be 4762292SN/A // reprocessed when this stage unblocks. 4772292SN/A skidInsert(tid); 4782292SN/A } 4792292SN/A 4802292SN/A // If we switched over to blocking, then there's a potential for 4812292SN/A // an overall status change. 4822292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4831858SN/A } 4841858SN/A} 4851858SN/A 4861858SN/Atemplate <class Impl> 4871858SN/Avoid 4886221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 4891858SN/A{ 4902292SN/A // Instructions can be either in the skid buffer or the queue of 4912292SN/A // instructions coming from decode, depending on the status. 4922292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4932292SN/A skidBuffer[tid].size() : insts[tid].size(); 4941858SN/A 4952292SN/A // Check the decode queue to see if instructions are available. 4962292SN/A // If there are no available instructions to rename, then do nothing. 4972292SN/A if (insts_available == 0) { 4982292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4992292SN/A tid); 5002292SN/A // Should I change status to idle? 5012292SN/A ++renameIdleCycles; 5022292SN/A return; 5032292SN/A } else if (renameStatus[tid] == Unblocking) { 5042292SN/A ++renameUnblockCycles; 5052292SN/A } else if (renameStatus[tid] == Running) { 5062292SN/A ++renameRunCycles; 5072292SN/A } 5081858SN/A 5092292SN/A DynInstPtr inst; 5102292SN/A 5112292SN/A // Will have to do a different calculation for the number of free 5122292SN/A // entries. 5132292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5142292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5152292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5162292SN/A int min_free_entries = free_rob_entries; 5172292SN/A 5182292SN/A FullSource source = ROB; 5192292SN/A 5202292SN/A if (free_iq_entries < min_free_entries) { 5212292SN/A min_free_entries = free_iq_entries; 5222292SN/A source = IQ; 5232292SN/A } 5242292SN/A 5252292SN/A if (free_lsq_entries < min_free_entries) { 5262292SN/A min_free_entries = free_lsq_entries; 5272292SN/A source = LSQ; 5282292SN/A } 5292292SN/A 5302292SN/A // Check if there's any space left. 5312292SN/A if (min_free_entries <= 0) { 5322292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5332292SN/A "entries.\n" 5342292SN/A "ROB has %i free entries.\n" 5352292SN/A "IQ has %i free entries.\n" 5362292SN/A "LSQ has %i free entries.\n", 5372292SN/A tid, 5382292SN/A free_rob_entries, 5392292SN/A free_iq_entries, 5402292SN/A free_lsq_entries); 5412292SN/A 5422292SN/A blockThisCycle = true; 5432292SN/A 5442292SN/A block(tid); 5452292SN/A 5462292SN/A incrFullStat(source); 5472292SN/A 5482292SN/A return; 5492292SN/A } else if (min_free_entries < insts_available) { 5502292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5512292SN/A "%i insts available, but only %i insts can be " 5522292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5532292SN/A tid, insts_available, min_free_entries); 5542292SN/A 5552292SN/A insts_available = min_free_entries; 5562292SN/A 5572292SN/A blockThisCycle = true; 5582292SN/A 5592292SN/A incrFullStat(source); 5602292SN/A } 5612292SN/A 5622292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5632292SN/A skidBuffer[tid] : insts[tid]; 5642292SN/A 5652292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5662292SN/A "send iew.\n", tid, insts_available); 5672292SN/A 5682292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5692292SN/A "dispatched to IQ last cycle.\n", 5702292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5712292SN/A 5722292SN/A // Handle serializing the next instruction if necessary. 5732292SN/A if (serializeOnNextInst[tid]) { 5742292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5752292SN/A // ROB already empty; no need to serialize. 5762292SN/A serializeOnNextInst[tid] = false; 5772292SN/A } else if (!insts_to_rename.empty()) { 5782292SN/A insts_to_rename.front()->setSerializeBefore(); 5792292SN/A } 5802292SN/A } 5812292SN/A 5822292SN/A int renamed_insts = 0; 5832292SN/A 5842292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5852292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5862292SN/A 5872292SN/A assert(!insts_to_rename.empty()); 5882292SN/A 5892292SN/A inst = insts_to_rename.front(); 5902292SN/A 5912292SN/A insts_to_rename.pop_front(); 5922292SN/A 5932292SN/A if (renameStatus[tid] == Unblocking) { 5942292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 5952292SN/A "skidBuffer\n", 5962292SN/A tid, inst->seqNum, inst->readPC()); 5972292SN/A } 5982292SN/A 5992292SN/A if (inst->isSquashed()) { 6002292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 6012292SN/A "squashed, skipping.\n", 6022935Sksewell@umich.edu tid, inst->seqNum, inst->readPC()); 6032292SN/A 6042292SN/A ++renameSquashedInsts; 6052292SN/A 6062292SN/A // Decrement how many instructions are available. 6072292SN/A --insts_available; 6082292SN/A 6092292SN/A continue; 6102292SN/A } 6112292SN/A 6122292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6132292SN/A "PC %#x.\n", 6142292SN/A tid, inst->seqNum, inst->readPC()); 6152292SN/A 6162292SN/A // Handle serializeAfter/serializeBefore instructions. 6172292SN/A // serializeAfter marks the next instruction as serializeBefore. 6182292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6192292SN/A // is empty. 6202336SN/A 6212336SN/A // In this model, IPR accesses are serialize before 6222336SN/A // instructions, and store conditionals are serialize after 6232336SN/A // instructions. This is mainly due to lack of support for 6242336SN/A // out-of-order operations of either of those classes of 6252336SN/A // instructions. 6262336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6272336SN/A !inst->isSerializeHandled()) { 6282292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6292292SN/A 6302301SN/A if (!inst->isTempSerializeBefore()) { 6312301SN/A renamedSerializing++; 6322292SN/A inst->setSerializeHandled(); 6332301SN/A } else { 6342301SN/A renamedTempSerializing++; 6352301SN/A } 6362292SN/A 6372301SN/A // Change status over to SerializeStall so that other stages know 6382292SN/A // what this is blocked on. 6392301SN/A renameStatus[tid] = SerializeStall; 6402292SN/A 6412301SN/A serializeInst[tid] = inst; 6422292SN/A 6432292SN/A blockThisCycle = true; 6442292SN/A 6452292SN/A break; 6462336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6472336SN/A !inst->isSerializeHandled()) { 6482292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6492292SN/A 6502307SN/A renamedSerializing++; 6512307SN/A 6522292SN/A inst->setSerializeHandled(); 6532292SN/A 6542292SN/A serializeAfter(insts_to_rename, tid); 6552292SN/A } 6562292SN/A 6572292SN/A // Check here to make sure there are enough destination registers 6582292SN/A // to rename to. Otherwise block. 6592292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6602292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6612292SN/A "physical registers to rename to.\n"); 6622292SN/A blockThisCycle = true; 6634345Sktlim@umich.edu insts_to_rename.push_front(inst); 6642292SN/A ++renameFullRegistersEvents; 6652292SN/A 6662292SN/A break; 6672292SN/A } 6682292SN/A 6692292SN/A renameSrcRegs(inst, inst->threadNumber); 6702292SN/A 6712292SN/A renameDestRegs(inst, inst->threadNumber); 6722292SN/A 6732292SN/A ++renamed_insts; 6742292SN/A 6752292SN/A // Put instruction in rename queue. 6762292SN/A toIEW->insts[toIEWIndex] = inst; 6772292SN/A ++(toIEW->size); 6782292SN/A 6792292SN/A // Increment which instruction we're on. 6802292SN/A ++toIEWIndex; 6812292SN/A 6822292SN/A // Decrement how many instructions are available. 6832292SN/A --insts_available; 6842292SN/A } 6852292SN/A 6862292SN/A instsInProgress[tid] += renamed_insts; 6872307SN/A renameRenamedInsts += renamed_insts; 6882292SN/A 6892292SN/A // If we wrote to the time buffer, record this. 6902292SN/A if (toIEWIndex) { 6912292SN/A wroteToTimeBuffer = true; 6922292SN/A } 6932292SN/A 6942292SN/A // Check if there's any instructions left that haven't yet been renamed. 6952292SN/A // If so then block. 6962292SN/A if (insts_available) { 6972292SN/A blockThisCycle = true; 6982292SN/A } 6992292SN/A 7002292SN/A if (blockThisCycle) { 7012292SN/A block(tid); 7022292SN/A toDecode->renameUnblock[tid] = false; 7032292SN/A } 7042292SN/A} 7052292SN/A 7062292SN/Atemplate<class Impl> 7072292SN/Avoid 7086221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7092292SN/A{ 7102292SN/A DynInstPtr inst = NULL; 7112292SN/A 7122292SN/A while (!insts[tid].empty()) { 7132292SN/A inst = insts[tid].front(); 7142292SN/A 7152292SN/A insts[tid].pop_front(); 7162292SN/A 7172292SN/A assert(tid == inst->threadNumber); 7182292SN/A 7192292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 7202292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 7212292SN/A 7222307SN/A ++renameSkidInsts; 7232307SN/A 7242292SN/A skidBuffer[tid].push_back(inst); 7252292SN/A } 7262292SN/A 7272292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7283798Sgblack@eecs.umich.edu { 7293798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7303798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7313798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7323798Sgblack@eecs.umich.edu { 7333798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7343798Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->readPC()), 7353798Sgblack@eecs.umich.edu (*it)->seqNum); 7363798Sgblack@eecs.umich.edu } 7372292SN/A panic("Skidbuffer Exceeded Max Size"); 7383798Sgblack@eecs.umich.edu } 7392292SN/A} 7402292SN/A 7412292SN/Atemplate <class Impl> 7422292SN/Avoid 7432292SN/ADefaultRename<Impl>::sortInsts() 7442292SN/A{ 7452292SN/A int insts_from_decode = fromDecode->size; 7462329SN/A#ifdef DEBUG 7476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 7486221Snate@binkert.org assert(insts[tid].empty()); 7492329SN/A#endif 7502292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7512292SN/A DynInstPtr inst = fromDecode->insts[i]; 7522292SN/A insts[inst->threadNumber].push_back(inst); 7532292SN/A } 7542292SN/A} 7552292SN/A 7562292SN/Atemplate<class Impl> 7572292SN/Abool 7582292SN/ADefaultRename<Impl>::skidsEmpty() 7592292SN/A{ 7606221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7616221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7622292SN/A 7633867Sbinkertn@umich.edu while (threads != end) { 7646221Snate@binkert.org ThreadID tid = *threads++; 7653867Sbinkertn@umich.edu 7663867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7672292SN/A return false; 7682292SN/A } 7692292SN/A 7702292SN/A return true; 7712292SN/A} 7722292SN/A 7732292SN/Atemplate<class Impl> 7742292SN/Avoid 7752292SN/ADefaultRename<Impl>::updateStatus() 7762292SN/A{ 7772292SN/A bool any_unblocking = false; 7782292SN/A 7796221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7806221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7812292SN/A 7823867Sbinkertn@umich.edu while (threads != end) { 7836221Snate@binkert.org ThreadID tid = *threads++; 7842292SN/A 7852292SN/A if (renameStatus[tid] == Unblocking) { 7862292SN/A any_unblocking = true; 7872292SN/A break; 7882292SN/A } 7892292SN/A } 7902292SN/A 7912292SN/A // Rename will have activity if it's unblocking. 7922292SN/A if (any_unblocking) { 7932292SN/A if (_status == Inactive) { 7942292SN/A _status = Active; 7952292SN/A 7962292SN/A DPRINTF(Activity, "Activating stage.\n"); 7972292SN/A 7982733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7992292SN/A } 8002292SN/A } else { 8012292SN/A // If it's not unblocking, then rename will not have any internal 8022292SN/A // activity. Switch it to inactive. 8032292SN/A if (_status == Active) { 8042292SN/A _status = Inactive; 8052292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8062292SN/A 8072733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8082292SN/A } 8092292SN/A } 8102292SN/A} 8112292SN/A 8122292SN/Atemplate <class Impl> 8132292SN/Abool 8146221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8152292SN/A{ 8162292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8172292SN/A 8182292SN/A // Add the current inputs onto the skid buffer, so they can be 8192292SN/A // reprocessed when this stage unblocks. 8202292SN/A skidInsert(tid); 8212292SN/A 8222292SN/A // Only signal backwards to block if the previous stages do not think 8232292SN/A // rename is already blocked. 8242292SN/A if (renameStatus[tid] != Blocked) { 8253798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8263798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8273798Sgblack@eecs.umich.edu // stages to block. 8283798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8292292SN/A toDecode->renameBlock[tid] = true; 8302292SN/A toDecode->renameUnblock[tid] = false; 8312292SN/A wroteToTimeBuffer = true; 8322292SN/A } 8332292SN/A 8342329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8352329SN/A // it would not know to complete the serialize stall. 8362301SN/A if (renameStatus[tid] != SerializeStall) { 8372292SN/A // Set status to Blocked. 8382292SN/A renameStatus[tid] = Blocked; 8392292SN/A return true; 8402292SN/A } 8412292SN/A } 8422292SN/A 8432292SN/A return false; 8442292SN/A} 8452292SN/A 8462292SN/Atemplate <class Impl> 8472292SN/Abool 8486221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8492292SN/A{ 8502292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8512292SN/A 8522292SN/A // Rename is done unblocking if the skid buffer is empty. 8532301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8542292SN/A 8552292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8562292SN/A 8572292SN/A toDecode->renameUnblock[tid] = true; 8582292SN/A wroteToTimeBuffer = true; 8592292SN/A 8602292SN/A renameStatus[tid] = Running; 8612292SN/A return true; 8622292SN/A } 8632292SN/A 8642292SN/A return false; 8652292SN/A} 8662292SN/A 8672292SN/Atemplate <class Impl> 8682292SN/Avoid 8696221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8702292SN/A{ 8712980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8722980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8732292SN/A 8741060SN/A // After a syscall squashes everything, the history buffer may be empty 8751060SN/A // but the ROB may still be squashing instructions. 8762292SN/A if (historyBuffer[tid].empty()) { 8771060SN/A return; 8781060SN/A } 8791060SN/A 8801060SN/A // Go through the most recent instructions, undoing the mappings 8811060SN/A // they did and freeing up the registers. 8822292SN/A while (!historyBuffer[tid].empty() && 8832292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8842292SN/A assert(hb_it != historyBuffer[tid].end()); 8851062SN/A 8862292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8872292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8881060SN/A 8892292SN/A // Tell the rename map to set the architected register to the 8902292SN/A // previous physical register that it was renamed to. 8912292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8921060SN/A 8932292SN/A // Put the renamed physical register back on the free list. 8942292SN/A freeList->addReg(hb_it->newPhysReg); 8951062SN/A 8962367SN/A // Be sure to mark its register as ready if it's a misc register. 8972367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 8982367SN/A scoreboard->setReg(hb_it->newPhysReg); 8992367SN/A } 9002367SN/A 9012292SN/A historyBuffer[tid].erase(hb_it++); 9021061SN/A 9031062SN/A ++renameUndoneMaps; 9041060SN/A } 9051060SN/A} 9061060SN/A 9071060SN/Atemplate<class Impl> 9081060SN/Avoid 9096221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9101060SN/A{ 9112292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9122292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9132292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9142292SN/A 9152980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9162980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9171060SN/A 9181061SN/A --hb_it; 9191060SN/A 9202292SN/A if (historyBuffer[tid].empty()) { 9212292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9222292SN/A return; 9232292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9242292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9252292SN/A "that a syscall happened recently.\n", tid); 9261060SN/A return; 9271060SN/A } 9281060SN/A 9292292SN/A // Commit all the renames up until (and including) the committed sequence 9302292SN/A // number. Some or even all of the committed instructions may not have 9312292SN/A // rename histories if they did not have destination registers that were 9322292SN/A // renamed. 9332292SN/A while (!historyBuffer[tid].empty() && 9342292SN/A hb_it != historyBuffer[tid].end() && 9352292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9361060SN/A 9372329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9382329SN/A "[sn:%lli].\n", 9392292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9401061SN/A 9412292SN/A freeList->addReg((*hb_it).prevPhysReg); 9422292SN/A ++renameCommittedMaps; 9431061SN/A 9442292SN/A historyBuffer[tid].erase(hb_it--); 9451060SN/A } 9461060SN/A} 9471060SN/A 9481061SN/Atemplate <class Impl> 9491061SN/Ainline void 9506221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9511061SN/A{ 9522292SN/A assert(renameMap[tid] != 0); 9532292SN/A 9541061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9551061SN/A 9561061SN/A // Get the architectual register numbers from the source and 9571061SN/A // destination operands, and redirect them to the right register. 9581061SN/A // Will need to mark dependencies though. 9592292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9601061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9613773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9623773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9636313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 9643773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 9655082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9665082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9676313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 9685082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9697649Sminkyu.jeong@arm.com } else if (src_reg < TheISA::Max_DepTag) { 9704352Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 9714636Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); 9727649Sminkyu.jeong@arm.com } else { 9737649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9743773Sgblack@eecs.umich.edu } 9754352Sgblack@eecs.umich.edu 9763773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 9771061SN/A 9781061SN/A // Look up the source registers to get the phys. register they've 9791061SN/A // been renamed to, and set the sources to those registers. 9803773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 9811061SN/A 9822292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9833773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 9842292SN/A (int)renamed_reg); 9851061SN/A 9861061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9871061SN/A 9882292SN/A // See if the register is ready or not. 9892292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9904636Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg); 9911061SN/A 9921061SN/A inst->markSrcRegReady(src_idx); 9934636Sgblack@eecs.umich.edu } else { 9944636Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg); 9951061SN/A } 9961062SN/A 9971062SN/A ++renameRenameLookups; 9981061SN/A } 9991061SN/A} 10001061SN/A 10011061SN/Atemplate <class Impl> 10021061SN/Ainline void 10036221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10041061SN/A{ 10052292SN/A typename RenameMap::RenameInfo rename_result; 10061061SN/A 10071061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10081061SN/A 10092292SN/A // Rename the destination registers. 10102292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10112292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10123773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10133773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10144352Sgblack@eecs.umich.edu // Integer registers are flattened. 10156313Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 10163773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 10177649Sminkyu.jeong@arm.com } else if (dest_reg < TheISA::Max_DepTag) { 10184352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10194352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10204352Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 10214636Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg); 10227649Sminkyu.jeong@arm.com } else { 10237649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10243773Sgblack@eecs.umich.edu } 10253773Sgblack@eecs.umich.edu 10263773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10271061SN/A 10282292SN/A // Get the physical register that the destination will be 10292292SN/A // renamed to. 10303773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10311061SN/A 10322292SN/A //Mark Scoreboard entry as not ready 10332292SN/A scoreboard->unsetReg(rename_result.first); 10341062SN/A 10352292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10363773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10372292SN/A (int)rename_result.first); 10381062SN/A 10392292SN/A // Record the rename information so that a history can be kept. 10403773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10412292SN/A rename_result.first, 10422292SN/A rename_result.second); 10431062SN/A 10442292SN/A historyBuffer[tid].push_front(hb_entry); 10451062SN/A 10462935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10472935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10482935Sksewell@umich.edu historyBuffer[tid].size(), 10492292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10501062SN/A 10512292SN/A // Tell the instruction to rename the appropriate destination 10522292SN/A // register (dest_idx) to the new physical register 10532292SN/A // (rename_result.first), and record the previous physical 10542292SN/A // register that the same logical register was renamed to 10552292SN/A // (rename_result.second). 10562292SN/A inst->renameDestReg(dest_idx, 10572292SN/A rename_result.first, 10582292SN/A rename_result.second); 10591062SN/A 10602292SN/A ++renameRenamedOperands; 10611061SN/A } 10621061SN/A} 10631061SN/A 10641061SN/Atemplate <class Impl> 10651061SN/Ainline int 10666221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 10671061SN/A{ 10682292SN/A int num_free = freeEntries[tid].robEntries - 10692292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10702292SN/A 10712292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10722292SN/A 10732292SN/A return num_free; 10741061SN/A} 10751061SN/A 10761061SN/Atemplate <class Impl> 10771061SN/Ainline int 10786221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 10791061SN/A{ 10802292SN/A int num_free = freeEntries[tid].iqEntries - 10812292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10822292SN/A 10832292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10842292SN/A 10852292SN/A return num_free; 10862292SN/A} 10872292SN/A 10882292SN/Atemplate <class Impl> 10892292SN/Ainline int 10906221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 10912292SN/A{ 10922292SN/A int num_free = freeEntries[tid].lsqEntries - 10932292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10942292SN/A 10952292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 10962292SN/A 10972292SN/A return num_free; 10982292SN/A} 10992292SN/A 11002292SN/Atemplate <class Impl> 11012292SN/Aunsigned 11022292SN/ADefaultRename<Impl>::validInsts() 11032292SN/A{ 11042292SN/A unsigned inst_count = 0; 11052292SN/A 11062292SN/A for (int i=0; i<fromDecode->size; i++) { 11072731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11082292SN/A inst_count++; 11092292SN/A } 11102292SN/A 11112292SN/A return inst_count; 11122292SN/A} 11132292SN/A 11142292SN/Atemplate <class Impl> 11152292SN/Avoid 11166221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11172292SN/A{ 11182292SN/A if (fromIEW->iewBlock[tid]) { 11192292SN/A stalls[tid].iew = true; 11202292SN/A } 11212292SN/A 11222292SN/A if (fromIEW->iewUnblock[tid]) { 11232292SN/A assert(stalls[tid].iew); 11242292SN/A stalls[tid].iew = false; 11252292SN/A } 11262292SN/A 11272292SN/A if (fromCommit->commitBlock[tid]) { 11282292SN/A stalls[tid].commit = true; 11292292SN/A } 11302292SN/A 11312292SN/A if (fromCommit->commitUnblock[tid]) { 11322292SN/A assert(stalls[tid].commit); 11332292SN/A stalls[tid].commit = false; 11342292SN/A } 11352292SN/A} 11362292SN/A 11372292SN/Atemplate <class Impl> 11382292SN/Abool 11396221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11402292SN/A{ 11412292SN/A bool ret_val = false; 11422292SN/A 11432292SN/A if (stalls[tid].iew) { 11442292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11452292SN/A ret_val = true; 11462292SN/A } else if (stalls[tid].commit) { 11472292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11482292SN/A ret_val = true; 11492292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11502292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11512292SN/A ret_val = true; 11522292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11532292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11542292SN/A ret_val = true; 11552292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11562292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11572292SN/A ret_val = true; 11582292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11592292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11602292SN/A ret_val = true; 11612301SN/A } else if (renameStatus[tid] == SerializeStall && 11622292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11632301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11642292SN/A "empty.\n", 11652292SN/A tid); 11662292SN/A ret_val = true; 11672292SN/A } 11682292SN/A 11692292SN/A return ret_val; 11702292SN/A} 11712292SN/A 11722292SN/Atemplate <class Impl> 11732292SN/Avoid 11746221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 11752292SN/A{ 11762292SN/A bool updated = false; 11772292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 11782292SN/A freeEntries[tid].iqEntries = 11792292SN/A fromIEW->iewInfo[tid].freeIQEntries; 11802292SN/A updated = true; 11812292SN/A } 11822292SN/A 11832292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11842292SN/A freeEntries[tid].lsqEntries = 11852292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 11862292SN/A updated = true; 11872292SN/A } 11882292SN/A 11892292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11902292SN/A freeEntries[tid].robEntries = 11912292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11922292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11932292SN/A updated = true; 11942292SN/A } 11952292SN/A 11962292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11972292SN/A tid, 11982292SN/A freeEntries[tid].iqEntries, 11992292SN/A freeEntries[tid].robEntries, 12002292SN/A freeEntries[tid].lsqEntries); 12012292SN/A 12022292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12032292SN/A tid, instsInProgress[tid]); 12042292SN/A} 12052292SN/A 12062292SN/Atemplate <class Impl> 12072292SN/Abool 12086221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12092292SN/A{ 12102292SN/A // Check if there's a squash signal, squash if there is 12112292SN/A // Check stall signals, block if necessary. 12122292SN/A // If status was blocked 12132292SN/A // check if stall conditions have passed 12142292SN/A // if so then go to unblocking 12152292SN/A // If status was Squashing 12162292SN/A // check if squashing is not high. Switch to running this cycle. 12172301SN/A // If status was serialize stall 12182292SN/A // check if ROB is empty and no insts are in flight to the ROB 12192292SN/A 12202292SN/A readFreeEntries(tid); 12212292SN/A readStallSignals(tid); 12222292SN/A 12232292SN/A if (fromCommit->commitInfo[tid].squash) { 12242292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12252292SN/A "commit.\n", tid); 12262292SN/A 12274632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12282292SN/A 12292292SN/A return true; 12302292SN/A } 12312292SN/A 12322292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12332292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12342292SN/A 12352292SN/A renameStatus[tid] = Squashing; 12362292SN/A 12372292SN/A return true; 12382292SN/A } 12392292SN/A 12402292SN/A if (checkStall(tid)) { 12412292SN/A return block(tid); 12422292SN/A } 12432292SN/A 12442292SN/A if (renameStatus[tid] == Blocked) { 12452292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12462292SN/A tid); 12472292SN/A 12482292SN/A renameStatus[tid] = Unblocking; 12492292SN/A 12502292SN/A unblock(tid); 12512292SN/A 12522292SN/A return true; 12532292SN/A } 12542292SN/A 12552292SN/A if (renameStatus[tid] == Squashing) { 12562292SN/A // Switch status to running if rename isn't being told to block or 12572292SN/A // squash this cycle. 12583798Sgblack@eecs.umich.edu if (resumeSerialize) { 12593798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12603798Sgblack@eecs.umich.edu tid); 12612292SN/A 12623798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12633798Sgblack@eecs.umich.edu return true; 12643798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12653798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12663798Sgblack@eecs.umich.edu tid); 12673798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12683798Sgblack@eecs.umich.edu return true; 12693798Sgblack@eecs.umich.edu } else { 12703788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12713788Sgblack@eecs.umich.edu tid); 12722292SN/A 12733788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 12743788Sgblack@eecs.umich.edu return false; 12753788Sgblack@eecs.umich.edu } 12762292SN/A } 12772292SN/A 12782301SN/A if (renameStatus[tid] == SerializeStall) { 12792292SN/A // Stall ends once the ROB is free. 12802301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 12812292SN/A "unblocking.\n", tid); 12822292SN/A 12832301SN/A DynInstPtr serial_inst = serializeInst[tid]; 12842292SN/A 12852292SN/A renameStatus[tid] = Unblocking; 12862292SN/A 12872292SN/A unblock(tid); 12882292SN/A 12892292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 12902292SN/A "PC %#x.\n", 12912301SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 12922292SN/A 12932292SN/A // Put instruction into queue here. 12942301SN/A serial_inst->clearSerializeBefore(); 12952292SN/A 12962292SN/A if (!skidBuffer[tid].empty()) { 12972301SN/A skidBuffer[tid].push_front(serial_inst); 12982292SN/A } else { 12992301SN/A insts[tid].push_front(serial_inst); 13002292SN/A } 13012292SN/A 13022292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13032703Sktlim@umich.edu " Adding to front of list.\n", tid); 13042292SN/A 13052301SN/A serializeInst[tid] = NULL; 13062292SN/A 13072292SN/A return true; 13082292SN/A } 13092292SN/A 13102292SN/A // If we've reached this point, we have not gotten any signals that 13112292SN/A // cause rename to change its status. Rename remains the same as before. 13122292SN/A return false; 13131061SN/A} 13141061SN/A 13151060SN/Atemplate<class Impl> 13161060SN/Avoid 13176221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13181060SN/A{ 13192292SN/A if (inst_list.empty()) { 13202292SN/A // Mark a bit to say that I must serialize on the next instruction. 13212292SN/A serializeOnNextInst[tid] = true; 13221060SN/A return; 13231060SN/A } 13241060SN/A 13252292SN/A // Set the next instruction as serializing. 13262292SN/A inst_list.front()->setSerializeBefore(); 13272292SN/A} 13282292SN/A 13292292SN/Atemplate <class Impl> 13302292SN/Ainline void 13312292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13322292SN/A{ 13332292SN/A switch (source) { 13342292SN/A case ROB: 13352292SN/A ++renameROBFullEvents; 13362292SN/A break; 13372292SN/A case IQ: 13382292SN/A ++renameIQFullEvents; 13392292SN/A break; 13402292SN/A case LSQ: 13412292SN/A ++renameLSQFullEvents; 13422292SN/A break; 13432292SN/A default: 13442292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13452292SN/A break; 13461060SN/A } 13472292SN/A} 13481060SN/A 13492292SN/Atemplate <class Impl> 13502292SN/Avoid 13512292SN/ADefaultRename<Impl>::dumpHistory() 13522292SN/A{ 13532980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13541060SN/A 13556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13561060SN/A 13576221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13581060SN/A 13596221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13602292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13612292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13622292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13631060SN/A 13642292SN/A buf_it++; 13651062SN/A } 13661060SN/A } 13671060SN/A} 1368