rename_impl.hh revision 6658
12SN/A/* 21762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Korey Sewell 302SN/A */ 312SN/A 322SN/A#include <list> 332SN/A 342SN/A#include "arch/isa_traits.hh" 352SN/A#include "arch/registers.hh" 361354SN/A#include "config/full_system.hh" 371354SN/A#include "config/the_isa.hh" 382SN/A#include "cpu/o3/rename.hh" 392SN/A#include "params/DerivO3CPU.hh" 405501Snate@binkert.org 415546Snate@binkert.orgusing namespace std; 427004Snate@binkert.org 432SN/Atemplate <class Impl> 442SN/ADefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 4556SN/A : cpu(_cpu), 465769Snate@binkert.org iewToRenameDelay(params->iewToRenameDelay), 472361SN/A decodeToRenameDelay(params->decodeToRenameDelay), 481354SN/A commitToRenameDelay(params->commitToRenameDelay), 496216Snate@binkert.org renameWidth(params->renameWidth), 5056SN/A commitWidth(params->commitWidth), 512SN/A resumeSerialize(false), 525543Ssaidi@eecs.umich.edu resumeUnblocking(false), 532SN/A numThreads(params->numThreads), 541354SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 551354SN/A{ 562SN/A _status = Inactive; 572SN/A 582SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 592SN/A renameStatus[tid] = Idle; 605501Snate@binkert.org 615501Snate@binkert.org freeEntries[tid].iqEntries = 0; 622SN/A freeEntries[tid].lsqEntries = 0; 63395SN/A freeEntries[tid].robEntries = 0; 642SN/A 652SN/A stalls[tid].iew = false; 662SN/A stalls[tid].commit = false; 675769Snate@binkert.org serializeInst[tid] = NULL; 685769Snate@binkert.org 695769Snate@binkert.org instsInProgress[tid] = 0; 705769Snate@binkert.org 717059Snate@binkert.org emptyROB[tid] = true; 727059Snate@binkert.org 737059Snate@binkert.org serializeOnNextInst[tid] = false; 747059Snate@binkert.org } 757059Snate@binkert.org 767059Snate@binkert.org // @todo: Make into a parameter. 777059Snate@binkert.org skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 787059Snate@binkert.org} 797059Snate@binkert.org 807059Snate@binkert.orgtemplate <class Impl> 817059Snate@binkert.orgstd::string 827059Snate@binkert.orgDefaultRename<Impl>::name() const 837059Snate@binkert.org{ 847059Snate@binkert.org return cpu->name() + ".rename"; 857059Snate@binkert.org} 867059Snate@binkert.org 875769Snate@binkert.orgtemplate <class Impl> 887058Snate@binkert.orgvoid 897058Snate@binkert.orgDefaultRename<Impl>::regStats() 907058Snate@binkert.org{ 912SN/A renameSquashCycles 925502Snate@binkert.org .name(name() + ".RENAME:SquashCycles") 935502Snate@binkert.org .desc("Number of cycles rename is squashing") 945502Snate@binkert.org .prereq(renameSquashCycles); 955503Snate@binkert.org renameIdleCycles 965503Snate@binkert.org .name(name() + ".RENAME:IdleCycles") 975502Snate@binkert.org .desc("Number of cycles rename is idle") 985502Snate@binkert.org .prereq(renameIdleCycles); 995502Snate@binkert.org renameBlockCycles 1005502Snate@binkert.org .name(name() + ".RENAME:BlockCycles") 1015502Snate@binkert.org .desc("Number of cycles rename is blocking") 1025502Snate@binkert.org .prereq(renameBlockCycles); 1035502Snate@binkert.org renameSerializeStallCycles 1045602Snate@binkert.org .name(name() + ".RENAME:serializeStallCycles") 1055602Snate@binkert.org .desc("count of cycles rename stalled for serializing inst") 1065501Snate@binkert.org .flags(Stats::total); 1075543Ssaidi@eecs.umich.edu renameRunCycles 1087058Snate@binkert.org .name(name() + ".RENAME:RunCycles") 1095769Snate@binkert.org .desc("Number of cycles rename is running") 1104016Sstever@eecs.umich.edu .prereq(renameIdleCycles); 1114016Sstever@eecs.umich.edu renameUnblockCycles 1124016Sstever@eecs.umich.edu .name(name() + ".RENAME:UnblockCycles") 1134016Sstever@eecs.umich.edu .desc("Number of cycles rename is unblocking") 1144016Sstever@eecs.umich.edu .prereq(renameUnblockCycles); 1154016Sstever@eecs.umich.edu renameRenamedInsts 1164016Sstever@eecs.umich.edu .name(name() + ".RENAME:RenamedInsts") 1174016Sstever@eecs.umich.edu .desc("Number of instructions processed by rename") 1184016Sstever@eecs.umich.edu .prereq(renameRenamedInsts); 1195501Snate@binkert.org renameSquashedInsts 1205605Snate@binkert.org .name(name() + ".RENAME:SquashedInsts") 1215605Snate@binkert.org .desc("Number of squashed instructions processed by rename") 1225605Snate@binkert.org .prereq(renameSquashedInsts); 1235605Snate@binkert.org renameROBFullEvents 1245501Snate@binkert.org .name(name() + ".RENAME:ROBFullEvents") 1254016Sstever@eecs.umich.edu .desc("Number of times rename has blocked due to ROB full") 1265577SSteve.Reinhardt@amd.com .prereq(renameROBFullEvents); 1275501Snate@binkert.org renameIQFullEvents 1285501Snate@binkert.org .name(name() + ".RENAME:IQFullEvents") 1295501Snate@binkert.org .desc("Number of times rename has blocked due to IQ full") 1305502Snate@binkert.org .prereq(renameIQFullEvents); 1315502Snate@binkert.org renameLSQFullEvents 1325605Snate@binkert.org .name(name() + ".RENAME:LSQFullEvents") 1335502Snate@binkert.org .desc("Number of times rename has blocked due to LSQ full") 1345502Snate@binkert.org .prereq(renameLSQFullEvents); 1355605Snate@binkert.org renameFullRegistersEvents 1365605Snate@binkert.org .name(name() + ".RENAME:FullRegisterEvents") 1375605Snate@binkert.org .desc("Number of times there has been no free registers") 1385577SSteve.Reinhardt@amd.com .prereq(renameFullRegistersEvents); 1395502Snate@binkert.org renameRenamedOperands 1405502Snate@binkert.org .name(name() + ".RENAME:RenamedOperands") 1415502Snate@binkert.org .desc("Number of destination operands rename has renamed") 1425502Snate@binkert.org .prereq(renameRenamedOperands); 1432SN/A renameRenameLookups 1445769Snate@binkert.org .name(name() + ".RENAME:RenameLookups") 1455769Snate@binkert.org .desc("Number of register rename lookups that rename has made") 1465769Snate@binkert.org .prereq(renameRenameLookups); 1475769Snate@binkert.org renameCommittedMaps 1485769Snate@binkert.org .name(name() + ".RENAME:CommittedMaps") 1495769Snate@binkert.org .desc("Number of HB maps that are committed") 1502SN/A .prereq(renameCommittedMaps); 1515769Snate@binkert.org renameUndoneMaps 1525769Snate@binkert.org .name(name() + ".RENAME:UndoneMaps") 1535769Snate@binkert.org .desc("Number of HB maps that are undone due to squashing") 1547059Snate@binkert.org .prereq(renameUndoneMaps); 1555769Snate@binkert.org renamedSerializing 1565769Snate@binkert.org .name(name() + ".RENAME:serializingInsts") 1572SN/A .desc("count of serializing insts renamed") 1585769Snate@binkert.org .flags(Stats::total) 1595769Snate@binkert.org ; 1605769Snate@binkert.org renamedTempSerializing 1615769Snate@binkert.org .name(name() + ".RENAME:tempSerializingInsts") 1625769Snate@binkert.org .desc("count of temporary serializing insts renamed") 1635769Snate@binkert.org .flags(Stats::total) 1645769Snate@binkert.org ; 1655769Snate@binkert.org renameSkidInsts 1665769Snate@binkert.org .name(name() + ".RENAME:skidInsts") 1675769Snate@binkert.org .desc("count of insts added to the skid buffer") 1685769Snate@binkert.org .flags(Stats::total) 1695769Snate@binkert.org ; 1705769Snate@binkert.org} 1715769Snate@binkert.org 1725769Snate@binkert.orgtemplate <class Impl> 1735769Snate@binkert.orgvoid 1745769Snate@binkert.orgDefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1755769Snate@binkert.org{ 1765769Snate@binkert.org timeBuffer = tb_ptr; 1775769Snate@binkert.org 1785769Snate@binkert.org // Setup wire to read information from time buffer, from IEW stage. 1795769Snate@binkert.org fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1805769Snate@binkert.org 1815769Snate@binkert.org // Setup wire to read infromation from time buffer, from commit stage. 1825769Snate@binkert.org fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1835769Snate@binkert.org 1845769Snate@binkert.org // Setup wire to write information to previous stages. 1855769Snate@binkert.org toDecode = timeBuffer->getWire(0); 1865501Snate@binkert.org} 1875543Ssaidi@eecs.umich.edu 1882SN/Atemplate <class Impl> 1892SN/Avoid 190396SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 191396SN/A{ 192396SN/A renameQueue = rq_ptr; 193396SN/A 1945501Snate@binkert.org // Setup wire to write information to future stages. 1957058Snate@binkert.org toIEW = renameQueue->getWire(0); 1967058Snate@binkert.org} 1973329Sstever@eecs.umich.edu 1987058Snate@binkert.orgtemplate <class Impl> 1997058Snate@binkert.orgvoid 2007058Snate@binkert.orgDefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2017058Snate@binkert.org{ 202396SN/A decodeQueue = dq_ptr; 2037058Snate@binkert.org 2047058Snate@binkert.org // Setup wire to get information from decode. 2057058Snate@binkert.org fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2067058Snate@binkert.org} 2073329Sstever@eecs.umich.edu 2087058Snate@binkert.orgtemplate <class Impl> 2097058Snate@binkert.orgvoid 2107058Snate@binkert.orgDefaultRename<Impl>::initStage() 2117058Snate@binkert.org{ 2127058Snate@binkert.org // Grab the number of free entries directly from the stages. 213396SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2147058Snate@binkert.org freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2157058Snate@binkert.org freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2167058Snate@binkert.org freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2177058Snate@binkert.org emptyROB[tid] = true; 218396SN/A } 2197058Snate@binkert.org} 2207058Snate@binkert.org 221396SN/Atemplate<class Impl> 2227058Snate@binkert.orgvoid 2237058Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2247058Snate@binkert.org{ 2257058Snate@binkert.org activeThreads = at_ptr; 226396SN/A} 2277058Snate@binkert.org 2287058Snate@binkert.org 2297058Snate@binkert.orgtemplate <class Impl> 230396SN/Avoid 2317058Snate@binkert.orgDefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2327058Snate@binkert.org{ 2337058Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2344075Sbinkertn@umich.edu renameMap[tid] = &rm_ptr[tid]; 2357058Snate@binkert.org} 2367058Snate@binkert.org 2375501Snate@binkert.orgtemplate <class Impl> 2387058Snate@binkert.orgvoid 2397058Snate@binkert.orgDefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2407058Snate@binkert.org{ 2417058Snate@binkert.org freeList = fl_ptr; 2427058Snate@binkert.org} 2437058Snate@binkert.org 244396SN/Atemplate<class Impl> 2452SN/Avoid 2462SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2472SN/A{ 2482SN/A scoreboard = _scoreboard; 2495605Snate@binkert.org} 2507059Snate@binkert.org 251224SN/Atemplate <class Impl> 2524016Sstever@eecs.umich.edubool 2535501Snate@binkert.orgDefaultRename<Impl>::drain() 2545605Snate@binkert.org{ 2555501Snate@binkert.org // Rename is ready to switch out at any time. 2565501Snate@binkert.org cpu->signalDrained(); 2575501Snate@binkert.org return true; 2585501Snate@binkert.org} 2594016Sstever@eecs.umich.edu 260224SN/Atemplate <class Impl> 261224SN/Avoid 2625768Snate@binkert.orgDefaultRename<Impl>::switchOut() 2635768Snate@binkert.org{ 264265SN/A // Clear any state, fix up the rename map. 2655501Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2665501Snate@binkert.org typename std::list<RenameHistory>::iterator hb_it = 2675501Snate@binkert.org historyBuffer[tid].begin(); 2685501Snate@binkert.org 2695501Snate@binkert.org while (!historyBuffer[tid].empty()) { 2705501Snate@binkert.org assert(hb_it != historyBuffer[tid].end()); 2715501Snate@binkert.org 2725501Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2735501Snate@binkert.org "number %i.\n", tid, (*hb_it).instSeqNum); 2745501Snate@binkert.org 2755501Snate@binkert.org // Tell the rename map to set the architected register to the 2765501Snate@binkert.org // previous physical register that it was renamed to. 2775501Snate@binkert.org renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2785501Snate@binkert.org 2795501Snate@binkert.org // Put the renamed physical register back on the free list. 2805501Snate@binkert.org freeList->addReg(hb_it->newPhysReg); 2815501Snate@binkert.org 2825501Snate@binkert.org // Be sure to mark its register as ready if it's a misc register. 2835501Snate@binkert.org if (hb_it->newPhysReg >= maxPhysicalRegs) { 2845501Snate@binkert.org scoreboard->setReg(hb_it->newPhysReg); 2855501Snate@binkert.org } 2862SN/A 2875769Snate@binkert.org historyBuffer[tid].erase(hb_it++); 2882SN/A } 2892SN/A insts[tid].clear(); 2905769Snate@binkert.org skidBuffer[tid].clear(); 2912SN/A } 2922SN/A} 2935769Snate@binkert.org 2942SN/Atemplate <class Impl> 2952667Sstever@eecs.umich.eduvoid 2965769Snate@binkert.orgDefaultRename<Impl>::takeOverFrom() 2972667Sstever@eecs.umich.edu{ 2982SN/A _status = Inactive; 2992SN/A initStage(); 3002SN/A 3012SN/A // Reset all state prior to taking over from the other CPU. 3027058Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3032SN/A renameStatus[tid] = Idle; 3045605Snate@binkert.org 3055501Snate@binkert.org stalls[tid].iew = false; 3065501Snate@binkert.org stalls[tid].commit = false; 3072SN/A serializeInst[tid] = NULL; 3085501Snate@binkert.org 3095501Snate@binkert.org instsInProgress[tid] = 0; 3105501Snate@binkert.org 3112SN/A emptyROB[tid] = true; 3122SN/A 3132SN/A serializeOnNextInst[tid] = false; 314224SN/A } 315224SN/A} 316237SN/A 3175605Snate@binkert.orgtemplate <class Impl> 318571SN/Avoid 319571SN/ADefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3207005Snate@binkert.org{ 3217005Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3227005Snate@binkert.org 3237005Snate@binkert.org // Clear the stall signal if rename was blocked or unblocking before. 3247005Snate@binkert.org // If it still needs to block, the blocking should happen the next 3257005Snate@binkert.org // cycle and there should be space to hold everything due to the squash. 3267005Snate@binkert.org if (renameStatus[tid] == Blocked || 3277005Snate@binkert.org renameStatus[tid] == Unblocking) { 3287005Snate@binkert.org toDecode->renameUnblock[tid] = 1; 3297005Snate@binkert.org 3307005Snate@binkert.org resumeSerialize = false; 3317005Snate@binkert.org serializeInst[tid] = NULL; 3327005Snate@binkert.org } else if (renameStatus[tid] == SerializeStall) { 3337005Snate@binkert.org if (serializeInst[tid]->seqNum <= squash_seq_num) { 3347005Snate@binkert.org DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3357005Snate@binkert.org resumeSerialize = true; 3367005Snate@binkert.org assert(serializeInst[tid]); 3377005Snate@binkert.org } else { 3387005Snate@binkert.org resumeSerialize = false; 3397005Snate@binkert.org toDecode->renameUnblock[tid] = 1; 3407005Snate@binkert.org 3417005Snate@binkert.org serializeInst[tid] = NULL; 3427005Snate@binkert.org } 3437005Snate@binkert.org } 3447005Snate@binkert.org 3457005Snate@binkert.org // Set the status to Squashing. 3467005Snate@binkert.org renameStatus[tid] = Squashing; 3477005Snate@binkert.org 3487005Snate@binkert.org // Squash any instructions from decode. 3497005Snate@binkert.org unsigned squashCount = 0; 3507005Snate@binkert.org 3517005Snate@binkert.org for (int i=0; i<fromDecode->size; i++) { 3527005Snate@binkert.org if (fromDecode->insts[i]->threadNumber == tid && 3537005Snate@binkert.org fromDecode->insts[i]->seqNum > squash_seq_num) { 3547005Snate@binkert.org fromDecode->insts[i]->setSquashed(); 3557005Snate@binkert.org wroteToTimeBuffer = true; 3567005Snate@binkert.org squashCount++; 3577005Snate@binkert.org } 3587005Snate@binkert.org 3597005Snate@binkert.org } 3607005Snate@binkert.org 3612SN/A // Clear the instruction list and skid buffer in case they have any 3622SN/A // insts in them. 3632SN/A insts[tid].clear(); 364395SN/A 3652SN/A // Clear the skid buffer in case it has any data in it. 3665605Snate@binkert.org skidBuffer[tid].clear(); 367265SN/A 3682SN/A doSquash(squash_seq_num, tid); 3692SN/A} 3702SN/A 3712SN/Atemplate <class Impl> 3722SN/Avoid 3737063Snate@binkert.orgDefaultRename<Impl>::tick() 3747063Snate@binkert.org{ 3757063Snate@binkert.org wroteToTimeBuffer = false; 3762SN/A 3777063Snate@binkert.org blockThisCycle = false; 3782SN/A 379512SN/A bool status_change = false; 380265SN/A 3812SN/A toIEWIndex = 0; 3825738Snate@binkert.org 3835738Snate@binkert.org sortInsts(); 3845738Snate@binkert.org 3852SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 3865501Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3872667Sstever@eecs.umich.edu 3882SN/A // Check stall and squash signals. 3892SN/A while (threads != end) { 3902SN/A ThreadID tid = *threads++; 3912SN/A 3925501Snate@binkert.org DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3935501Snate@binkert.org 3945501Snate@binkert.org status_change = checkSignalsAndUpdate(tid) || status_change; 3952SN/A 3962SN/A rename(status_change, tid); 3972SN/A } 3982SN/A 3991634SN/A if (status_change) { 4001634SN/A updateStatus(); 4011634SN/A } 4021634SN/A 4031634SN/A if (wroteToTimeBuffer) { 4042SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4052SN/A cpu->activityThisCycle(); 4062SN/A } 4072SN/A 4082SN/A threads = activeThreads->begin(); 4092SN/A 4102SN/A while (threads != end) { 4112SN/A ThreadID tid = *threads++; 4125501Snate@binkert.org 4132SN/A // If we committed this cycle then doneSeqNum will be > 0 4145501Snate@binkert.org if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4152SN/A !fromCommit->commitInfo[tid].squash && 4162SN/A renameStatus[tid] != Squashing) { 4172SN/A 4185502Snate@binkert.org removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4195502Snate@binkert.org tid); 4205605Snate@binkert.org } 421217SN/A } 422237SN/A 4235605Snate@binkert.org // @todo: make into updateProgress function 4242SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4252SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4265605Snate@binkert.org 4275605Snate@binkert.org assert(instsInProgress[tid] >=0); 4285605Snate@binkert.org } 4295605Snate@binkert.org 4305605Snate@binkert.org} 4315605Snate@binkert.org 4322SN/Atemplate<class Impl> 4335605Snate@binkert.orgvoid 4345605Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4355605Snate@binkert.org{ 4365605Snate@binkert.org // If status is Running or idle, 4372SN/A // call renameInsts() 4385605Snate@binkert.org // If status is Unblocking, 4395605Snate@binkert.org // buffer any instructions coming from decode 4405605Snate@binkert.org // continue trying to empty skid buffer 4415605Snate@binkert.org // check if stall conditions have passed 4425605Snate@binkert.org 4435605Snate@binkert.org if (renameStatus[tid] == Blocked) { 4447060Snate@binkert.org ++renameBlockCycles; 4457060Snate@binkert.org } else if (renameStatus[tid] == Squashing) { 4467060Snate@binkert.org ++renameSquashCycles; 4477060Snate@binkert.org } else if (renameStatus[tid] == SerializeStall) { 4487060Snate@binkert.org ++renameSerializeStallCycles; 4495605Snate@binkert.org // If we are currently in SerializeStall and resumeSerialize 4505605Snate@binkert.org // was set, then that means that we are resuming serializing 4515605Snate@binkert.org // this cycle. Tell the previous stages to block. 4525605Snate@binkert.org if (resumeSerialize) { 4535605Snate@binkert.org resumeSerialize = false; 4545605Snate@binkert.org block(tid); 4555605Snate@binkert.org toDecode->renameUnblock[tid] = false; 4565605Snate@binkert.org } 4575605Snate@binkert.org } else if (renameStatus[tid] == Unblocking) { 4585605Snate@binkert.org if (resumeUnblocking) { 4595605Snate@binkert.org block(tid); 4605605Snate@binkert.org resumeUnblocking = false; 4615605Snate@binkert.org toDecode->renameUnblock[tid] = false; 4625605Snate@binkert.org } 4635605Snate@binkert.org } 4645605Snate@binkert.org 4655605Snate@binkert.org if (renameStatus[tid] == Running || 4665605Snate@binkert.org renameStatus[tid] == Idle) { 4675605Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4685605Snate@binkert.org "stage.\n", tid); 4695605Snate@binkert.org 4705605Snate@binkert.org renameInsts(tid); 4715605Snate@binkert.org } else if (renameStatus[tid] == Unblocking) { 4725605Snate@binkert.org renameInsts(tid); 4735605Snate@binkert.org 4745605Snate@binkert.org if (validInsts()) { 4755605Snate@binkert.org // Add the current inputs to the skid buffer so they can be 4765605Snate@binkert.org // reprocessed when this stage unblocks. 4775605Snate@binkert.org skidInsert(tid); 4785605Snate@binkert.org } 4795605Snate@binkert.org 4805605Snate@binkert.org // If we switched over to blocking, then there's a potential for 4815605Snate@binkert.org // an overall status change. 4825605Snate@binkert.org status_change = unblock(tid) || status_change || blockThisCycle; 4835605Snate@binkert.org } 4845605Snate@binkert.org} 4855605Snate@binkert.org 4862SN/Atemplate <class Impl> 4875605Snate@binkert.orgvoid 4882SN/ADefaultRename<Impl>::renameInsts(ThreadID tid) 4896712Snate@binkert.org{ 4905605Snate@binkert.org // Instructions can be either in the skid buffer or the queue of 4917059Snate@binkert.org // instructions coming from decode, depending on the status. 4925605Snate@binkert.org int insts_available = renameStatus[tid] == Unblocking ? 4935605Snate@binkert.org skidBuffer[tid].size() : insts[tid].size(); 4945605Snate@binkert.org 4955769Snate@binkert.org // Check the decode queue to see if instructions are available. 4965605Snate@binkert.org // If there are no available instructions to rename, then do nothing. 4975769Snate@binkert.org if (insts_available == 0) { 4985605Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4995769Snate@binkert.org tid); 5005605Snate@binkert.org // Should I change status to idle? 5015605Snate@binkert.org ++renameIdleCycles; 5025605Snate@binkert.org return; 5032SN/A } else if (renameStatus[tid] == Unblocking) { 5042SN/A ++renameUnblockCycles; 5052SN/A } else if (renameStatus[tid] == Running) { 5065605Snate@binkert.org ++renameRunCycles; 5072SN/A } 5085605Snate@binkert.org 5097059Snate@binkert.org DynInstPtr inst; 5105605Snate@binkert.org 5115605Snate@binkert.org // Will have to do a different calculation for the number of free 5125605Snate@binkert.org // entries. 5135769Snate@binkert.org int free_rob_entries = calcFreeROBEntries(tid); 5145769Snate@binkert.org int free_iq_entries = calcFreeIQEntries(tid); 5155605Snate@binkert.org int free_lsq_entries = calcFreeLSQEntries(tid); 5165769Snate@binkert.org int min_free_entries = free_rob_entries; 5175605Snate@binkert.org 5185605Snate@binkert.org FullSource source = ROB; 5195605Snate@binkert.org 5205605Snate@binkert.org if (free_iq_entries < min_free_entries) { 5212SN/A min_free_entries = free_iq_entries; 5222SN/A source = IQ; 5232SN/A } 5245605Snate@binkert.org 5252SN/A if (free_lsq_entries < min_free_entries) { 5265605Snate@binkert.org min_free_entries = free_lsq_entries; 5275605Snate@binkert.org source = LSQ; 5287059Snate@binkert.org } 5295605Snate@binkert.org 5305605Snate@binkert.org // Check if there's any space left. 5315605Snate@binkert.org if (min_free_entries <= 0) { 5325605Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5335605Snate@binkert.org "entries.\n" 5345605Snate@binkert.org "ROB has %i free entries.\n" 5355769Snate@binkert.org "IQ has %i free entries.\n" 5365769Snate@binkert.org "LSQ has %i free entries.\n", 5375605Snate@binkert.org tid, 5385769Snate@binkert.org free_rob_entries, 5395605Snate@binkert.org free_iq_entries, 5405769Snate@binkert.org free_lsq_entries); 5415605Snate@binkert.org 5425605Snate@binkert.org blockThisCycle = true; 5435605Snate@binkert.org 5442SN/A block(tid); 5452SN/A 5467005Snate@binkert.org incrFullStat(source); 5477005Snate@binkert.org 5487005Snate@binkert.org return; 5495502Snate@binkert.org } else if (min_free_entries < insts_available) { 5507005Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5517005Snate@binkert.org "%i insts available, but only %i insts can be " 5527005Snate@binkert.org "renamed due to ROB/IQ/LSQ limits.\n", 5537005Snate@binkert.org tid, insts_available, min_free_entries); 5547005Snate@binkert.org 5557005Snate@binkert.org insts_available = min_free_entries; 5567005Snate@binkert.org 5577005Snate@binkert.org blockThisCycle = true; 5587005Snate@binkert.org 5597005Snate@binkert.org incrFullStat(source); 5607005Snate@binkert.org } 5617005Snate@binkert.org 5627005Snate@binkert.org InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5637005Snate@binkert.org skidBuffer[tid] : insts[tid]; 5645502Snate@binkert.org 5655502Snate@binkert.org DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5667005Snate@binkert.org "send iew.\n", tid, insts_available); 5677005Snate@binkert.org 5685502Snate@binkert.org DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5697005Snate@binkert.org "dispatched to IQ last cycle.\n", 5707005Snate@binkert.org tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5715502Snate@binkert.org 5727005Snate@binkert.org // Handle serializing the next instruction if necessary. 5737005Snate@binkert.org if (serializeOnNextInst[tid]) { 5747005Snate@binkert.org if (emptyROB[tid] && instsInProgress[tid] == 0) { 5757005Snate@binkert.org // ROB already empty; no need to serialize. 5767005Snate@binkert.org serializeOnNextInst[tid] = false; 5777005Snate@binkert.org } else if (!insts_to_rename.empty()) { 5787005Snate@binkert.org insts_to_rename.front()->setSerializeBefore(); 5795502Snate@binkert.org } 5807066Snate@binkert.org } 5817066Snate@binkert.org 5827066Snate@binkert.org int renamed_insts = 0; 5837066Snate@binkert.org 5847066Snate@binkert.org while (insts_available > 0 && toIEWIndex < renameWidth) { 5857066Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5867066Snate@binkert.org 5877005Snate@binkert.org assert(!insts_to_rename.empty()); 5885502Snate@binkert.org 5897005Snate@binkert.org inst = insts_to_rename.front(); 5907005Snate@binkert.org 5917005Snate@binkert.org insts_to_rename.pop_front(); 5927005Snate@binkert.org 5937005Snate@binkert.org if (renameStatus[tid] == Unblocking) { 5947005Snate@binkert.org DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 5957005Snate@binkert.org "skidBuffer\n", 5967005Snate@binkert.org tid, inst->seqNum, inst->readPC()); 5975605Snate@binkert.org } 5982SN/A 5991354SN/A if (inst->isSquashed()) { 600 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 601 "squashed, skipping.\n", 602 tid, inst->seqNum, inst->readPC()); 603 604 ++renameSquashedInsts; 605 606 // Decrement how many instructions are available. 607 --insts_available; 608 609 continue; 610 } 611 612 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 613 "PC %#x.\n", 614 tid, inst->seqNum, inst->readPC()); 615 616 // Handle serializeAfter/serializeBefore instructions. 617 // serializeAfter marks the next instruction as serializeBefore. 618 // serializeBefore makes the instruction wait in rename until the ROB 619 // is empty. 620 621 // In this model, IPR accesses are serialize before 622 // instructions, and store conditionals are serialize after 623 // instructions. This is mainly due to lack of support for 624 // out-of-order operations of either of those classes of 625 // instructions. 626 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 627 !inst->isSerializeHandled()) { 628 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 629 630 if (!inst->isTempSerializeBefore()) { 631 renamedSerializing++; 632 inst->setSerializeHandled(); 633 } else { 634 renamedTempSerializing++; 635 } 636 637 // Change status over to SerializeStall so that other stages know 638 // what this is blocked on. 639 renameStatus[tid] = SerializeStall; 640 641 serializeInst[tid] = inst; 642 643 blockThisCycle = true; 644 645 break; 646 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 647 !inst->isSerializeHandled()) { 648 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 649 650 renamedSerializing++; 651 652 inst->setSerializeHandled(); 653 654 serializeAfter(insts_to_rename, tid); 655 } 656 657 // Check here to make sure there are enough destination registers 658 // to rename to. Otherwise block. 659 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 660 DPRINTF(Rename, "Blocking due to lack of free " 661 "physical registers to rename to.\n"); 662 blockThisCycle = true; 663 insts_to_rename.push_front(inst); 664 ++renameFullRegistersEvents; 665 666 break; 667 } 668 669 renameSrcRegs(inst, inst->threadNumber); 670 671 renameDestRegs(inst, inst->threadNumber); 672 673 ++renamed_insts; 674 675 // Put instruction in rename queue. 676 toIEW->insts[toIEWIndex] = inst; 677 ++(toIEW->size); 678 679 // Increment which instruction we're on. 680 ++toIEWIndex; 681 682 // Decrement how many instructions are available. 683 --insts_available; 684 } 685 686 instsInProgress[tid] += renamed_insts; 687 renameRenamedInsts += renamed_insts; 688 689 // If we wrote to the time buffer, record this. 690 if (toIEWIndex) { 691 wroteToTimeBuffer = true; 692 } 693 694 // Check if there's any instructions left that haven't yet been renamed. 695 // If so then block. 696 if (insts_available) { 697 blockThisCycle = true; 698 } 699 700 if (blockThisCycle) { 701 block(tid); 702 toDecode->renameUnblock[tid] = false; 703 } 704} 705 706template<class Impl> 707void 708DefaultRename<Impl>::skidInsert(ThreadID tid) 709{ 710 DynInstPtr inst = NULL; 711 712 while (!insts[tid].empty()) { 713 inst = insts[tid].front(); 714 715 insts[tid].pop_front(); 716 717 assert(tid == inst->threadNumber); 718 719 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 720 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 721 722 ++renameSkidInsts; 723 724 skidBuffer[tid].push_back(inst); 725 } 726 727 if (skidBuffer[tid].size() > skidBufferMax) 728 { 729 typename InstQueue::iterator it; 730 warn("Skidbuffer contents:\n"); 731 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 732 { 733 warn("[tid:%u]: %s [sn:%i].\n", tid, 734 (*it)->staticInst->disassemble(inst->readPC()), 735 (*it)->seqNum); 736 } 737 panic("Skidbuffer Exceeded Max Size"); 738 } 739} 740 741template <class Impl> 742void 743DefaultRename<Impl>::sortInsts() 744{ 745 int insts_from_decode = fromDecode->size; 746#ifdef DEBUG 747 for (ThreadID tid = 0; tid < numThreads; tid++) 748 assert(insts[tid].empty()); 749#endif 750 for (int i = 0; i < insts_from_decode; ++i) { 751 DynInstPtr inst = fromDecode->insts[i]; 752 insts[inst->threadNumber].push_back(inst); 753 } 754} 755 756template<class Impl> 757bool 758DefaultRename<Impl>::skidsEmpty() 759{ 760 list<ThreadID>::iterator threads = activeThreads->begin(); 761 list<ThreadID>::iterator end = activeThreads->end(); 762 763 while (threads != end) { 764 ThreadID tid = *threads++; 765 766 if (!skidBuffer[tid].empty()) 767 return false; 768 } 769 770 return true; 771} 772 773template<class Impl> 774void 775DefaultRename<Impl>::updateStatus() 776{ 777 bool any_unblocking = false; 778 779 list<ThreadID>::iterator threads = activeThreads->begin(); 780 list<ThreadID>::iterator end = activeThreads->end(); 781 782 while (threads != end) { 783 ThreadID tid = *threads++; 784 785 if (renameStatus[tid] == Unblocking) { 786 any_unblocking = true; 787 break; 788 } 789 } 790 791 // Rename will have activity if it's unblocking. 792 if (any_unblocking) { 793 if (_status == Inactive) { 794 _status = Active; 795 796 DPRINTF(Activity, "Activating stage.\n"); 797 798 cpu->activateStage(O3CPU::RenameIdx); 799 } 800 } else { 801 // If it's not unblocking, then rename will not have any internal 802 // activity. Switch it to inactive. 803 if (_status == Active) { 804 _status = Inactive; 805 DPRINTF(Activity, "Deactivating stage.\n"); 806 807 cpu->deactivateStage(O3CPU::RenameIdx); 808 } 809 } 810} 811 812template <class Impl> 813bool 814DefaultRename<Impl>::block(ThreadID tid) 815{ 816 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 817 818 // Add the current inputs onto the skid buffer, so they can be 819 // reprocessed when this stage unblocks. 820 skidInsert(tid); 821 822 // Only signal backwards to block if the previous stages do not think 823 // rename is already blocked. 824 if (renameStatus[tid] != Blocked) { 825 // If resumeUnblocking is set, we unblocked during the squash, 826 // but now we're have unblocking status. We need to tell earlier 827 // stages to block. 828 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 829 toDecode->renameBlock[tid] = true; 830 toDecode->renameUnblock[tid] = false; 831 wroteToTimeBuffer = true; 832 } 833 834 // Rename can not go from SerializeStall to Blocked, otherwise 835 // it would not know to complete the serialize stall. 836 if (renameStatus[tid] != SerializeStall) { 837 // Set status to Blocked. 838 renameStatus[tid] = Blocked; 839 return true; 840 } 841 } 842 843 return false; 844} 845 846template <class Impl> 847bool 848DefaultRename<Impl>::unblock(ThreadID tid) 849{ 850 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 851 852 // Rename is done unblocking if the skid buffer is empty. 853 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 854 855 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 856 857 toDecode->renameUnblock[tid] = true; 858 wroteToTimeBuffer = true; 859 860 renameStatus[tid] = Running; 861 return true; 862 } 863 864 return false; 865} 866 867template <class Impl> 868void 869DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 870{ 871 typename std::list<RenameHistory>::iterator hb_it = 872 historyBuffer[tid].begin(); 873 874 // After a syscall squashes everything, the history buffer may be empty 875 // but the ROB may still be squashing instructions. 876 if (historyBuffer[tid].empty()) { 877 return; 878 } 879 880 // Go through the most recent instructions, undoing the mappings 881 // they did and freeing up the registers. 882 while (!historyBuffer[tid].empty() && 883 (*hb_it).instSeqNum > squashed_seq_num) { 884 assert(hb_it != historyBuffer[tid].end()); 885 886 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 887 "number %i.\n", tid, (*hb_it).instSeqNum); 888 889 // Tell the rename map to set the architected register to the 890 // previous physical register that it was renamed to. 891 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 892 893 // Put the renamed physical register back on the free list. 894 freeList->addReg(hb_it->newPhysReg); 895 896 // Be sure to mark its register as ready if it's a misc register. 897 if (hb_it->newPhysReg >= maxPhysicalRegs) { 898 scoreboard->setReg(hb_it->newPhysReg); 899 } 900 901 historyBuffer[tid].erase(hb_it++); 902 903 ++renameUndoneMaps; 904 } 905} 906 907template<class Impl> 908void 909DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 910{ 911 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 912 "history buffer %u (size=%i), until [sn:%lli].\n", 913 tid, tid, historyBuffer[tid].size(), inst_seq_num); 914 915 typename std::list<RenameHistory>::iterator hb_it = 916 historyBuffer[tid].end(); 917 918 --hb_it; 919 920 if (historyBuffer[tid].empty()) { 921 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 922 return; 923 } else if (hb_it->instSeqNum > inst_seq_num) { 924 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 925 "that a syscall happened recently.\n", tid); 926 return; 927 } 928 929 // Commit all the renames up until (and including) the committed sequence 930 // number. Some or even all of the committed instructions may not have 931 // rename histories if they did not have destination registers that were 932 // renamed. 933 while (!historyBuffer[tid].empty() && 934 hb_it != historyBuffer[tid].end() && 935 (*hb_it).instSeqNum <= inst_seq_num) { 936 937 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 938 "[sn:%lli].\n", 939 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 940 941 freeList->addReg((*hb_it).prevPhysReg); 942 ++renameCommittedMaps; 943 944 historyBuffer[tid].erase(hb_it--); 945 } 946} 947 948template <class Impl> 949inline void 950DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 951{ 952 assert(renameMap[tid] != 0); 953 954 unsigned num_src_regs = inst->numSrcRegs(); 955 956 // Get the architectual register numbers from the source and 957 // destination operands, and redirect them to the right register. 958 // Will need to mark dependencies though. 959 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 960 RegIndex src_reg = inst->srcRegIdx(src_idx); 961 RegIndex flat_src_reg = src_reg; 962 if (src_reg < TheISA::FP_Base_DepTag) { 963 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 964 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 965 } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 966 src_reg = src_reg - TheISA::FP_Base_DepTag; 967 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 968 flat_src_reg += TheISA::NumIntRegs; 969 } else { 970 flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 971 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); 972 } 973 974 inst->flattenSrcReg(src_idx, flat_src_reg); 975 976 // Look up the source registers to get the phys. register they've 977 // been renamed to, and set the sources to those registers. 978 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 979 980 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 981 "physical reg %i.\n", tid, (int)flat_src_reg, 982 (int)renamed_reg); 983 984 inst->renameSrcReg(src_idx, renamed_reg); 985 986 // See if the register is ready or not. 987 if (scoreboard->getReg(renamed_reg) == true) { 988 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg); 989 990 inst->markSrcRegReady(src_idx); 991 } else { 992 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg); 993 } 994 995 ++renameRenameLookups; 996 } 997} 998 999template <class Impl> 1000inline void 1001DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1002{ 1003 typename RenameMap::RenameInfo rename_result; 1004 1005 unsigned num_dest_regs = inst->numDestRegs(); 1006 1007 // Rename the destination registers. 1008 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1009 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1010 RegIndex flat_dest_reg = dest_reg; 1011 if (dest_reg < TheISA::FP_Base_DepTag) { 1012 // Integer registers are flattened. 1013 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 1014 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 1015 } else { 1016 // Floating point and Miscellaneous registers need their indexes 1017 // adjusted to account for the expanded number of flattened int regs. 1018 flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 1019 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg); 1020 } 1021 1022 inst->flattenDestReg(dest_idx, flat_dest_reg); 1023 1024 // Get the physical register that the destination will be 1025 // renamed to. 1026 rename_result = renameMap[tid]->rename(flat_dest_reg); 1027 1028 //Mark Scoreboard entry as not ready 1029 scoreboard->unsetReg(rename_result.first); 1030 1031 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1032 "reg %i.\n", tid, (int)flat_dest_reg, 1033 (int)rename_result.first); 1034 1035 // Record the rename information so that a history can be kept. 1036 RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 1037 rename_result.first, 1038 rename_result.second); 1039 1040 historyBuffer[tid].push_front(hb_entry); 1041 1042 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1043 "(size=%i), [sn:%lli].\n",tid, 1044 historyBuffer[tid].size(), 1045 (*historyBuffer[tid].begin()).instSeqNum); 1046 1047 // Tell the instruction to rename the appropriate destination 1048 // register (dest_idx) to the new physical register 1049 // (rename_result.first), and record the previous physical 1050 // register that the same logical register was renamed to 1051 // (rename_result.second). 1052 inst->renameDestReg(dest_idx, 1053 rename_result.first, 1054 rename_result.second); 1055 1056 ++renameRenamedOperands; 1057 } 1058} 1059 1060template <class Impl> 1061inline int 1062DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1063{ 1064 int num_free = freeEntries[tid].robEntries - 1065 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1066 1067 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1068 1069 return num_free; 1070} 1071 1072template <class Impl> 1073inline int 1074DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1075{ 1076 int num_free = freeEntries[tid].iqEntries - 1077 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1078 1079 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1080 1081 return num_free; 1082} 1083 1084template <class Impl> 1085inline int 1086DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 1087{ 1088 int num_free = freeEntries[tid].lsqEntries - 1089 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1090 1091 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1092 1093 return num_free; 1094} 1095 1096template <class Impl> 1097unsigned 1098DefaultRename<Impl>::validInsts() 1099{ 1100 unsigned inst_count = 0; 1101 1102 for (int i=0; i<fromDecode->size; i++) { 1103 if (!fromDecode->insts[i]->isSquashed()) 1104 inst_count++; 1105 } 1106 1107 return inst_count; 1108} 1109 1110template <class Impl> 1111void 1112DefaultRename<Impl>::readStallSignals(ThreadID tid) 1113{ 1114 if (fromIEW->iewBlock[tid]) { 1115 stalls[tid].iew = true; 1116 } 1117 1118 if (fromIEW->iewUnblock[tid]) { 1119 assert(stalls[tid].iew); 1120 stalls[tid].iew = false; 1121 } 1122 1123 if (fromCommit->commitBlock[tid]) { 1124 stalls[tid].commit = true; 1125 } 1126 1127 if (fromCommit->commitUnblock[tid]) { 1128 assert(stalls[tid].commit); 1129 stalls[tid].commit = false; 1130 } 1131} 1132 1133template <class Impl> 1134bool 1135DefaultRename<Impl>::checkStall(ThreadID tid) 1136{ 1137 bool ret_val = false; 1138 1139 if (stalls[tid].iew) { 1140 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1141 ret_val = true; 1142 } else if (stalls[tid].commit) { 1143 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1144 ret_val = true; 1145 } else if (calcFreeROBEntries(tid) <= 0) { 1146 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1147 ret_val = true; 1148 } else if (calcFreeIQEntries(tid) <= 0) { 1149 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1150 ret_val = true; 1151 } else if (calcFreeLSQEntries(tid) <= 0) { 1152 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1153 ret_val = true; 1154 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1155 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1156 ret_val = true; 1157 } else if (renameStatus[tid] == SerializeStall && 1158 (!emptyROB[tid] || instsInProgress[tid])) { 1159 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1160 "empty.\n", 1161 tid); 1162 ret_val = true; 1163 } 1164 1165 return ret_val; 1166} 1167 1168template <class Impl> 1169void 1170DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1171{ 1172 bool updated = false; 1173 if (fromIEW->iewInfo[tid].usedIQ) { 1174 freeEntries[tid].iqEntries = 1175 fromIEW->iewInfo[tid].freeIQEntries; 1176 updated = true; 1177 } 1178 1179 if (fromIEW->iewInfo[tid].usedLSQ) { 1180 freeEntries[tid].lsqEntries = 1181 fromIEW->iewInfo[tid].freeLSQEntries; 1182 updated = true; 1183 } 1184 1185 if (fromCommit->commitInfo[tid].usedROB) { 1186 freeEntries[tid].robEntries = 1187 fromCommit->commitInfo[tid].freeROBEntries; 1188 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1189 updated = true; 1190 } 1191 1192 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1193 tid, 1194 freeEntries[tid].iqEntries, 1195 freeEntries[tid].robEntries, 1196 freeEntries[tid].lsqEntries); 1197 1198 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1199 tid, instsInProgress[tid]); 1200} 1201 1202template <class Impl> 1203bool 1204DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1205{ 1206 // Check if there's a squash signal, squash if there is 1207 // Check stall signals, block if necessary. 1208 // If status was blocked 1209 // check if stall conditions have passed 1210 // if so then go to unblocking 1211 // If status was Squashing 1212 // check if squashing is not high. Switch to running this cycle. 1213 // If status was serialize stall 1214 // check if ROB is empty and no insts are in flight to the ROB 1215 1216 readFreeEntries(tid); 1217 readStallSignals(tid); 1218 1219 if (fromCommit->commitInfo[tid].squash) { 1220 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1221 "commit.\n", tid); 1222 1223 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1224 1225 return true; 1226 } 1227 1228 if (fromCommit->commitInfo[tid].robSquashing) { 1229 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1230 1231 renameStatus[tid] = Squashing; 1232 1233 return true; 1234 } 1235 1236 if (checkStall(tid)) { 1237 return block(tid); 1238 } 1239 1240 if (renameStatus[tid] == Blocked) { 1241 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1242 tid); 1243 1244 renameStatus[tid] = Unblocking; 1245 1246 unblock(tid); 1247 1248 return true; 1249 } 1250 1251 if (renameStatus[tid] == Squashing) { 1252 // Switch status to running if rename isn't being told to block or 1253 // squash this cycle. 1254 if (resumeSerialize) { 1255 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1256 tid); 1257 1258 renameStatus[tid] = SerializeStall; 1259 return true; 1260 } else if (resumeUnblocking) { 1261 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1262 tid); 1263 renameStatus[tid] = Unblocking; 1264 return true; 1265 } else { 1266 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1267 tid); 1268 1269 renameStatus[tid] = Running; 1270 return false; 1271 } 1272 } 1273 1274 if (renameStatus[tid] == SerializeStall) { 1275 // Stall ends once the ROB is free. 1276 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1277 "unblocking.\n", tid); 1278 1279 DynInstPtr serial_inst = serializeInst[tid]; 1280 1281 renameStatus[tid] = Unblocking; 1282 1283 unblock(tid); 1284 1285 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1286 "PC %#x.\n", 1287 tid, serial_inst->seqNum, serial_inst->readPC()); 1288 1289 // Put instruction into queue here. 1290 serial_inst->clearSerializeBefore(); 1291 1292 if (!skidBuffer[tid].empty()) { 1293 skidBuffer[tid].push_front(serial_inst); 1294 } else { 1295 insts[tid].push_front(serial_inst); 1296 } 1297 1298 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1299 " Adding to front of list.\n", tid); 1300 1301 serializeInst[tid] = NULL; 1302 1303 return true; 1304 } 1305 1306 // If we've reached this point, we have not gotten any signals that 1307 // cause rename to change its status. Rename remains the same as before. 1308 return false; 1309} 1310 1311template<class Impl> 1312void 1313DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1314{ 1315 if (inst_list.empty()) { 1316 // Mark a bit to say that I must serialize on the next instruction. 1317 serializeOnNextInst[tid] = true; 1318 return; 1319 } 1320 1321 // Set the next instruction as serializing. 1322 inst_list.front()->setSerializeBefore(); 1323} 1324 1325template <class Impl> 1326inline void 1327DefaultRename<Impl>::incrFullStat(const FullSource &source) 1328{ 1329 switch (source) { 1330 case ROB: 1331 ++renameROBFullEvents; 1332 break; 1333 case IQ: 1334 ++renameIQFullEvents; 1335 break; 1336 case LSQ: 1337 ++renameLSQFullEvents; 1338 break; 1339 default: 1340 panic("Rename full stall stat should be incremented for a reason!"); 1341 break; 1342 } 1343} 1344 1345template <class Impl> 1346void 1347DefaultRename<Impl>::dumpHistory() 1348{ 1349 typename std::list<RenameHistory>::iterator buf_it; 1350 1351 for (ThreadID tid = 0; tid < numThreads; tid++) { 1352 1353 buf_it = historyBuffer[tid].begin(); 1354 1355 while (buf_it != historyBuffer[tid].end()) { 1356 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1357 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1358 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1359 1360 buf_it++; 1361 } 1362 } 1363} 1364