rename_impl.hh revision 5529
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292935Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321060SN/A#include <list> 331060SN/A 343773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 353773Sgblack@eecs.umich.edu#include "arch/regfile.hh" 361858SN/A#include "config/full_system.hh" 371717SN/A#include "cpu/o3/rename.hh" 385529Snate@binkert.org#include "params/DerivO3CPU.hh" 391060SN/A 401061SN/Atemplate <class Impl> 415529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 424329Sktlim@umich.edu : cpu(_cpu), 434329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 442292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 452292SN/A commitToRenameDelay(params->commitToRenameDelay), 462292SN/A renameWidth(params->renameWidth), 472292SN/A commitWidth(params->commitWidth), 483788Sgblack@eecs.umich.edu resumeSerialize(false), 493798Sgblack@eecs.umich.edu resumeUnblocking(false), 505529Snate@binkert.org numThreads(params->numThreads), 512361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 521060SN/A{ 532292SN/A _status = Inactive; 542292SN/A 552292SN/A for (int i=0; i< numThreads; i++) { 562292SN/A renameStatus[i] = Idle; 572292SN/A 582292SN/A freeEntries[i].iqEntries = 0; 592292SN/A freeEntries[i].lsqEntries = 0; 602292SN/A freeEntries[i].robEntries = 0; 612292SN/A 622292SN/A stalls[i].iew = false; 632292SN/A stalls[i].commit = false; 642301SN/A serializeInst[i] = NULL; 652292SN/A 662292SN/A instsInProgress[i] = 0; 672292SN/A 682292SN/A emptyROB[i] = true; 692292SN/A 702292SN/A serializeOnNextInst[i] = false; 712292SN/A } 722292SN/A 732292SN/A // @todo: Make into a parameter. 742292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 752292SN/A} 762292SN/A 772292SN/Atemplate <class Impl> 782292SN/Astd::string 792292SN/ADefaultRename<Impl>::name() const 802292SN/A{ 812292SN/A return cpu->name() + ".rename"; 821060SN/A} 831060SN/A 841061SN/Atemplate <class Impl> 851060SN/Avoid 862292SN/ADefaultRename<Impl>::regStats() 871062SN/A{ 881062SN/A renameSquashCycles 892301SN/A .name(name() + ".RENAME:SquashCycles") 901062SN/A .desc("Number of cycles rename is squashing") 911062SN/A .prereq(renameSquashCycles); 921062SN/A renameIdleCycles 932301SN/A .name(name() + ".RENAME:IdleCycles") 941062SN/A .desc("Number of cycles rename is idle") 951062SN/A .prereq(renameIdleCycles); 961062SN/A renameBlockCycles 972301SN/A .name(name() + ".RENAME:BlockCycles") 981062SN/A .desc("Number of cycles rename is blocking") 991062SN/A .prereq(renameBlockCycles); 1002301SN/A renameSerializeStallCycles 1012301SN/A .name(name() + ".RENAME:serializeStallCycles") 1022301SN/A .desc("count of cycles rename stalled for serializing inst") 1032301SN/A .flags(Stats::total); 1042292SN/A renameRunCycles 1052301SN/A .name(name() + ".RENAME:RunCycles") 1062292SN/A .desc("Number of cycles rename is running") 1072292SN/A .prereq(renameIdleCycles); 1081062SN/A renameUnblockCycles 1092301SN/A .name(name() + ".RENAME:UnblockCycles") 1101062SN/A .desc("Number of cycles rename is unblocking") 1111062SN/A .prereq(renameUnblockCycles); 1121062SN/A renameRenamedInsts 1132301SN/A .name(name() + ".RENAME:RenamedInsts") 1141062SN/A .desc("Number of instructions processed by rename") 1151062SN/A .prereq(renameRenamedInsts); 1161062SN/A renameSquashedInsts 1172301SN/A .name(name() + ".RENAME:SquashedInsts") 1181062SN/A .desc("Number of squashed instructions processed by rename") 1191062SN/A .prereq(renameSquashedInsts); 1201062SN/A renameROBFullEvents 1212301SN/A .name(name() + ".RENAME:ROBFullEvents") 1222292SN/A .desc("Number of times rename has blocked due to ROB full") 1231062SN/A .prereq(renameROBFullEvents); 1241062SN/A renameIQFullEvents 1252301SN/A .name(name() + ".RENAME:IQFullEvents") 1262292SN/A .desc("Number of times rename has blocked due to IQ full") 1271062SN/A .prereq(renameIQFullEvents); 1282292SN/A renameLSQFullEvents 1292301SN/A .name(name() + ".RENAME:LSQFullEvents") 1302292SN/A .desc("Number of times rename has blocked due to LSQ full") 1312292SN/A .prereq(renameLSQFullEvents); 1321062SN/A renameFullRegistersEvents 1332301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1341062SN/A .desc("Number of times there has been no free registers") 1351062SN/A .prereq(renameFullRegistersEvents); 1361062SN/A renameRenamedOperands 1372301SN/A .name(name() + ".RENAME:RenamedOperands") 1381062SN/A .desc("Number of destination operands rename has renamed") 1391062SN/A .prereq(renameRenamedOperands); 1401062SN/A renameRenameLookups 1412301SN/A .name(name() + ".RENAME:RenameLookups") 1421062SN/A .desc("Number of register rename lookups that rename has made") 1431062SN/A .prereq(renameRenameLookups); 1441062SN/A renameCommittedMaps 1452301SN/A .name(name() + ".RENAME:CommittedMaps") 1461062SN/A .desc("Number of HB maps that are committed") 1471062SN/A .prereq(renameCommittedMaps); 1481062SN/A renameUndoneMaps 1492301SN/A .name(name() + ".RENAME:UndoneMaps") 1501062SN/A .desc("Number of HB maps that are undone due to squashing") 1511062SN/A .prereq(renameUndoneMaps); 1522301SN/A renamedSerializing 1532301SN/A .name(name() + ".RENAME:serializingInsts") 1542301SN/A .desc("count of serializing insts renamed") 1552301SN/A .flags(Stats::total) 1562301SN/A ; 1572301SN/A renamedTempSerializing 1582301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1592301SN/A .desc("count of temporary serializing insts renamed") 1602301SN/A .flags(Stats::total) 1612301SN/A ; 1622307SN/A renameSkidInsts 1632307SN/A .name(name() + ".RENAME:skidInsts") 1642307SN/A .desc("count of insts added to the skid buffer") 1652307SN/A .flags(Stats::total) 1662307SN/A ; 1671062SN/A} 1681062SN/A 1691062SN/Atemplate <class Impl> 1701062SN/Avoid 1712292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1721060SN/A{ 1731060SN/A timeBuffer = tb_ptr; 1741060SN/A 1751060SN/A // Setup wire to read information from time buffer, from IEW stage. 1761060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1771060SN/A 1781060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1791060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1801060SN/A 1811060SN/A // Setup wire to write information to previous stages. 1821060SN/A toDecode = timeBuffer->getWire(0); 1831060SN/A} 1841060SN/A 1851061SN/Atemplate <class Impl> 1861060SN/Avoid 1872292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1881060SN/A{ 1891060SN/A renameQueue = rq_ptr; 1901060SN/A 1911060SN/A // Setup wire to write information to future stages. 1921060SN/A toIEW = renameQueue->getWire(0); 1931060SN/A} 1941060SN/A 1951061SN/Atemplate <class Impl> 1961060SN/Avoid 1972292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1981060SN/A{ 1991060SN/A decodeQueue = dq_ptr; 2001060SN/A 2011060SN/A // Setup wire to get information from decode. 2021060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2031060SN/A} 2041060SN/A 2051061SN/Atemplate <class Impl> 2061060SN/Avoid 2072292SN/ADefaultRename<Impl>::initStage() 2081060SN/A{ 2092329SN/A // Grab the number of free entries directly from the stages. 2102292SN/A for (int tid=0; tid < numThreads; tid++) { 2112292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2122292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2132292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2142292SN/A emptyROB[tid] = true; 2152292SN/A } 2161060SN/A} 2171060SN/A 2182292SN/Atemplate<class Impl> 2192292SN/Avoid 2202980Sgblack@eecs.umich.eduDefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2212292SN/A{ 2222292SN/A activeThreads = at_ptr; 2232292SN/A} 2242292SN/A 2252292SN/A 2261061SN/Atemplate <class Impl> 2271060SN/Avoid 2282292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2291060SN/A{ 2302292SN/A for (int i=0; i<numThreads; i++) { 2312292SN/A renameMap[i] = &rm_ptr[i]; 2321060SN/A } 2331060SN/A} 2341060SN/A 2351061SN/Atemplate <class Impl> 2361060SN/Avoid 2372292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2381060SN/A{ 2392292SN/A freeList = fl_ptr; 2402292SN/A} 2411060SN/A 2422292SN/Atemplate<class Impl> 2432292SN/Avoid 2442292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2452292SN/A{ 2462292SN/A scoreboard = _scoreboard; 2471060SN/A} 2481060SN/A 2491061SN/Atemplate <class Impl> 2502863Sktlim@umich.edubool 2512843Sktlim@umich.eduDefaultRename<Impl>::drain() 2521060SN/A{ 2532348SN/A // Rename is ready to switch out at any time. 2542843Sktlim@umich.edu cpu->signalDrained(); 2552863Sktlim@umich.edu return true; 2562316SN/A} 2571060SN/A 2582316SN/Atemplate <class Impl> 2592316SN/Avoid 2602843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2612316SN/A{ 2622348SN/A // Clear any state, fix up the rename map. 2632307SN/A for (int i = 0; i < numThreads; i++) { 2642980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2652980Sgblack@eecs.umich.edu historyBuffer[i].begin(); 2662307SN/A 2672307SN/A while (!historyBuffer[i].empty()) { 2682307SN/A assert(hb_it != historyBuffer[i].end()); 2692307SN/A 2702307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2712307SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2722307SN/A 2732307SN/A // Tell the rename map to set the architected register to the 2742307SN/A // previous physical register that it was renamed to. 2752307SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2762307SN/A 2772307SN/A // Put the renamed physical register back on the free list. 2782307SN/A freeList->addReg(hb_it->newPhysReg); 2792307SN/A 2802361SN/A // Be sure to mark its register as ready if it's a misc register. 2812361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2822361SN/A scoreboard->setReg(hb_it->newPhysReg); 2832361SN/A } 2842361SN/A 2852307SN/A historyBuffer[i].erase(hb_it++); 2862307SN/A } 2872307SN/A insts[i].clear(); 2882307SN/A skidBuffer[i].clear(); 2891060SN/A } 2901060SN/A} 2911060SN/A 2921061SN/Atemplate <class Impl> 2931060SN/Avoid 2942307SN/ADefaultRename<Impl>::takeOverFrom() 2951060SN/A{ 2962307SN/A _status = Inactive; 2972307SN/A initStage(); 2981060SN/A 2992329SN/A // Reset all state prior to taking over from the other CPU. 3002307SN/A for (int i=0; i< numThreads; i++) { 3012307SN/A renameStatus[i] = Idle; 3021060SN/A 3032307SN/A stalls[i].iew = false; 3042307SN/A stalls[i].commit = false; 3052307SN/A serializeInst[i] = NULL; 3062307SN/A 3072307SN/A instsInProgress[i] = 0; 3082307SN/A 3092307SN/A emptyROB[i] = true; 3102307SN/A 3112307SN/A serializeOnNextInst[i] = false; 3122307SN/A } 3132307SN/A} 3142307SN/A 3152307SN/Atemplate <class Impl> 3162307SN/Avoid 3172935Sksewell@umich.eduDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 3181858SN/A{ 3192292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3201858SN/A 3212292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3222292SN/A // If it still needs to block, the blocking should happen the next 3232292SN/A // cycle and there should be space to hold everything due to the squash. 3242292SN/A if (renameStatus[tid] == Blocked || 3253788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3262292SN/A toDecode->renameUnblock[tid] = 1; 3272698Sktlim@umich.edu 3283788Sgblack@eecs.umich.edu resumeSerialize = false; 3292301SN/A serializeInst[tid] = NULL; 3303788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3313788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3323788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3333788Sgblack@eecs.umich.edu resumeSerialize = true; 3343788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3353788Sgblack@eecs.umich.edu } else { 3363788Sgblack@eecs.umich.edu resumeSerialize = false; 3373788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3383788Sgblack@eecs.umich.edu 3393788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3403788Sgblack@eecs.umich.edu } 3412292SN/A } 3422292SN/A 3432292SN/A // Set the status to Squashing. 3442292SN/A renameStatus[tid] = Squashing; 3452292SN/A 3462329SN/A // Squash any instructions from decode. 3472292SN/A unsigned squashCount = 0; 3482292SN/A 3492292SN/A for (int i=0; i<fromDecode->size; i++) { 3502935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3512935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3522731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3532292SN/A wroteToTimeBuffer = true; 3542292SN/A squashCount++; 3552292SN/A } 3562935Sksewell@umich.edu 3572292SN/A } 3582292SN/A 3592935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3604632Sgblack@eecs.umich.edu // insts in them. 3613093Sksewell@umich.edu insts[tid].clear(); 3622292SN/A 3632292SN/A // Clear the skid buffer in case it has any data in it. 3643093Sksewell@umich.edu skidBuffer[tid].clear(); 3654632Sgblack@eecs.umich.edu 3662935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3672292SN/A} 3682292SN/A 3692292SN/Atemplate <class Impl> 3702292SN/Avoid 3712292SN/ADefaultRename<Impl>::tick() 3722292SN/A{ 3732292SN/A wroteToTimeBuffer = false; 3742292SN/A 3752292SN/A blockThisCycle = false; 3762292SN/A 3772292SN/A bool status_change = false; 3782292SN/A 3792292SN/A toIEWIndex = 0; 3802292SN/A 3812292SN/A sortInsts(); 3822292SN/A 3833867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 3843867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 3852292SN/A 3862292SN/A // Check stall and squash signals. 3873867Sbinkertn@umich.edu while (threads != end) { 3882292SN/A unsigned tid = *threads++; 3892292SN/A 3902292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3912292SN/A 3922292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3932292SN/A 3942292SN/A rename(status_change, tid); 3952292SN/A } 3962292SN/A 3972292SN/A if (status_change) { 3982292SN/A updateStatus(); 3992292SN/A } 4002292SN/A 4012292SN/A if (wroteToTimeBuffer) { 4022292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4032292SN/A cpu->activityThisCycle(); 4042292SN/A } 4052292SN/A 4063867Sbinkertn@umich.edu threads = activeThreads->begin(); 4072292SN/A 4083867Sbinkertn@umich.edu while (threads != end) { 4092292SN/A unsigned tid = *threads++; 4102292SN/A 4112292SN/A // If we committed this cycle then doneSeqNum will be > 0 4122292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4132292SN/A !fromCommit->commitInfo[tid].squash && 4142292SN/A renameStatus[tid] != Squashing) { 4152292SN/A 4162292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4172292SN/A tid); 4182292SN/A } 4192292SN/A } 4202292SN/A 4212292SN/A // @todo: make into updateProgress function 4222292SN/A for (int tid=0; tid < numThreads; tid++) { 4232292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4242292SN/A 4252292SN/A assert(instsInProgress[tid] >=0); 4262292SN/A } 4272292SN/A 4282292SN/A} 4292292SN/A 4302292SN/Atemplate<class Impl> 4312292SN/Avoid 4322292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4332292SN/A{ 4342292SN/A // If status is Running or idle, 4352292SN/A // call renameInsts() 4362292SN/A // If status is Unblocking, 4372292SN/A // buffer any instructions coming from decode 4382292SN/A // continue trying to empty skid buffer 4392292SN/A // check if stall conditions have passed 4402292SN/A 4412292SN/A if (renameStatus[tid] == Blocked) { 4422292SN/A ++renameBlockCycles; 4432292SN/A } else if (renameStatus[tid] == Squashing) { 4442292SN/A ++renameSquashCycles; 4452301SN/A } else if (renameStatus[tid] == SerializeStall) { 4462301SN/A ++renameSerializeStallCycles; 4473788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4483788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4493788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4503788Sgblack@eecs.umich.edu if (resumeSerialize) { 4513788Sgblack@eecs.umich.edu resumeSerialize = false; 4523788Sgblack@eecs.umich.edu block(tid); 4533788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4543788Sgblack@eecs.umich.edu } 4553798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4563798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4573798Sgblack@eecs.umich.edu block(tid); 4583798Sgblack@eecs.umich.edu resumeUnblocking = false; 4593798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4603798Sgblack@eecs.umich.edu } 4612292SN/A } 4622292SN/A 4632292SN/A if (renameStatus[tid] == Running || 4642292SN/A renameStatus[tid] == Idle) { 4652292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4662292SN/A "stage.\n", tid); 4672292SN/A 4682292SN/A renameInsts(tid); 4692292SN/A } else if (renameStatus[tid] == Unblocking) { 4702292SN/A renameInsts(tid); 4712292SN/A 4722292SN/A if (validInsts()) { 4732292SN/A // Add the current inputs to the skid buffer so they can be 4742292SN/A // reprocessed when this stage unblocks. 4752292SN/A skidInsert(tid); 4762292SN/A } 4772292SN/A 4782292SN/A // If we switched over to blocking, then there's a potential for 4792292SN/A // an overall status change. 4802292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4811858SN/A } 4821858SN/A} 4831858SN/A 4841858SN/Atemplate <class Impl> 4851858SN/Avoid 4862292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 4871858SN/A{ 4882292SN/A // Instructions can be either in the skid buffer or the queue of 4892292SN/A // instructions coming from decode, depending on the status. 4902292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4912292SN/A skidBuffer[tid].size() : insts[tid].size(); 4921858SN/A 4932292SN/A // Check the decode queue to see if instructions are available. 4942292SN/A // If there are no available instructions to rename, then do nothing. 4952292SN/A if (insts_available == 0) { 4962292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4972292SN/A tid); 4982292SN/A // Should I change status to idle? 4992292SN/A ++renameIdleCycles; 5002292SN/A return; 5012292SN/A } else if (renameStatus[tid] == Unblocking) { 5022292SN/A ++renameUnblockCycles; 5032292SN/A } else if (renameStatus[tid] == Running) { 5042292SN/A ++renameRunCycles; 5052292SN/A } 5061858SN/A 5072292SN/A DynInstPtr inst; 5082292SN/A 5092292SN/A // Will have to do a different calculation for the number of free 5102292SN/A // entries. 5112292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5122292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5132292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5142292SN/A int min_free_entries = free_rob_entries; 5152292SN/A 5162292SN/A FullSource source = ROB; 5172292SN/A 5182292SN/A if (free_iq_entries < min_free_entries) { 5192292SN/A min_free_entries = free_iq_entries; 5202292SN/A source = IQ; 5212292SN/A } 5222292SN/A 5232292SN/A if (free_lsq_entries < min_free_entries) { 5242292SN/A min_free_entries = free_lsq_entries; 5252292SN/A source = LSQ; 5262292SN/A } 5272292SN/A 5282292SN/A // Check if there's any space left. 5292292SN/A if (min_free_entries <= 0) { 5302292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5312292SN/A "entries.\n" 5322292SN/A "ROB has %i free entries.\n" 5332292SN/A "IQ has %i free entries.\n" 5342292SN/A "LSQ has %i free entries.\n", 5352292SN/A tid, 5362292SN/A free_rob_entries, 5372292SN/A free_iq_entries, 5382292SN/A free_lsq_entries); 5392292SN/A 5402292SN/A blockThisCycle = true; 5412292SN/A 5422292SN/A block(tid); 5432292SN/A 5442292SN/A incrFullStat(source); 5452292SN/A 5462292SN/A return; 5472292SN/A } else if (min_free_entries < insts_available) { 5482292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5492292SN/A "%i insts available, but only %i insts can be " 5502292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5512292SN/A tid, insts_available, min_free_entries); 5522292SN/A 5532292SN/A insts_available = min_free_entries; 5542292SN/A 5552292SN/A blockThisCycle = true; 5562292SN/A 5572292SN/A incrFullStat(source); 5582292SN/A } 5592292SN/A 5602292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5612292SN/A skidBuffer[tid] : insts[tid]; 5622292SN/A 5632292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5642292SN/A "send iew.\n", tid, insts_available); 5652292SN/A 5662292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5672292SN/A "dispatched to IQ last cycle.\n", 5682292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5692292SN/A 5702292SN/A // Handle serializing the next instruction if necessary. 5712292SN/A if (serializeOnNextInst[tid]) { 5722292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5732292SN/A // ROB already empty; no need to serialize. 5742292SN/A serializeOnNextInst[tid] = false; 5752292SN/A } else if (!insts_to_rename.empty()) { 5762292SN/A insts_to_rename.front()->setSerializeBefore(); 5772292SN/A } 5782292SN/A } 5792292SN/A 5802292SN/A int renamed_insts = 0; 5812292SN/A 5822292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5832292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5842292SN/A 5852292SN/A assert(!insts_to_rename.empty()); 5862292SN/A 5872292SN/A inst = insts_to_rename.front(); 5882292SN/A 5892292SN/A insts_to_rename.pop_front(); 5902292SN/A 5912292SN/A if (renameStatus[tid] == Unblocking) { 5922292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 5932292SN/A "skidBuffer\n", 5942292SN/A tid, inst->seqNum, inst->readPC()); 5952292SN/A } 5962292SN/A 5972292SN/A if (inst->isSquashed()) { 5982292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 5992292SN/A "squashed, skipping.\n", 6002935Sksewell@umich.edu tid, inst->seqNum, inst->readPC()); 6012292SN/A 6022292SN/A ++renameSquashedInsts; 6032292SN/A 6042292SN/A // Decrement how many instructions are available. 6052292SN/A --insts_available; 6062292SN/A 6072292SN/A continue; 6082292SN/A } 6092292SN/A 6102292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6112292SN/A "PC %#x.\n", 6122292SN/A tid, inst->seqNum, inst->readPC()); 6132292SN/A 6142292SN/A // Handle serializeAfter/serializeBefore instructions. 6152292SN/A // serializeAfter marks the next instruction as serializeBefore. 6162292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6172292SN/A // is empty. 6182336SN/A 6192336SN/A // In this model, IPR accesses are serialize before 6202336SN/A // instructions, and store conditionals are serialize after 6212336SN/A // instructions. This is mainly due to lack of support for 6222336SN/A // out-of-order operations of either of those classes of 6232336SN/A // instructions. 6242336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6252336SN/A !inst->isSerializeHandled()) { 6262292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6272292SN/A 6282301SN/A if (!inst->isTempSerializeBefore()) { 6292301SN/A renamedSerializing++; 6302292SN/A inst->setSerializeHandled(); 6312301SN/A } else { 6322301SN/A renamedTempSerializing++; 6332301SN/A } 6342292SN/A 6352301SN/A // Change status over to SerializeStall so that other stages know 6362292SN/A // what this is blocked on. 6372301SN/A renameStatus[tid] = SerializeStall; 6382292SN/A 6392301SN/A serializeInst[tid] = inst; 6402292SN/A 6412292SN/A blockThisCycle = true; 6422292SN/A 6432292SN/A break; 6442336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6452336SN/A !inst->isSerializeHandled()) { 6462292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6472292SN/A 6482307SN/A renamedSerializing++; 6492307SN/A 6502292SN/A inst->setSerializeHandled(); 6512292SN/A 6522292SN/A serializeAfter(insts_to_rename, tid); 6532292SN/A } 6542292SN/A 6552292SN/A // Check here to make sure there are enough destination registers 6562292SN/A // to rename to. Otherwise block. 6572292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6582292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6592292SN/A "physical registers to rename to.\n"); 6602292SN/A blockThisCycle = true; 6614345Sktlim@umich.edu insts_to_rename.push_front(inst); 6622292SN/A ++renameFullRegistersEvents; 6632292SN/A 6642292SN/A break; 6652292SN/A } 6662292SN/A 6672292SN/A renameSrcRegs(inst, inst->threadNumber); 6682292SN/A 6692292SN/A renameDestRegs(inst, inst->threadNumber); 6702292SN/A 6712292SN/A ++renamed_insts; 6722292SN/A 6732292SN/A // Put instruction in rename queue. 6742292SN/A toIEW->insts[toIEWIndex] = inst; 6752292SN/A ++(toIEW->size); 6762292SN/A 6772292SN/A // Increment which instruction we're on. 6782292SN/A ++toIEWIndex; 6792292SN/A 6802292SN/A // Decrement how many instructions are available. 6812292SN/A --insts_available; 6822292SN/A } 6832292SN/A 6842292SN/A instsInProgress[tid] += renamed_insts; 6852307SN/A renameRenamedInsts += renamed_insts; 6862292SN/A 6872292SN/A // If we wrote to the time buffer, record this. 6882292SN/A if (toIEWIndex) { 6892292SN/A wroteToTimeBuffer = true; 6902292SN/A } 6912292SN/A 6922292SN/A // Check if there's any instructions left that haven't yet been renamed. 6932292SN/A // If so then block. 6942292SN/A if (insts_available) { 6952292SN/A blockThisCycle = true; 6962292SN/A } 6972292SN/A 6982292SN/A if (blockThisCycle) { 6992292SN/A block(tid); 7002292SN/A toDecode->renameUnblock[tid] = false; 7012292SN/A } 7022292SN/A} 7032292SN/A 7042292SN/Atemplate<class Impl> 7052292SN/Avoid 7062292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 7072292SN/A{ 7082292SN/A DynInstPtr inst = NULL; 7092292SN/A 7102292SN/A while (!insts[tid].empty()) { 7112292SN/A inst = insts[tid].front(); 7122292SN/A 7132292SN/A insts[tid].pop_front(); 7142292SN/A 7152292SN/A assert(tid == inst->threadNumber); 7162292SN/A 7172292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 7182292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 7192292SN/A 7202307SN/A ++renameSkidInsts; 7212307SN/A 7222292SN/A skidBuffer[tid].push_back(inst); 7232292SN/A } 7242292SN/A 7252292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7263798Sgblack@eecs.umich.edu { 7273798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7283798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7293798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7303798Sgblack@eecs.umich.edu { 7313798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7323798Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->readPC()), 7333798Sgblack@eecs.umich.edu (*it)->seqNum); 7343798Sgblack@eecs.umich.edu } 7352292SN/A panic("Skidbuffer Exceeded Max Size"); 7363798Sgblack@eecs.umich.edu } 7372292SN/A} 7382292SN/A 7392292SN/Atemplate <class Impl> 7402292SN/Avoid 7412292SN/ADefaultRename<Impl>::sortInsts() 7422292SN/A{ 7432292SN/A int insts_from_decode = fromDecode->size; 7442329SN/A#ifdef DEBUG 7452292SN/A for (int i=0; i < numThreads; i++) 7462292SN/A assert(insts[i].empty()); 7472329SN/A#endif 7482292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7492292SN/A DynInstPtr inst = fromDecode->insts[i]; 7502292SN/A insts[inst->threadNumber].push_back(inst); 7512292SN/A } 7522292SN/A} 7532292SN/A 7542292SN/Atemplate<class Impl> 7552292SN/Abool 7562292SN/ADefaultRename<Impl>::skidsEmpty() 7572292SN/A{ 7583867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7593867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7602292SN/A 7613867Sbinkertn@umich.edu while (threads != end) { 7623867Sbinkertn@umich.edu unsigned tid = *threads++; 7633867Sbinkertn@umich.edu 7643867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7652292SN/A return false; 7662292SN/A } 7672292SN/A 7682292SN/A return true; 7692292SN/A} 7702292SN/A 7712292SN/Atemplate<class Impl> 7722292SN/Avoid 7732292SN/ADefaultRename<Impl>::updateStatus() 7742292SN/A{ 7752292SN/A bool any_unblocking = false; 7762292SN/A 7773867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7783867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7792292SN/A 7803867Sbinkertn@umich.edu while (threads != end) { 7812292SN/A unsigned tid = *threads++; 7822292SN/A 7832292SN/A if (renameStatus[tid] == Unblocking) { 7842292SN/A any_unblocking = true; 7852292SN/A break; 7862292SN/A } 7872292SN/A } 7882292SN/A 7892292SN/A // Rename will have activity if it's unblocking. 7902292SN/A if (any_unblocking) { 7912292SN/A if (_status == Inactive) { 7922292SN/A _status = Active; 7932292SN/A 7942292SN/A DPRINTF(Activity, "Activating stage.\n"); 7952292SN/A 7962733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7972292SN/A } 7982292SN/A } else { 7992292SN/A // If it's not unblocking, then rename will not have any internal 8002292SN/A // activity. Switch it to inactive. 8012292SN/A if (_status == Active) { 8022292SN/A _status = Inactive; 8032292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8042292SN/A 8052733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8062292SN/A } 8072292SN/A } 8082292SN/A} 8092292SN/A 8102292SN/Atemplate <class Impl> 8112292SN/Abool 8122292SN/ADefaultRename<Impl>::block(unsigned tid) 8132292SN/A{ 8142292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8152292SN/A 8162292SN/A // Add the current inputs onto the skid buffer, so they can be 8172292SN/A // reprocessed when this stage unblocks. 8182292SN/A skidInsert(tid); 8192292SN/A 8202292SN/A // Only signal backwards to block if the previous stages do not think 8212292SN/A // rename is already blocked. 8222292SN/A if (renameStatus[tid] != Blocked) { 8233798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8243798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8253798Sgblack@eecs.umich.edu // stages to block. 8263798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8272292SN/A toDecode->renameBlock[tid] = true; 8282292SN/A toDecode->renameUnblock[tid] = false; 8292292SN/A wroteToTimeBuffer = true; 8302292SN/A } 8312292SN/A 8322329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8332329SN/A // it would not know to complete the serialize stall. 8342301SN/A if (renameStatus[tid] != SerializeStall) { 8352292SN/A // Set status to Blocked. 8362292SN/A renameStatus[tid] = Blocked; 8372292SN/A return true; 8382292SN/A } 8392292SN/A } 8402292SN/A 8412292SN/A return false; 8422292SN/A} 8432292SN/A 8442292SN/Atemplate <class Impl> 8452292SN/Abool 8462292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8472292SN/A{ 8482292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8492292SN/A 8502292SN/A // Rename is done unblocking if the skid buffer is empty. 8512301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8522292SN/A 8532292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8542292SN/A 8552292SN/A toDecode->renameUnblock[tid] = true; 8562292SN/A wroteToTimeBuffer = true; 8572292SN/A 8582292SN/A renameStatus[tid] = Running; 8592292SN/A return true; 8602292SN/A } 8612292SN/A 8622292SN/A return false; 8632292SN/A} 8642292SN/A 8652292SN/Atemplate <class Impl> 8662292SN/Avoid 8672935Sksewell@umich.eduDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 8682292SN/A{ 8692980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8702980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8712292SN/A 8721060SN/A // After a syscall squashes everything, the history buffer may be empty 8731060SN/A // but the ROB may still be squashing instructions. 8742292SN/A if (historyBuffer[tid].empty()) { 8751060SN/A return; 8761060SN/A } 8771060SN/A 8781060SN/A // Go through the most recent instructions, undoing the mappings 8791060SN/A // they did and freeing up the registers. 8802292SN/A while (!historyBuffer[tid].empty() && 8812292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8822292SN/A assert(hb_it != historyBuffer[tid].end()); 8831062SN/A 8842292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8852292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8861060SN/A 8872292SN/A // Tell the rename map to set the architected register to the 8882292SN/A // previous physical register that it was renamed to. 8892292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8901060SN/A 8912292SN/A // Put the renamed physical register back on the free list. 8922292SN/A freeList->addReg(hb_it->newPhysReg); 8931062SN/A 8942367SN/A // Be sure to mark its register as ready if it's a misc register. 8952367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 8962367SN/A scoreboard->setReg(hb_it->newPhysReg); 8972367SN/A } 8982367SN/A 8992292SN/A historyBuffer[tid].erase(hb_it++); 9001061SN/A 9011062SN/A ++renameUndoneMaps; 9021060SN/A } 9031060SN/A} 9041060SN/A 9051060SN/Atemplate<class Impl> 9061060SN/Avoid 9072292SN/ADefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 9081060SN/A{ 9092292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9102292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9112292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9122292SN/A 9132980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9142980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9151060SN/A 9161061SN/A --hb_it; 9171060SN/A 9182292SN/A if (historyBuffer[tid].empty()) { 9192292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9202292SN/A return; 9212292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9222292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9232292SN/A "that a syscall happened recently.\n", tid); 9241060SN/A return; 9251060SN/A } 9261060SN/A 9272292SN/A // Commit all the renames up until (and including) the committed sequence 9282292SN/A // number. Some or even all of the committed instructions may not have 9292292SN/A // rename histories if they did not have destination registers that were 9302292SN/A // renamed. 9312292SN/A while (!historyBuffer[tid].empty() && 9322292SN/A hb_it != historyBuffer[tid].end() && 9332292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9341060SN/A 9352329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9362329SN/A "[sn:%lli].\n", 9372292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9381061SN/A 9392292SN/A freeList->addReg((*hb_it).prevPhysReg); 9402292SN/A ++renameCommittedMaps; 9411061SN/A 9422292SN/A historyBuffer[tid].erase(hb_it--); 9431060SN/A } 9441060SN/A} 9451060SN/A 9461061SN/Atemplate <class Impl> 9471061SN/Ainline void 9482292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9491061SN/A{ 9502292SN/A assert(renameMap[tid] != 0); 9512292SN/A 9521061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9531061SN/A 9541061SN/A // Get the architectual register numbers from the source and 9551061SN/A // destination operands, and redirect them to the right register. 9561061SN/A // Will need to mark dependencies though. 9572292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9581061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9593773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9603773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9613773Sgblack@eecs.umich.edu flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 9623773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 9635082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9645082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9655082Sgblack@eecs.umich.edu flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); 9665082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9674352Sgblack@eecs.umich.edu } else { 9684352Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 9694636Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); 9703773Sgblack@eecs.umich.edu } 9714352Sgblack@eecs.umich.edu 9723773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 9731061SN/A 9741061SN/A // Look up the source registers to get the phys. register they've 9751061SN/A // been renamed to, and set the sources to those registers. 9763773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 9771061SN/A 9782292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9793773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 9802292SN/A (int)renamed_reg); 9811061SN/A 9821061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9831061SN/A 9842292SN/A // See if the register is ready or not. 9852292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9864636Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg); 9871061SN/A 9881061SN/A inst->markSrcRegReady(src_idx); 9894636Sgblack@eecs.umich.edu } else { 9904636Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg); 9911061SN/A } 9921062SN/A 9931062SN/A ++renameRenameLookups; 9941061SN/A } 9951061SN/A} 9961061SN/A 9971061SN/Atemplate <class Impl> 9981061SN/Ainline void 9992292SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 10001061SN/A{ 10012292SN/A typename RenameMap::RenameInfo rename_result; 10021061SN/A 10031061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10041061SN/A 10052292SN/A // Rename the destination registers. 10062292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10072292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10083773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10093773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10104352Sgblack@eecs.umich.edu // Integer registers are flattened. 10113773Sgblack@eecs.umich.edu flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 10123773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 10134352Sgblack@eecs.umich.edu } else { 10144352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10154352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10164352Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 10174636Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg); 10183773Sgblack@eecs.umich.edu } 10193773Sgblack@eecs.umich.edu 10203773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10211061SN/A 10222292SN/A // Get the physical register that the destination will be 10232292SN/A // renamed to. 10243773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10251061SN/A 10262292SN/A //Mark Scoreboard entry as not ready 10272292SN/A scoreboard->unsetReg(rename_result.first); 10281062SN/A 10292292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10303773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10312292SN/A (int)rename_result.first); 10321062SN/A 10332292SN/A // Record the rename information so that a history can be kept. 10343773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10352292SN/A rename_result.first, 10362292SN/A rename_result.second); 10371062SN/A 10382292SN/A historyBuffer[tid].push_front(hb_entry); 10391062SN/A 10402935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10412935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10422935Sksewell@umich.edu historyBuffer[tid].size(), 10432292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10441062SN/A 10452292SN/A // Tell the instruction to rename the appropriate destination 10462292SN/A // register (dest_idx) to the new physical register 10472292SN/A // (rename_result.first), and record the previous physical 10482292SN/A // register that the same logical register was renamed to 10492292SN/A // (rename_result.second). 10502292SN/A inst->renameDestReg(dest_idx, 10512292SN/A rename_result.first, 10522292SN/A rename_result.second); 10531062SN/A 10542292SN/A ++renameRenamedOperands; 10551061SN/A } 10561061SN/A} 10571061SN/A 10581061SN/Atemplate <class Impl> 10591061SN/Ainline int 10602292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 10611061SN/A{ 10622292SN/A int num_free = freeEntries[tid].robEntries - 10632292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10642292SN/A 10652292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10662292SN/A 10672292SN/A return num_free; 10681061SN/A} 10691061SN/A 10701061SN/Atemplate <class Impl> 10711061SN/Ainline int 10722292SN/ADefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 10731061SN/A{ 10742292SN/A int num_free = freeEntries[tid].iqEntries - 10752292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10762292SN/A 10772292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10782292SN/A 10792292SN/A return num_free; 10802292SN/A} 10812292SN/A 10822292SN/Atemplate <class Impl> 10832292SN/Ainline int 10842292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 10852292SN/A{ 10862292SN/A int num_free = freeEntries[tid].lsqEntries - 10872292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10882292SN/A 10892292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 10902292SN/A 10912292SN/A return num_free; 10922292SN/A} 10932292SN/A 10942292SN/Atemplate <class Impl> 10952292SN/Aunsigned 10962292SN/ADefaultRename<Impl>::validInsts() 10972292SN/A{ 10982292SN/A unsigned inst_count = 0; 10992292SN/A 11002292SN/A for (int i=0; i<fromDecode->size; i++) { 11012731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11022292SN/A inst_count++; 11032292SN/A } 11042292SN/A 11052292SN/A return inst_count; 11062292SN/A} 11072292SN/A 11082292SN/Atemplate <class Impl> 11092292SN/Avoid 11102292SN/ADefaultRename<Impl>::readStallSignals(unsigned tid) 11112292SN/A{ 11122292SN/A if (fromIEW->iewBlock[tid]) { 11132292SN/A stalls[tid].iew = true; 11142292SN/A } 11152292SN/A 11162292SN/A if (fromIEW->iewUnblock[tid]) { 11172292SN/A assert(stalls[tid].iew); 11182292SN/A stalls[tid].iew = false; 11192292SN/A } 11202292SN/A 11212292SN/A if (fromCommit->commitBlock[tid]) { 11222292SN/A stalls[tid].commit = true; 11232292SN/A } 11242292SN/A 11252292SN/A if (fromCommit->commitUnblock[tid]) { 11262292SN/A assert(stalls[tid].commit); 11272292SN/A stalls[tid].commit = false; 11282292SN/A } 11292292SN/A} 11302292SN/A 11312292SN/Atemplate <class Impl> 11322292SN/Abool 11332292SN/ADefaultRename<Impl>::checkStall(unsigned tid) 11342292SN/A{ 11352292SN/A bool ret_val = false; 11362292SN/A 11372292SN/A if (stalls[tid].iew) { 11382292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11392292SN/A ret_val = true; 11402292SN/A } else if (stalls[tid].commit) { 11412292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11422292SN/A ret_val = true; 11432292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11442292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11452292SN/A ret_val = true; 11462292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11472292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11482292SN/A ret_val = true; 11492292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11502292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11512292SN/A ret_val = true; 11522292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11532292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11542292SN/A ret_val = true; 11552301SN/A } else if (renameStatus[tid] == SerializeStall && 11562292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11572301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11582292SN/A "empty.\n", 11592292SN/A tid); 11602292SN/A ret_val = true; 11612292SN/A } 11622292SN/A 11632292SN/A return ret_val; 11642292SN/A} 11652292SN/A 11662292SN/Atemplate <class Impl> 11672292SN/Avoid 11682292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 11692292SN/A{ 11702292SN/A bool updated = false; 11712292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 11722292SN/A freeEntries[tid].iqEntries = 11732292SN/A fromIEW->iewInfo[tid].freeIQEntries; 11742292SN/A updated = true; 11752292SN/A } 11762292SN/A 11772292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11782292SN/A freeEntries[tid].lsqEntries = 11792292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 11802292SN/A updated = true; 11812292SN/A } 11822292SN/A 11832292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11842292SN/A freeEntries[tid].robEntries = 11852292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11862292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11872292SN/A updated = true; 11882292SN/A } 11892292SN/A 11902292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11912292SN/A tid, 11922292SN/A freeEntries[tid].iqEntries, 11932292SN/A freeEntries[tid].robEntries, 11942292SN/A freeEntries[tid].lsqEntries); 11952292SN/A 11962292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 11972292SN/A tid, instsInProgress[tid]); 11982292SN/A} 11992292SN/A 12002292SN/Atemplate <class Impl> 12012292SN/Abool 12022292SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 12032292SN/A{ 12042292SN/A // Check if there's a squash signal, squash if there is 12052292SN/A // Check stall signals, block if necessary. 12062292SN/A // If status was blocked 12072292SN/A // check if stall conditions have passed 12082292SN/A // if so then go to unblocking 12092292SN/A // If status was Squashing 12102292SN/A // check if squashing is not high. Switch to running this cycle. 12112301SN/A // If status was serialize stall 12122292SN/A // check if ROB is empty and no insts are in flight to the ROB 12132292SN/A 12142292SN/A readFreeEntries(tid); 12152292SN/A readStallSignals(tid); 12162292SN/A 12172292SN/A if (fromCommit->commitInfo[tid].squash) { 12182292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12192292SN/A "commit.\n", tid); 12202292SN/A 12214632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12222292SN/A 12232292SN/A return true; 12242292SN/A } 12252292SN/A 12262292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12272292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12282292SN/A 12292292SN/A renameStatus[tid] = Squashing; 12302292SN/A 12312292SN/A return true; 12322292SN/A } 12332292SN/A 12342292SN/A if (checkStall(tid)) { 12352292SN/A return block(tid); 12362292SN/A } 12372292SN/A 12382292SN/A if (renameStatus[tid] == Blocked) { 12392292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12402292SN/A tid); 12412292SN/A 12422292SN/A renameStatus[tid] = Unblocking; 12432292SN/A 12442292SN/A unblock(tid); 12452292SN/A 12462292SN/A return true; 12472292SN/A } 12482292SN/A 12492292SN/A if (renameStatus[tid] == Squashing) { 12502292SN/A // Switch status to running if rename isn't being told to block or 12512292SN/A // squash this cycle. 12523798Sgblack@eecs.umich.edu if (resumeSerialize) { 12533798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12543798Sgblack@eecs.umich.edu tid); 12552292SN/A 12563798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12573798Sgblack@eecs.umich.edu return true; 12583798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12593798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12603798Sgblack@eecs.umich.edu tid); 12613798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12623798Sgblack@eecs.umich.edu return true; 12633798Sgblack@eecs.umich.edu } else { 12643788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12653788Sgblack@eecs.umich.edu tid); 12662292SN/A 12673788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 12683788Sgblack@eecs.umich.edu return false; 12693788Sgblack@eecs.umich.edu } 12702292SN/A } 12712292SN/A 12722301SN/A if (renameStatus[tid] == SerializeStall) { 12732292SN/A // Stall ends once the ROB is free. 12742301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 12752292SN/A "unblocking.\n", tid); 12762292SN/A 12772301SN/A DynInstPtr serial_inst = serializeInst[tid]; 12782292SN/A 12792292SN/A renameStatus[tid] = Unblocking; 12802292SN/A 12812292SN/A unblock(tid); 12822292SN/A 12832292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 12842292SN/A "PC %#x.\n", 12852301SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 12862292SN/A 12872292SN/A // Put instruction into queue here. 12882301SN/A serial_inst->clearSerializeBefore(); 12892292SN/A 12902292SN/A if (!skidBuffer[tid].empty()) { 12912301SN/A skidBuffer[tid].push_front(serial_inst); 12922292SN/A } else { 12932301SN/A insts[tid].push_front(serial_inst); 12942292SN/A } 12952292SN/A 12962292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 12972703Sktlim@umich.edu " Adding to front of list.\n", tid); 12982292SN/A 12992301SN/A serializeInst[tid] = NULL; 13002292SN/A 13012292SN/A return true; 13022292SN/A } 13032292SN/A 13042292SN/A // If we've reached this point, we have not gotten any signals that 13052292SN/A // cause rename to change its status. Rename remains the same as before. 13062292SN/A return false; 13071061SN/A} 13081061SN/A 13091060SN/Atemplate<class Impl> 13101060SN/Avoid 13112292SN/ADefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 13122292SN/A unsigned tid) 13131060SN/A{ 13142292SN/A if (inst_list.empty()) { 13152292SN/A // Mark a bit to say that I must serialize on the next instruction. 13162292SN/A serializeOnNextInst[tid] = true; 13171060SN/A return; 13181060SN/A } 13191060SN/A 13202292SN/A // Set the next instruction as serializing. 13212292SN/A inst_list.front()->setSerializeBefore(); 13222292SN/A} 13232292SN/A 13242292SN/Atemplate <class Impl> 13252292SN/Ainline void 13262292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13272292SN/A{ 13282292SN/A switch (source) { 13292292SN/A case ROB: 13302292SN/A ++renameROBFullEvents; 13312292SN/A break; 13322292SN/A case IQ: 13332292SN/A ++renameIQFullEvents; 13342292SN/A break; 13352292SN/A case LSQ: 13362292SN/A ++renameLSQFullEvents; 13372292SN/A break; 13382292SN/A default: 13392292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13402292SN/A break; 13411060SN/A } 13422292SN/A} 13431060SN/A 13442292SN/Atemplate <class Impl> 13452292SN/Avoid 13462292SN/ADefaultRename<Impl>::dumpHistory() 13472292SN/A{ 13482980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13491060SN/A 13502292SN/A for (int i = 0; i < numThreads; i++) { 13511060SN/A 13522292SN/A buf_it = historyBuffer[i].begin(); 13531060SN/A 13542292SN/A while (buf_it != historyBuffer[i].end()) { 13552292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13562292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13572292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13581060SN/A 13592292SN/A buf_it++; 13601062SN/A } 13611060SN/A } 13621060SN/A} 1363