rename_impl.hh revision 5082
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292935Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321060SN/A#include <list> 331060SN/A 343773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 353773Sgblack@eecs.umich.edu#include "arch/regfile.hh" 361858SN/A#include "config/full_system.hh" 371717SN/A#include "cpu/o3/rename.hh" 381060SN/A 391061SN/Atemplate <class Impl> 404329Sktlim@umich.eduDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params) 414329Sktlim@umich.edu : cpu(_cpu), 424329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 432292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 442292SN/A commitToRenameDelay(params->commitToRenameDelay), 452292SN/A renameWidth(params->renameWidth), 462292SN/A commitWidth(params->commitWidth), 473788Sgblack@eecs.umich.edu resumeSerialize(false), 483798Sgblack@eecs.umich.edu resumeUnblocking(false), 492361SN/A numThreads(params->numberOfThreads), 502361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 511060SN/A{ 522292SN/A _status = Inactive; 532292SN/A 542292SN/A for (int i=0; i< numThreads; i++) { 552292SN/A renameStatus[i] = Idle; 562292SN/A 572292SN/A freeEntries[i].iqEntries = 0; 582292SN/A freeEntries[i].lsqEntries = 0; 592292SN/A freeEntries[i].robEntries = 0; 602292SN/A 612292SN/A stalls[i].iew = false; 622292SN/A stalls[i].commit = false; 632301SN/A serializeInst[i] = NULL; 642292SN/A 652292SN/A instsInProgress[i] = 0; 662292SN/A 672292SN/A emptyROB[i] = true; 682292SN/A 692292SN/A serializeOnNextInst[i] = false; 702292SN/A } 712292SN/A 722292SN/A // @todo: Make into a parameter. 732292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 742292SN/A} 752292SN/A 762292SN/Atemplate <class Impl> 772292SN/Astd::string 782292SN/ADefaultRename<Impl>::name() const 792292SN/A{ 802292SN/A return cpu->name() + ".rename"; 811060SN/A} 821060SN/A 831061SN/Atemplate <class Impl> 841060SN/Avoid 852292SN/ADefaultRename<Impl>::regStats() 861062SN/A{ 871062SN/A renameSquashCycles 882301SN/A .name(name() + ".RENAME:SquashCycles") 891062SN/A .desc("Number of cycles rename is squashing") 901062SN/A .prereq(renameSquashCycles); 911062SN/A renameIdleCycles 922301SN/A .name(name() + ".RENAME:IdleCycles") 931062SN/A .desc("Number of cycles rename is idle") 941062SN/A .prereq(renameIdleCycles); 951062SN/A renameBlockCycles 962301SN/A .name(name() + ".RENAME:BlockCycles") 971062SN/A .desc("Number of cycles rename is blocking") 981062SN/A .prereq(renameBlockCycles); 992301SN/A renameSerializeStallCycles 1002301SN/A .name(name() + ".RENAME:serializeStallCycles") 1012301SN/A .desc("count of cycles rename stalled for serializing inst") 1022301SN/A .flags(Stats::total); 1032292SN/A renameRunCycles 1042301SN/A .name(name() + ".RENAME:RunCycles") 1052292SN/A .desc("Number of cycles rename is running") 1062292SN/A .prereq(renameIdleCycles); 1071062SN/A renameUnblockCycles 1082301SN/A .name(name() + ".RENAME:UnblockCycles") 1091062SN/A .desc("Number of cycles rename is unblocking") 1101062SN/A .prereq(renameUnblockCycles); 1111062SN/A renameRenamedInsts 1122301SN/A .name(name() + ".RENAME:RenamedInsts") 1131062SN/A .desc("Number of instructions processed by rename") 1141062SN/A .prereq(renameRenamedInsts); 1151062SN/A renameSquashedInsts 1162301SN/A .name(name() + ".RENAME:SquashedInsts") 1171062SN/A .desc("Number of squashed instructions processed by rename") 1181062SN/A .prereq(renameSquashedInsts); 1191062SN/A renameROBFullEvents 1202301SN/A .name(name() + ".RENAME:ROBFullEvents") 1212292SN/A .desc("Number of times rename has blocked due to ROB full") 1221062SN/A .prereq(renameROBFullEvents); 1231062SN/A renameIQFullEvents 1242301SN/A .name(name() + ".RENAME:IQFullEvents") 1252292SN/A .desc("Number of times rename has blocked due to IQ full") 1261062SN/A .prereq(renameIQFullEvents); 1272292SN/A renameLSQFullEvents 1282301SN/A .name(name() + ".RENAME:LSQFullEvents") 1292292SN/A .desc("Number of times rename has blocked due to LSQ full") 1302292SN/A .prereq(renameLSQFullEvents); 1311062SN/A renameFullRegistersEvents 1322301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1331062SN/A .desc("Number of times there has been no free registers") 1341062SN/A .prereq(renameFullRegistersEvents); 1351062SN/A renameRenamedOperands 1362301SN/A .name(name() + ".RENAME:RenamedOperands") 1371062SN/A .desc("Number of destination operands rename has renamed") 1381062SN/A .prereq(renameRenamedOperands); 1391062SN/A renameRenameLookups 1402301SN/A .name(name() + ".RENAME:RenameLookups") 1411062SN/A .desc("Number of register rename lookups that rename has made") 1421062SN/A .prereq(renameRenameLookups); 1431062SN/A renameCommittedMaps 1442301SN/A .name(name() + ".RENAME:CommittedMaps") 1451062SN/A .desc("Number of HB maps that are committed") 1461062SN/A .prereq(renameCommittedMaps); 1471062SN/A renameUndoneMaps 1482301SN/A .name(name() + ".RENAME:UndoneMaps") 1491062SN/A .desc("Number of HB maps that are undone due to squashing") 1501062SN/A .prereq(renameUndoneMaps); 1512301SN/A renamedSerializing 1522301SN/A .name(name() + ".RENAME:serializingInsts") 1532301SN/A .desc("count of serializing insts renamed") 1542301SN/A .flags(Stats::total) 1552301SN/A ; 1562301SN/A renamedTempSerializing 1572301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1582301SN/A .desc("count of temporary serializing insts renamed") 1592301SN/A .flags(Stats::total) 1602301SN/A ; 1612307SN/A renameSkidInsts 1622307SN/A .name(name() + ".RENAME:skidInsts") 1632307SN/A .desc("count of insts added to the skid buffer") 1642307SN/A .flags(Stats::total) 1652307SN/A ; 1661062SN/A} 1671062SN/A 1681062SN/Atemplate <class Impl> 1691062SN/Avoid 1702292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1711060SN/A{ 1721060SN/A timeBuffer = tb_ptr; 1731060SN/A 1741060SN/A // Setup wire to read information from time buffer, from IEW stage. 1751060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1761060SN/A 1771060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1781060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1791060SN/A 1801060SN/A // Setup wire to write information to previous stages. 1811060SN/A toDecode = timeBuffer->getWire(0); 1821060SN/A} 1831060SN/A 1841061SN/Atemplate <class Impl> 1851060SN/Avoid 1862292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1871060SN/A{ 1881060SN/A renameQueue = rq_ptr; 1891060SN/A 1901060SN/A // Setup wire to write information to future stages. 1911060SN/A toIEW = renameQueue->getWire(0); 1921060SN/A} 1931060SN/A 1941061SN/Atemplate <class Impl> 1951060SN/Avoid 1962292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1971060SN/A{ 1981060SN/A decodeQueue = dq_ptr; 1991060SN/A 2001060SN/A // Setup wire to get information from decode. 2011060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2021060SN/A} 2031060SN/A 2041061SN/Atemplate <class Impl> 2051060SN/Avoid 2062292SN/ADefaultRename<Impl>::initStage() 2071060SN/A{ 2082329SN/A // Grab the number of free entries directly from the stages. 2092292SN/A for (int tid=0; tid < numThreads; tid++) { 2102292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2112292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2122292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2132292SN/A emptyROB[tid] = true; 2142292SN/A } 2151060SN/A} 2161060SN/A 2172292SN/Atemplate<class Impl> 2182292SN/Avoid 2192980Sgblack@eecs.umich.eduDefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2202292SN/A{ 2212292SN/A activeThreads = at_ptr; 2222292SN/A} 2232292SN/A 2242292SN/A 2251061SN/Atemplate <class Impl> 2261060SN/Avoid 2272292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2281060SN/A{ 2292292SN/A for (int i=0; i<numThreads; i++) { 2302292SN/A renameMap[i] = &rm_ptr[i]; 2311060SN/A } 2321060SN/A} 2331060SN/A 2341061SN/Atemplate <class Impl> 2351060SN/Avoid 2362292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2371060SN/A{ 2382292SN/A freeList = fl_ptr; 2392292SN/A} 2401060SN/A 2412292SN/Atemplate<class Impl> 2422292SN/Avoid 2432292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2442292SN/A{ 2452292SN/A scoreboard = _scoreboard; 2461060SN/A} 2471060SN/A 2481061SN/Atemplate <class Impl> 2492863Sktlim@umich.edubool 2502843Sktlim@umich.eduDefaultRename<Impl>::drain() 2511060SN/A{ 2522348SN/A // Rename is ready to switch out at any time. 2532843Sktlim@umich.edu cpu->signalDrained(); 2542863Sktlim@umich.edu return true; 2552316SN/A} 2561060SN/A 2572316SN/Atemplate <class Impl> 2582316SN/Avoid 2592843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2602316SN/A{ 2612348SN/A // Clear any state, fix up the rename map. 2622307SN/A for (int i = 0; i < numThreads; i++) { 2632980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2642980Sgblack@eecs.umich.edu historyBuffer[i].begin(); 2652307SN/A 2662307SN/A while (!historyBuffer[i].empty()) { 2672307SN/A assert(hb_it != historyBuffer[i].end()); 2682307SN/A 2692307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2702307SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2712307SN/A 2722307SN/A // Tell the rename map to set the architected register to the 2732307SN/A // previous physical register that it was renamed to. 2742307SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2752307SN/A 2762307SN/A // Put the renamed physical register back on the free list. 2772307SN/A freeList->addReg(hb_it->newPhysReg); 2782307SN/A 2792361SN/A // Be sure to mark its register as ready if it's a misc register. 2802361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2812361SN/A scoreboard->setReg(hb_it->newPhysReg); 2822361SN/A } 2832361SN/A 2842307SN/A historyBuffer[i].erase(hb_it++); 2852307SN/A } 2862307SN/A insts[i].clear(); 2872307SN/A skidBuffer[i].clear(); 2881060SN/A } 2891060SN/A} 2901060SN/A 2911061SN/Atemplate <class Impl> 2921060SN/Avoid 2932307SN/ADefaultRename<Impl>::takeOverFrom() 2941060SN/A{ 2952307SN/A _status = Inactive; 2962307SN/A initStage(); 2971060SN/A 2982329SN/A // Reset all state prior to taking over from the other CPU. 2992307SN/A for (int i=0; i< numThreads; i++) { 3002307SN/A renameStatus[i] = Idle; 3011060SN/A 3022307SN/A stalls[i].iew = false; 3032307SN/A stalls[i].commit = false; 3042307SN/A serializeInst[i] = NULL; 3052307SN/A 3062307SN/A instsInProgress[i] = 0; 3072307SN/A 3082307SN/A emptyROB[i] = true; 3092307SN/A 3102307SN/A serializeOnNextInst[i] = false; 3112307SN/A } 3122307SN/A} 3132307SN/A 3142307SN/Atemplate <class Impl> 3152307SN/Avoid 3162935Sksewell@umich.eduDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 3171858SN/A{ 3182292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3191858SN/A 3202292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3212292SN/A // If it still needs to block, the blocking should happen the next 3222292SN/A // cycle and there should be space to hold everything due to the squash. 3232292SN/A if (renameStatus[tid] == Blocked || 3243788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3252292SN/A toDecode->renameUnblock[tid] = 1; 3262698Sktlim@umich.edu 3273788Sgblack@eecs.umich.edu resumeSerialize = false; 3282301SN/A serializeInst[tid] = NULL; 3293788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3303788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3313788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3323788Sgblack@eecs.umich.edu resumeSerialize = true; 3333788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3343788Sgblack@eecs.umich.edu } else { 3353788Sgblack@eecs.umich.edu resumeSerialize = false; 3363788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3373788Sgblack@eecs.umich.edu 3383788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3393788Sgblack@eecs.umich.edu } 3402292SN/A } 3412292SN/A 3422292SN/A // Set the status to Squashing. 3432292SN/A renameStatus[tid] = Squashing; 3442292SN/A 3452329SN/A // Squash any instructions from decode. 3462292SN/A unsigned squashCount = 0; 3472292SN/A 3482292SN/A for (int i=0; i<fromDecode->size; i++) { 3492935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3502935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3512731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3522292SN/A wroteToTimeBuffer = true; 3532292SN/A squashCount++; 3542292SN/A } 3552935Sksewell@umich.edu 3562292SN/A } 3572292SN/A 3582935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3594632Sgblack@eecs.umich.edu // insts in them. 3603093Sksewell@umich.edu insts[tid].clear(); 3612292SN/A 3622292SN/A // Clear the skid buffer in case it has any data in it. 3633093Sksewell@umich.edu skidBuffer[tid].clear(); 3644632Sgblack@eecs.umich.edu 3652935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3662292SN/A} 3672292SN/A 3682292SN/Atemplate <class Impl> 3692292SN/Avoid 3702292SN/ADefaultRename<Impl>::tick() 3712292SN/A{ 3722292SN/A wroteToTimeBuffer = false; 3732292SN/A 3742292SN/A blockThisCycle = false; 3752292SN/A 3762292SN/A bool status_change = false; 3772292SN/A 3782292SN/A toIEWIndex = 0; 3792292SN/A 3802292SN/A sortInsts(); 3812292SN/A 3823867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 3833867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 3842292SN/A 3852292SN/A // Check stall and squash signals. 3863867Sbinkertn@umich.edu while (threads != end) { 3872292SN/A unsigned tid = *threads++; 3882292SN/A 3892292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3902292SN/A 3912292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3922292SN/A 3932292SN/A rename(status_change, tid); 3942292SN/A } 3952292SN/A 3962292SN/A if (status_change) { 3972292SN/A updateStatus(); 3982292SN/A } 3992292SN/A 4002292SN/A if (wroteToTimeBuffer) { 4012292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4022292SN/A cpu->activityThisCycle(); 4032292SN/A } 4042292SN/A 4053867Sbinkertn@umich.edu threads = activeThreads->begin(); 4062292SN/A 4073867Sbinkertn@umich.edu while (threads != end) { 4082292SN/A unsigned tid = *threads++; 4092292SN/A 4102292SN/A // If we committed this cycle then doneSeqNum will be > 0 4112292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4122292SN/A !fromCommit->commitInfo[tid].squash && 4132292SN/A renameStatus[tid] != Squashing) { 4142292SN/A 4152292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4162292SN/A tid); 4172292SN/A } 4182292SN/A } 4192292SN/A 4202292SN/A // @todo: make into updateProgress function 4212292SN/A for (int tid=0; tid < numThreads; tid++) { 4222292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4232292SN/A 4242292SN/A assert(instsInProgress[tid] >=0); 4252292SN/A } 4262292SN/A 4272292SN/A} 4282292SN/A 4292292SN/Atemplate<class Impl> 4302292SN/Avoid 4312292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4322292SN/A{ 4332292SN/A // If status is Running or idle, 4342292SN/A // call renameInsts() 4352292SN/A // If status is Unblocking, 4362292SN/A // buffer any instructions coming from decode 4372292SN/A // continue trying to empty skid buffer 4382292SN/A // check if stall conditions have passed 4392292SN/A 4402292SN/A if (renameStatus[tid] == Blocked) { 4412292SN/A ++renameBlockCycles; 4422292SN/A } else if (renameStatus[tid] == Squashing) { 4432292SN/A ++renameSquashCycles; 4442301SN/A } else if (renameStatus[tid] == SerializeStall) { 4452301SN/A ++renameSerializeStallCycles; 4463788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4473788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4483788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4493788Sgblack@eecs.umich.edu if (resumeSerialize) { 4503788Sgblack@eecs.umich.edu resumeSerialize = false; 4513788Sgblack@eecs.umich.edu block(tid); 4523788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4533788Sgblack@eecs.umich.edu } 4543798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4553798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4563798Sgblack@eecs.umich.edu block(tid); 4573798Sgblack@eecs.umich.edu resumeUnblocking = false; 4583798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4593798Sgblack@eecs.umich.edu } 4602292SN/A } 4612292SN/A 4622292SN/A if (renameStatus[tid] == Running || 4632292SN/A renameStatus[tid] == Idle) { 4642292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4652292SN/A "stage.\n", tid); 4662292SN/A 4672292SN/A renameInsts(tid); 4682292SN/A } else if (renameStatus[tid] == Unblocking) { 4692292SN/A renameInsts(tid); 4702292SN/A 4712292SN/A if (validInsts()) { 4722292SN/A // Add the current inputs to the skid buffer so they can be 4732292SN/A // reprocessed when this stage unblocks. 4742292SN/A skidInsert(tid); 4752292SN/A } 4762292SN/A 4772292SN/A // If we switched over to blocking, then there's a potential for 4782292SN/A // an overall status change. 4792292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4801858SN/A } 4811858SN/A} 4821858SN/A 4831858SN/Atemplate <class Impl> 4841858SN/Avoid 4852292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 4861858SN/A{ 4872292SN/A // Instructions can be either in the skid buffer or the queue of 4882292SN/A // instructions coming from decode, depending on the status. 4892292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4902292SN/A skidBuffer[tid].size() : insts[tid].size(); 4911858SN/A 4922292SN/A // Check the decode queue to see if instructions are available. 4932292SN/A // If there are no available instructions to rename, then do nothing. 4942292SN/A if (insts_available == 0) { 4952292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4962292SN/A tid); 4972292SN/A // Should I change status to idle? 4982292SN/A ++renameIdleCycles; 4992292SN/A return; 5002292SN/A } else if (renameStatus[tid] == Unblocking) { 5012292SN/A ++renameUnblockCycles; 5022292SN/A } else if (renameStatus[tid] == Running) { 5032292SN/A ++renameRunCycles; 5042292SN/A } 5051858SN/A 5062292SN/A DynInstPtr inst; 5072292SN/A 5082292SN/A // Will have to do a different calculation for the number of free 5092292SN/A // entries. 5102292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5112292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5122292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5132292SN/A int min_free_entries = free_rob_entries; 5142292SN/A 5152292SN/A FullSource source = ROB; 5162292SN/A 5172292SN/A if (free_iq_entries < min_free_entries) { 5182292SN/A min_free_entries = free_iq_entries; 5192292SN/A source = IQ; 5202292SN/A } 5212292SN/A 5222292SN/A if (free_lsq_entries < min_free_entries) { 5232292SN/A min_free_entries = free_lsq_entries; 5242292SN/A source = LSQ; 5252292SN/A } 5262292SN/A 5272292SN/A // Check if there's any space left. 5282292SN/A if (min_free_entries <= 0) { 5292292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5302292SN/A "entries.\n" 5312292SN/A "ROB has %i free entries.\n" 5322292SN/A "IQ has %i free entries.\n" 5332292SN/A "LSQ has %i free entries.\n", 5342292SN/A tid, 5352292SN/A free_rob_entries, 5362292SN/A free_iq_entries, 5372292SN/A free_lsq_entries); 5382292SN/A 5392292SN/A blockThisCycle = true; 5402292SN/A 5412292SN/A block(tid); 5422292SN/A 5432292SN/A incrFullStat(source); 5442292SN/A 5452292SN/A return; 5462292SN/A } else if (min_free_entries < insts_available) { 5472292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5482292SN/A "%i insts available, but only %i insts can be " 5492292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5502292SN/A tid, insts_available, min_free_entries); 5512292SN/A 5522292SN/A insts_available = min_free_entries; 5532292SN/A 5542292SN/A blockThisCycle = true; 5552292SN/A 5562292SN/A incrFullStat(source); 5572292SN/A } 5582292SN/A 5592292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5602292SN/A skidBuffer[tid] : insts[tid]; 5612292SN/A 5622292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5632292SN/A "send iew.\n", tid, insts_available); 5642292SN/A 5652292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5662292SN/A "dispatched to IQ last cycle.\n", 5672292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5682292SN/A 5692292SN/A // Handle serializing the next instruction if necessary. 5702292SN/A if (serializeOnNextInst[tid]) { 5712292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5722292SN/A // ROB already empty; no need to serialize. 5732292SN/A serializeOnNextInst[tid] = false; 5742292SN/A } else if (!insts_to_rename.empty()) { 5752292SN/A insts_to_rename.front()->setSerializeBefore(); 5762292SN/A } 5772292SN/A } 5782292SN/A 5792292SN/A int renamed_insts = 0; 5802292SN/A 5812292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5822292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5832292SN/A 5842292SN/A assert(!insts_to_rename.empty()); 5852292SN/A 5862292SN/A inst = insts_to_rename.front(); 5872292SN/A 5882292SN/A insts_to_rename.pop_front(); 5892292SN/A 5902292SN/A if (renameStatus[tid] == Unblocking) { 5912292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 5922292SN/A "skidBuffer\n", 5932292SN/A tid, inst->seqNum, inst->readPC()); 5942292SN/A } 5952292SN/A 5962292SN/A if (inst->isSquashed()) { 5972292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 5982292SN/A "squashed, skipping.\n", 5992935Sksewell@umich.edu tid, inst->seqNum, inst->readPC()); 6002292SN/A 6012292SN/A ++renameSquashedInsts; 6022292SN/A 6032292SN/A // Decrement how many instructions are available. 6042292SN/A --insts_available; 6052292SN/A 6062292SN/A continue; 6072292SN/A } 6082292SN/A 6092292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6102292SN/A "PC %#x.\n", 6112292SN/A tid, inst->seqNum, inst->readPC()); 6122292SN/A 6132292SN/A // Handle serializeAfter/serializeBefore instructions. 6142292SN/A // serializeAfter marks the next instruction as serializeBefore. 6152292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6162292SN/A // is empty. 6172336SN/A 6182336SN/A // In this model, IPR accesses are serialize before 6192336SN/A // instructions, and store conditionals are serialize after 6202336SN/A // instructions. This is mainly due to lack of support for 6212336SN/A // out-of-order operations of either of those classes of 6222336SN/A // instructions. 6232336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6242336SN/A !inst->isSerializeHandled()) { 6252292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6262292SN/A 6272301SN/A if (!inst->isTempSerializeBefore()) { 6282301SN/A renamedSerializing++; 6292292SN/A inst->setSerializeHandled(); 6302301SN/A } else { 6312301SN/A renamedTempSerializing++; 6322301SN/A } 6332292SN/A 6342301SN/A // Change status over to SerializeStall so that other stages know 6352292SN/A // what this is blocked on. 6362301SN/A renameStatus[tid] = SerializeStall; 6372292SN/A 6382301SN/A serializeInst[tid] = inst; 6392292SN/A 6402292SN/A blockThisCycle = true; 6412292SN/A 6422292SN/A break; 6432336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6442336SN/A !inst->isSerializeHandled()) { 6452292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6462292SN/A 6472307SN/A renamedSerializing++; 6482307SN/A 6492292SN/A inst->setSerializeHandled(); 6502292SN/A 6512292SN/A serializeAfter(insts_to_rename, tid); 6522292SN/A } 6532292SN/A 6542292SN/A // Check here to make sure there are enough destination registers 6552292SN/A // to rename to. Otherwise block. 6562292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6572292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6582292SN/A "physical registers to rename to.\n"); 6592292SN/A blockThisCycle = true; 6604345Sktlim@umich.edu insts_to_rename.push_front(inst); 6612292SN/A ++renameFullRegistersEvents; 6622292SN/A 6632292SN/A break; 6642292SN/A } 6652292SN/A 6662292SN/A renameSrcRegs(inst, inst->threadNumber); 6672292SN/A 6682292SN/A renameDestRegs(inst, inst->threadNumber); 6692292SN/A 6702292SN/A ++renamed_insts; 6712292SN/A 6722292SN/A // Put instruction in rename queue. 6732292SN/A toIEW->insts[toIEWIndex] = inst; 6742292SN/A ++(toIEW->size); 6752292SN/A 6762292SN/A // Increment which instruction we're on. 6772292SN/A ++toIEWIndex; 6782292SN/A 6792292SN/A // Decrement how many instructions are available. 6802292SN/A --insts_available; 6812292SN/A } 6822292SN/A 6832292SN/A instsInProgress[tid] += renamed_insts; 6842307SN/A renameRenamedInsts += renamed_insts; 6852292SN/A 6862292SN/A // If we wrote to the time buffer, record this. 6872292SN/A if (toIEWIndex) { 6882292SN/A wroteToTimeBuffer = true; 6892292SN/A } 6902292SN/A 6912292SN/A // Check if there's any instructions left that haven't yet been renamed. 6922292SN/A // If so then block. 6932292SN/A if (insts_available) { 6942292SN/A blockThisCycle = true; 6952292SN/A } 6962292SN/A 6972292SN/A if (blockThisCycle) { 6982292SN/A block(tid); 6992292SN/A toDecode->renameUnblock[tid] = false; 7002292SN/A } 7012292SN/A} 7022292SN/A 7032292SN/Atemplate<class Impl> 7042292SN/Avoid 7052292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 7062292SN/A{ 7072292SN/A DynInstPtr inst = NULL; 7082292SN/A 7092292SN/A while (!insts[tid].empty()) { 7102292SN/A inst = insts[tid].front(); 7112292SN/A 7122292SN/A insts[tid].pop_front(); 7132292SN/A 7142292SN/A assert(tid == inst->threadNumber); 7152292SN/A 7162292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 7172292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 7182292SN/A 7192307SN/A ++renameSkidInsts; 7202307SN/A 7212292SN/A skidBuffer[tid].push_back(inst); 7222292SN/A } 7232292SN/A 7242292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7253798Sgblack@eecs.umich.edu { 7263798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7273798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7283798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7293798Sgblack@eecs.umich.edu { 7303798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7313798Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->readPC()), 7323798Sgblack@eecs.umich.edu (*it)->seqNum); 7333798Sgblack@eecs.umich.edu } 7342292SN/A panic("Skidbuffer Exceeded Max Size"); 7353798Sgblack@eecs.umich.edu } 7362292SN/A} 7372292SN/A 7382292SN/Atemplate <class Impl> 7392292SN/Avoid 7402292SN/ADefaultRename<Impl>::sortInsts() 7412292SN/A{ 7422292SN/A int insts_from_decode = fromDecode->size; 7432329SN/A#ifdef DEBUG 7442292SN/A for (int i=0; i < numThreads; i++) 7452292SN/A assert(insts[i].empty()); 7462329SN/A#endif 7472292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7482292SN/A DynInstPtr inst = fromDecode->insts[i]; 7492292SN/A insts[inst->threadNumber].push_back(inst); 7502292SN/A } 7512292SN/A} 7522292SN/A 7532292SN/Atemplate<class Impl> 7542292SN/Abool 7552292SN/ADefaultRename<Impl>::skidsEmpty() 7562292SN/A{ 7573867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7583867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7592292SN/A 7603867Sbinkertn@umich.edu while (threads != end) { 7613867Sbinkertn@umich.edu unsigned tid = *threads++; 7623867Sbinkertn@umich.edu 7633867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7642292SN/A return false; 7652292SN/A } 7662292SN/A 7672292SN/A return true; 7682292SN/A} 7692292SN/A 7702292SN/Atemplate<class Impl> 7712292SN/Avoid 7722292SN/ADefaultRename<Impl>::updateStatus() 7732292SN/A{ 7742292SN/A bool any_unblocking = false; 7752292SN/A 7763867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7773867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7782292SN/A 7793867Sbinkertn@umich.edu while (threads != end) { 7802292SN/A unsigned tid = *threads++; 7812292SN/A 7822292SN/A if (renameStatus[tid] == Unblocking) { 7832292SN/A any_unblocking = true; 7842292SN/A break; 7852292SN/A } 7862292SN/A } 7872292SN/A 7882292SN/A // Rename will have activity if it's unblocking. 7892292SN/A if (any_unblocking) { 7902292SN/A if (_status == Inactive) { 7912292SN/A _status = Active; 7922292SN/A 7932292SN/A DPRINTF(Activity, "Activating stage.\n"); 7942292SN/A 7952733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7962292SN/A } 7972292SN/A } else { 7982292SN/A // If it's not unblocking, then rename will not have any internal 7992292SN/A // activity. Switch it to inactive. 8002292SN/A if (_status == Active) { 8012292SN/A _status = Inactive; 8022292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8032292SN/A 8042733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8052292SN/A } 8062292SN/A } 8072292SN/A} 8082292SN/A 8092292SN/Atemplate <class Impl> 8102292SN/Abool 8112292SN/ADefaultRename<Impl>::block(unsigned tid) 8122292SN/A{ 8132292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8142292SN/A 8152292SN/A // Add the current inputs onto the skid buffer, so they can be 8162292SN/A // reprocessed when this stage unblocks. 8172292SN/A skidInsert(tid); 8182292SN/A 8192292SN/A // Only signal backwards to block if the previous stages do not think 8202292SN/A // rename is already blocked. 8212292SN/A if (renameStatus[tid] != Blocked) { 8223798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8233798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8243798Sgblack@eecs.umich.edu // stages to block. 8253798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8262292SN/A toDecode->renameBlock[tid] = true; 8272292SN/A toDecode->renameUnblock[tid] = false; 8282292SN/A wroteToTimeBuffer = true; 8292292SN/A } 8302292SN/A 8312329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8322329SN/A // it would not know to complete the serialize stall. 8332301SN/A if (renameStatus[tid] != SerializeStall) { 8342292SN/A // Set status to Blocked. 8352292SN/A renameStatus[tid] = Blocked; 8362292SN/A return true; 8372292SN/A } 8382292SN/A } 8392292SN/A 8402292SN/A return false; 8412292SN/A} 8422292SN/A 8432292SN/Atemplate <class Impl> 8442292SN/Abool 8452292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8462292SN/A{ 8472292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8482292SN/A 8492292SN/A // Rename is done unblocking if the skid buffer is empty. 8502301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8512292SN/A 8522292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8532292SN/A 8542292SN/A toDecode->renameUnblock[tid] = true; 8552292SN/A wroteToTimeBuffer = true; 8562292SN/A 8572292SN/A renameStatus[tid] = Running; 8582292SN/A return true; 8592292SN/A } 8602292SN/A 8612292SN/A return false; 8622292SN/A} 8632292SN/A 8642292SN/Atemplate <class Impl> 8652292SN/Avoid 8662935Sksewell@umich.eduDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 8672292SN/A{ 8682980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8692980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8702292SN/A 8711060SN/A // After a syscall squashes everything, the history buffer may be empty 8721060SN/A // but the ROB may still be squashing instructions. 8732292SN/A if (historyBuffer[tid].empty()) { 8741060SN/A return; 8751060SN/A } 8761060SN/A 8771060SN/A // Go through the most recent instructions, undoing the mappings 8781060SN/A // they did and freeing up the registers. 8792292SN/A while (!historyBuffer[tid].empty() && 8802292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8812292SN/A assert(hb_it != historyBuffer[tid].end()); 8821062SN/A 8832292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8842292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8851060SN/A 8862292SN/A // Tell the rename map to set the architected register to the 8872292SN/A // previous physical register that it was renamed to. 8882292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8891060SN/A 8902292SN/A // Put the renamed physical register back on the free list. 8912292SN/A freeList->addReg(hb_it->newPhysReg); 8921062SN/A 8932367SN/A // Be sure to mark its register as ready if it's a misc register. 8942367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 8952367SN/A scoreboard->setReg(hb_it->newPhysReg); 8962367SN/A } 8972367SN/A 8982292SN/A historyBuffer[tid].erase(hb_it++); 8991061SN/A 9001062SN/A ++renameUndoneMaps; 9011060SN/A } 9021060SN/A} 9031060SN/A 9041060SN/Atemplate<class Impl> 9051060SN/Avoid 9062292SN/ADefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 9071060SN/A{ 9082292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9092292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9102292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9112292SN/A 9122980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9132980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9141060SN/A 9151061SN/A --hb_it; 9161060SN/A 9172292SN/A if (historyBuffer[tid].empty()) { 9182292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9192292SN/A return; 9202292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9212292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9222292SN/A "that a syscall happened recently.\n", tid); 9231060SN/A return; 9241060SN/A } 9251060SN/A 9262292SN/A // Commit all the renames up until (and including) the committed sequence 9272292SN/A // number. Some or even all of the committed instructions may not have 9282292SN/A // rename histories if they did not have destination registers that were 9292292SN/A // renamed. 9302292SN/A while (!historyBuffer[tid].empty() && 9312292SN/A hb_it != historyBuffer[tid].end() && 9322292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9331060SN/A 9342329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9352329SN/A "[sn:%lli].\n", 9362292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9371061SN/A 9382292SN/A freeList->addReg((*hb_it).prevPhysReg); 9392292SN/A ++renameCommittedMaps; 9401061SN/A 9412292SN/A historyBuffer[tid].erase(hb_it--); 9421060SN/A } 9431060SN/A} 9441060SN/A 9451061SN/Atemplate <class Impl> 9461061SN/Ainline void 9472292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9481061SN/A{ 9492292SN/A assert(renameMap[tid] != 0); 9502292SN/A 9511061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9521061SN/A 9531061SN/A // Get the architectual register numbers from the source and 9541061SN/A // destination operands, and redirect them to the right register. 9551061SN/A // Will need to mark dependencies though. 9562292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9571061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9583773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9593773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9603773Sgblack@eecs.umich.edu flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 9613773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 9625082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9635082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9645082Sgblack@eecs.umich.edu flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); 9655082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9664352Sgblack@eecs.umich.edu } else { 9674352Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 9684636Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); 9693773Sgblack@eecs.umich.edu } 9704352Sgblack@eecs.umich.edu 9713773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 9721061SN/A 9731061SN/A // Look up the source registers to get the phys. register they've 9741061SN/A // been renamed to, and set the sources to those registers. 9753773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 9761061SN/A 9772292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9783773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 9792292SN/A (int)renamed_reg); 9801061SN/A 9811061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9821061SN/A 9832292SN/A // See if the register is ready or not. 9842292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9854636Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg); 9861061SN/A 9871061SN/A inst->markSrcRegReady(src_idx); 9884636Sgblack@eecs.umich.edu } else { 9894636Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg); 9901061SN/A } 9911062SN/A 9921062SN/A ++renameRenameLookups; 9931061SN/A } 9941061SN/A} 9951061SN/A 9961061SN/Atemplate <class Impl> 9971061SN/Ainline void 9982292SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 9991061SN/A{ 10002292SN/A typename RenameMap::RenameInfo rename_result; 10011061SN/A 10021061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10031061SN/A 10042292SN/A // Rename the destination registers. 10052292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10062292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10073773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10083773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10094352Sgblack@eecs.umich.edu // Integer registers are flattened. 10103773Sgblack@eecs.umich.edu flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 10113773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 10124352Sgblack@eecs.umich.edu } else { 10134352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10144352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10154352Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; 10164636Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg); 10173773Sgblack@eecs.umich.edu } 10183773Sgblack@eecs.umich.edu 10193773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10201061SN/A 10212292SN/A // Get the physical register that the destination will be 10222292SN/A // renamed to. 10233773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10241061SN/A 10252292SN/A //Mark Scoreboard entry as not ready 10262292SN/A scoreboard->unsetReg(rename_result.first); 10271062SN/A 10282292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10293773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10302292SN/A (int)rename_result.first); 10311062SN/A 10322292SN/A // Record the rename information so that a history can be kept. 10333773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10342292SN/A rename_result.first, 10352292SN/A rename_result.second); 10361062SN/A 10372292SN/A historyBuffer[tid].push_front(hb_entry); 10381062SN/A 10392935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10402935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10412935Sksewell@umich.edu historyBuffer[tid].size(), 10422292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10431062SN/A 10442292SN/A // Tell the instruction to rename the appropriate destination 10452292SN/A // register (dest_idx) to the new physical register 10462292SN/A // (rename_result.first), and record the previous physical 10472292SN/A // register that the same logical register was renamed to 10482292SN/A // (rename_result.second). 10492292SN/A inst->renameDestReg(dest_idx, 10502292SN/A rename_result.first, 10512292SN/A rename_result.second); 10521062SN/A 10532292SN/A ++renameRenamedOperands; 10541061SN/A } 10551061SN/A} 10561061SN/A 10571061SN/Atemplate <class Impl> 10581061SN/Ainline int 10592292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 10601061SN/A{ 10612292SN/A int num_free = freeEntries[tid].robEntries - 10622292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10632292SN/A 10642292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10652292SN/A 10662292SN/A return num_free; 10671061SN/A} 10681061SN/A 10691061SN/Atemplate <class Impl> 10701061SN/Ainline int 10712292SN/ADefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 10721061SN/A{ 10732292SN/A int num_free = freeEntries[tid].iqEntries - 10742292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10752292SN/A 10762292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10772292SN/A 10782292SN/A return num_free; 10792292SN/A} 10802292SN/A 10812292SN/Atemplate <class Impl> 10822292SN/Ainline int 10832292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 10842292SN/A{ 10852292SN/A int num_free = freeEntries[tid].lsqEntries - 10862292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10872292SN/A 10882292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 10892292SN/A 10902292SN/A return num_free; 10912292SN/A} 10922292SN/A 10932292SN/Atemplate <class Impl> 10942292SN/Aunsigned 10952292SN/ADefaultRename<Impl>::validInsts() 10962292SN/A{ 10972292SN/A unsigned inst_count = 0; 10982292SN/A 10992292SN/A for (int i=0; i<fromDecode->size; i++) { 11002731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11012292SN/A inst_count++; 11022292SN/A } 11032292SN/A 11042292SN/A return inst_count; 11052292SN/A} 11062292SN/A 11072292SN/Atemplate <class Impl> 11082292SN/Avoid 11092292SN/ADefaultRename<Impl>::readStallSignals(unsigned tid) 11102292SN/A{ 11112292SN/A if (fromIEW->iewBlock[tid]) { 11122292SN/A stalls[tid].iew = true; 11132292SN/A } 11142292SN/A 11152292SN/A if (fromIEW->iewUnblock[tid]) { 11162292SN/A assert(stalls[tid].iew); 11172292SN/A stalls[tid].iew = false; 11182292SN/A } 11192292SN/A 11202292SN/A if (fromCommit->commitBlock[tid]) { 11212292SN/A stalls[tid].commit = true; 11222292SN/A } 11232292SN/A 11242292SN/A if (fromCommit->commitUnblock[tid]) { 11252292SN/A assert(stalls[tid].commit); 11262292SN/A stalls[tid].commit = false; 11272292SN/A } 11282292SN/A} 11292292SN/A 11302292SN/Atemplate <class Impl> 11312292SN/Abool 11322292SN/ADefaultRename<Impl>::checkStall(unsigned tid) 11332292SN/A{ 11342292SN/A bool ret_val = false; 11352292SN/A 11362292SN/A if (stalls[tid].iew) { 11372292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11382292SN/A ret_val = true; 11392292SN/A } else if (stalls[tid].commit) { 11402292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11412292SN/A ret_val = true; 11422292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11432292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11442292SN/A ret_val = true; 11452292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11462292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11472292SN/A ret_val = true; 11482292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11492292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11502292SN/A ret_val = true; 11512292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11522292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11532292SN/A ret_val = true; 11542301SN/A } else if (renameStatus[tid] == SerializeStall && 11552292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11562301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11572292SN/A "empty.\n", 11582292SN/A tid); 11592292SN/A ret_val = true; 11602292SN/A } 11612292SN/A 11622292SN/A return ret_val; 11632292SN/A} 11642292SN/A 11652292SN/Atemplate <class Impl> 11662292SN/Avoid 11672292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 11682292SN/A{ 11692292SN/A bool updated = false; 11702292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 11712292SN/A freeEntries[tid].iqEntries = 11722292SN/A fromIEW->iewInfo[tid].freeIQEntries; 11732292SN/A updated = true; 11742292SN/A } 11752292SN/A 11762292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11772292SN/A freeEntries[tid].lsqEntries = 11782292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 11792292SN/A updated = true; 11802292SN/A } 11812292SN/A 11822292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11832292SN/A freeEntries[tid].robEntries = 11842292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11852292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11862292SN/A updated = true; 11872292SN/A } 11882292SN/A 11892292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11902292SN/A tid, 11912292SN/A freeEntries[tid].iqEntries, 11922292SN/A freeEntries[tid].robEntries, 11932292SN/A freeEntries[tid].lsqEntries); 11942292SN/A 11952292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 11962292SN/A tid, instsInProgress[tid]); 11972292SN/A} 11982292SN/A 11992292SN/Atemplate <class Impl> 12002292SN/Abool 12012292SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 12022292SN/A{ 12032292SN/A // Check if there's a squash signal, squash if there is 12042292SN/A // Check stall signals, block if necessary. 12052292SN/A // If status was blocked 12062292SN/A // check if stall conditions have passed 12072292SN/A // if so then go to unblocking 12082292SN/A // If status was Squashing 12092292SN/A // check if squashing is not high. Switch to running this cycle. 12102301SN/A // If status was serialize stall 12112292SN/A // check if ROB is empty and no insts are in flight to the ROB 12122292SN/A 12132292SN/A readFreeEntries(tid); 12142292SN/A readStallSignals(tid); 12152292SN/A 12162292SN/A if (fromCommit->commitInfo[tid].squash) { 12172292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12182292SN/A "commit.\n", tid); 12192292SN/A 12204632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12212292SN/A 12222292SN/A return true; 12232292SN/A } 12242292SN/A 12252292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12262292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12272292SN/A 12282292SN/A renameStatus[tid] = Squashing; 12292292SN/A 12302292SN/A return true; 12312292SN/A } 12322292SN/A 12332292SN/A if (checkStall(tid)) { 12342292SN/A return block(tid); 12352292SN/A } 12362292SN/A 12372292SN/A if (renameStatus[tid] == Blocked) { 12382292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12392292SN/A tid); 12402292SN/A 12412292SN/A renameStatus[tid] = Unblocking; 12422292SN/A 12432292SN/A unblock(tid); 12442292SN/A 12452292SN/A return true; 12462292SN/A } 12472292SN/A 12482292SN/A if (renameStatus[tid] == Squashing) { 12492292SN/A // Switch status to running if rename isn't being told to block or 12502292SN/A // squash this cycle. 12513798Sgblack@eecs.umich.edu if (resumeSerialize) { 12523798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12533798Sgblack@eecs.umich.edu tid); 12542292SN/A 12553798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12563798Sgblack@eecs.umich.edu return true; 12573798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12583798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12593798Sgblack@eecs.umich.edu tid); 12603798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12613798Sgblack@eecs.umich.edu return true; 12623798Sgblack@eecs.umich.edu } else { 12633788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12643788Sgblack@eecs.umich.edu tid); 12652292SN/A 12663788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 12673788Sgblack@eecs.umich.edu return false; 12683788Sgblack@eecs.umich.edu } 12692292SN/A } 12702292SN/A 12712301SN/A if (renameStatus[tid] == SerializeStall) { 12722292SN/A // Stall ends once the ROB is free. 12732301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 12742292SN/A "unblocking.\n", tid); 12752292SN/A 12762301SN/A DynInstPtr serial_inst = serializeInst[tid]; 12772292SN/A 12782292SN/A renameStatus[tid] = Unblocking; 12792292SN/A 12802292SN/A unblock(tid); 12812292SN/A 12822292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 12832292SN/A "PC %#x.\n", 12842301SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 12852292SN/A 12862292SN/A // Put instruction into queue here. 12872301SN/A serial_inst->clearSerializeBefore(); 12882292SN/A 12892292SN/A if (!skidBuffer[tid].empty()) { 12902301SN/A skidBuffer[tid].push_front(serial_inst); 12912292SN/A } else { 12922301SN/A insts[tid].push_front(serial_inst); 12932292SN/A } 12942292SN/A 12952292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 12962703Sktlim@umich.edu " Adding to front of list.\n", tid); 12972292SN/A 12982301SN/A serializeInst[tid] = NULL; 12992292SN/A 13002292SN/A return true; 13012292SN/A } 13022292SN/A 13032292SN/A // If we've reached this point, we have not gotten any signals that 13042292SN/A // cause rename to change its status. Rename remains the same as before. 13052292SN/A return false; 13061061SN/A} 13071061SN/A 13081060SN/Atemplate<class Impl> 13091060SN/Avoid 13102292SN/ADefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 13112292SN/A unsigned tid) 13121060SN/A{ 13132292SN/A if (inst_list.empty()) { 13142292SN/A // Mark a bit to say that I must serialize on the next instruction. 13152292SN/A serializeOnNextInst[tid] = true; 13161060SN/A return; 13171060SN/A } 13181060SN/A 13192292SN/A // Set the next instruction as serializing. 13202292SN/A inst_list.front()->setSerializeBefore(); 13212292SN/A} 13222292SN/A 13232292SN/Atemplate <class Impl> 13242292SN/Ainline void 13252292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13262292SN/A{ 13272292SN/A switch (source) { 13282292SN/A case ROB: 13292292SN/A ++renameROBFullEvents; 13302292SN/A break; 13312292SN/A case IQ: 13322292SN/A ++renameIQFullEvents; 13332292SN/A break; 13342292SN/A case LSQ: 13352292SN/A ++renameLSQFullEvents; 13362292SN/A break; 13372292SN/A default: 13382292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13392292SN/A break; 13401060SN/A } 13412292SN/A} 13421060SN/A 13432292SN/Atemplate <class Impl> 13442292SN/Avoid 13452292SN/ADefaultRename<Impl>::dumpHistory() 13462292SN/A{ 13472980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13481060SN/A 13492292SN/A for (int i = 0; i < numThreads; i++) { 13501060SN/A 13512292SN/A buf_it = historyBuffer[i].begin(); 13521060SN/A 13532292SN/A while (buf_it != historyBuffer[i].end()) { 13542292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13552292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13562292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13571060SN/A 13582292SN/A buf_it++; 13591062SN/A } 13601060SN/A } 13611060SN/A} 1362