rename_impl.hh revision 3867
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292935Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321060SN/A#include <list> 331060SN/A 341858SN/A#include "config/full_system.hh" 351717SN/A#include "cpu/o3/rename.hh" 361060SN/A 371061SN/Atemplate <class Impl> 382292SN/ADefaultRename<Impl>::DefaultRename(Params *params) 392292SN/A : iewToRenameDelay(params->iewToRenameDelay), 402292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 412292SN/A commitToRenameDelay(params->commitToRenameDelay), 422292SN/A renameWidth(params->renameWidth), 432292SN/A commitWidth(params->commitWidth), 442361SN/A numThreads(params->numberOfThreads), 452361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 461060SN/A{ 472292SN/A _status = Inactive; 482292SN/A 492292SN/A for (int i=0; i< numThreads; i++) { 502292SN/A renameStatus[i] = Idle; 512292SN/A 522292SN/A freeEntries[i].iqEntries = 0; 532292SN/A freeEntries[i].lsqEntries = 0; 542292SN/A freeEntries[i].robEntries = 0; 552292SN/A 562292SN/A stalls[i].iew = false; 572292SN/A stalls[i].commit = false; 582301SN/A serializeInst[i] = NULL; 592292SN/A 602292SN/A instsInProgress[i] = 0; 612292SN/A 622292SN/A emptyROB[i] = true; 632292SN/A 642292SN/A serializeOnNextInst[i] = false; 652292SN/A } 662292SN/A 672292SN/A // @todo: Make into a parameter. 682292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Astd::string 732292SN/ADefaultRename<Impl>::name() const 742292SN/A{ 752292SN/A return cpu->name() + ".rename"; 761060SN/A} 771060SN/A 781061SN/Atemplate <class Impl> 791060SN/Avoid 802292SN/ADefaultRename<Impl>::regStats() 811062SN/A{ 821062SN/A renameSquashCycles 832301SN/A .name(name() + ".RENAME:SquashCycles") 841062SN/A .desc("Number of cycles rename is squashing") 851062SN/A .prereq(renameSquashCycles); 861062SN/A renameIdleCycles 872301SN/A .name(name() + ".RENAME:IdleCycles") 881062SN/A .desc("Number of cycles rename is idle") 891062SN/A .prereq(renameIdleCycles); 901062SN/A renameBlockCycles 912301SN/A .name(name() + ".RENAME:BlockCycles") 921062SN/A .desc("Number of cycles rename is blocking") 931062SN/A .prereq(renameBlockCycles); 942301SN/A renameSerializeStallCycles 952301SN/A .name(name() + ".RENAME:serializeStallCycles") 962301SN/A .desc("count of cycles rename stalled for serializing inst") 972301SN/A .flags(Stats::total); 982292SN/A renameRunCycles 992301SN/A .name(name() + ".RENAME:RunCycles") 1002292SN/A .desc("Number of cycles rename is running") 1012292SN/A .prereq(renameIdleCycles); 1021062SN/A renameUnblockCycles 1032301SN/A .name(name() + ".RENAME:UnblockCycles") 1041062SN/A .desc("Number of cycles rename is unblocking") 1051062SN/A .prereq(renameUnblockCycles); 1061062SN/A renameRenamedInsts 1072301SN/A .name(name() + ".RENAME:RenamedInsts") 1081062SN/A .desc("Number of instructions processed by rename") 1091062SN/A .prereq(renameRenamedInsts); 1101062SN/A renameSquashedInsts 1112301SN/A .name(name() + ".RENAME:SquashedInsts") 1121062SN/A .desc("Number of squashed instructions processed by rename") 1131062SN/A .prereq(renameSquashedInsts); 1141062SN/A renameROBFullEvents 1152301SN/A .name(name() + ".RENAME:ROBFullEvents") 1162292SN/A .desc("Number of times rename has blocked due to ROB full") 1171062SN/A .prereq(renameROBFullEvents); 1181062SN/A renameIQFullEvents 1192301SN/A .name(name() + ".RENAME:IQFullEvents") 1202292SN/A .desc("Number of times rename has blocked due to IQ full") 1211062SN/A .prereq(renameIQFullEvents); 1222292SN/A renameLSQFullEvents 1232301SN/A .name(name() + ".RENAME:LSQFullEvents") 1242292SN/A .desc("Number of times rename has blocked due to LSQ full") 1252292SN/A .prereq(renameLSQFullEvents); 1261062SN/A renameFullRegistersEvents 1272301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1281062SN/A .desc("Number of times there has been no free registers") 1291062SN/A .prereq(renameFullRegistersEvents); 1301062SN/A renameRenamedOperands 1312301SN/A .name(name() + ".RENAME:RenamedOperands") 1321062SN/A .desc("Number of destination operands rename has renamed") 1331062SN/A .prereq(renameRenamedOperands); 1341062SN/A renameRenameLookups 1352301SN/A .name(name() + ".RENAME:RenameLookups") 1361062SN/A .desc("Number of register rename lookups that rename has made") 1371062SN/A .prereq(renameRenameLookups); 1381062SN/A renameCommittedMaps 1392301SN/A .name(name() + ".RENAME:CommittedMaps") 1401062SN/A .desc("Number of HB maps that are committed") 1411062SN/A .prereq(renameCommittedMaps); 1421062SN/A renameUndoneMaps 1432301SN/A .name(name() + ".RENAME:UndoneMaps") 1441062SN/A .desc("Number of HB maps that are undone due to squashing") 1451062SN/A .prereq(renameUndoneMaps); 1462301SN/A renamedSerializing 1472301SN/A .name(name() + ".RENAME:serializingInsts") 1482301SN/A .desc("count of serializing insts renamed") 1492301SN/A .flags(Stats::total) 1502301SN/A ; 1512301SN/A renamedTempSerializing 1522301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1532301SN/A .desc("count of temporary serializing insts renamed") 1542301SN/A .flags(Stats::total) 1552301SN/A ; 1562307SN/A renameSkidInsts 1572307SN/A .name(name() + ".RENAME:skidInsts") 1582307SN/A .desc("count of insts added to the skid buffer") 1592307SN/A .flags(Stats::total) 1602307SN/A ; 1611062SN/A} 1621062SN/A 1631062SN/Atemplate <class Impl> 1641062SN/Avoid 1652733Sktlim@umich.eduDefaultRename<Impl>::setCPU(O3CPU *cpu_ptr) 1661060SN/A{ 1672292SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1681060SN/A cpu = cpu_ptr; 1691060SN/A} 1701060SN/A 1711061SN/Atemplate <class Impl> 1721060SN/Avoid 1732292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1741060SN/A{ 1752292SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1761060SN/A timeBuffer = tb_ptr; 1771060SN/A 1781060SN/A // Setup wire to read information from time buffer, from IEW stage. 1791060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1801060SN/A 1811060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1821060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1831060SN/A 1841060SN/A // Setup wire to write information to previous stages. 1851060SN/A toDecode = timeBuffer->getWire(0); 1861060SN/A} 1871060SN/A 1881061SN/Atemplate <class Impl> 1891060SN/Avoid 1902292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1911060SN/A{ 1922292SN/A DPRINTF(Rename, "Setting rename queue pointer.\n"); 1931060SN/A renameQueue = rq_ptr; 1941060SN/A 1951060SN/A // Setup wire to write information to future stages. 1961060SN/A toIEW = renameQueue->getWire(0); 1971060SN/A} 1981060SN/A 1991061SN/Atemplate <class Impl> 2001060SN/Avoid 2012292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2021060SN/A{ 2032292SN/A DPRINTF(Rename, "Setting decode queue pointer.\n"); 2041060SN/A decodeQueue = dq_ptr; 2051060SN/A 2061060SN/A // Setup wire to get information from decode. 2071060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2081060SN/A} 2091060SN/A 2101061SN/Atemplate <class Impl> 2111060SN/Avoid 2122292SN/ADefaultRename<Impl>::initStage() 2131060SN/A{ 2142329SN/A // Grab the number of free entries directly from the stages. 2152292SN/A for (int tid=0; tid < numThreads; tid++) { 2162292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2172292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2182292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2192292SN/A emptyROB[tid] = true; 2202292SN/A } 2211060SN/A} 2221060SN/A 2232292SN/Atemplate<class Impl> 2242292SN/Avoid 2252980Sgblack@eecs.umich.eduDefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2262292SN/A{ 2272292SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2282292SN/A activeThreads = at_ptr; 2292292SN/A} 2302292SN/A 2312292SN/A 2321061SN/Atemplate <class Impl> 2331060SN/Avoid 2342292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2351060SN/A{ 2362292SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2371060SN/A 2382292SN/A for (int i=0; i<numThreads; i++) { 2392292SN/A renameMap[i] = &rm_ptr[i]; 2401060SN/A } 2411060SN/A} 2421060SN/A 2431061SN/Atemplate <class Impl> 2441060SN/Avoid 2452292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2461060SN/A{ 2472292SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2482292SN/A freeList = fl_ptr; 2492292SN/A} 2501060SN/A 2512292SN/Atemplate<class Impl> 2522292SN/Avoid 2532292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2542292SN/A{ 2552292SN/A DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2562292SN/A scoreboard = _scoreboard; 2571060SN/A} 2581060SN/A 2591061SN/Atemplate <class Impl> 2602863Sktlim@umich.edubool 2612843Sktlim@umich.eduDefaultRename<Impl>::drain() 2621060SN/A{ 2632348SN/A // Rename is ready to switch out at any time. 2642843Sktlim@umich.edu cpu->signalDrained(); 2652863Sktlim@umich.edu return true; 2662316SN/A} 2671060SN/A 2682316SN/Atemplate <class Impl> 2692316SN/Avoid 2702843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2712316SN/A{ 2722348SN/A // Clear any state, fix up the rename map. 2732307SN/A for (int i = 0; i < numThreads; i++) { 2742980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2752980Sgblack@eecs.umich.edu historyBuffer[i].begin(); 2762307SN/A 2772307SN/A while (!historyBuffer[i].empty()) { 2782307SN/A assert(hb_it != historyBuffer[i].end()); 2792307SN/A 2802307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2812307SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2822307SN/A 2832307SN/A // Tell the rename map to set the architected register to the 2842307SN/A // previous physical register that it was renamed to. 2852307SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2862307SN/A 2872307SN/A // Put the renamed physical register back on the free list. 2882307SN/A freeList->addReg(hb_it->newPhysReg); 2892307SN/A 2902361SN/A // Be sure to mark its register as ready if it's a misc register. 2912361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2922361SN/A scoreboard->setReg(hb_it->newPhysReg); 2932361SN/A } 2942361SN/A 2952307SN/A historyBuffer[i].erase(hb_it++); 2962307SN/A } 2972307SN/A insts[i].clear(); 2982307SN/A skidBuffer[i].clear(); 2991060SN/A } 3001060SN/A} 3011060SN/A 3021061SN/Atemplate <class Impl> 3031060SN/Avoid 3042307SN/ADefaultRename<Impl>::takeOverFrom() 3051060SN/A{ 3062307SN/A _status = Inactive; 3072307SN/A initStage(); 3081060SN/A 3092329SN/A // Reset all state prior to taking over from the other CPU. 3102307SN/A for (int i=0; i< numThreads; i++) { 3112307SN/A renameStatus[i] = Idle; 3121060SN/A 3132307SN/A stalls[i].iew = false; 3142307SN/A stalls[i].commit = false; 3152307SN/A serializeInst[i] = NULL; 3162307SN/A 3172307SN/A instsInProgress[i] = 0; 3182307SN/A 3192307SN/A emptyROB[i] = true; 3202307SN/A 3212307SN/A serializeOnNextInst[i] = false; 3222307SN/A } 3232307SN/A} 3242307SN/A 3252307SN/Atemplate <class Impl> 3262307SN/Avoid 3272935Sksewell@umich.eduDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 3281858SN/A{ 3292292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3301858SN/A 3312292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3322292SN/A // If it still needs to block, the blocking should happen the next 3332292SN/A // cycle and there should be space to hold everything due to the squash. 3342292SN/A if (renameStatus[tid] == Blocked || 3352292SN/A renameStatus[tid] == Unblocking || 3362301SN/A renameStatus[tid] == SerializeStall) { 3372698Sktlim@umich.edu 3382292SN/A toDecode->renameUnblock[tid] = 1; 3392698Sktlim@umich.edu 3402301SN/A serializeInst[tid] = NULL; 3412292SN/A } 3422292SN/A 3432292SN/A // Set the status to Squashing. 3442292SN/A renameStatus[tid] = Squashing; 3452292SN/A 3462329SN/A // Squash any instructions from decode. 3472292SN/A unsigned squashCount = 0; 3482292SN/A 3492292SN/A for (int i=0; i<fromDecode->size; i++) { 3502935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3512935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3522731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3532292SN/A wroteToTimeBuffer = true; 3542292SN/A squashCount++; 3552292SN/A } 3562935Sksewell@umich.edu 3572292SN/A } 3582292SN/A 3592935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3602935Sksewell@umich.edu // insts in them. Since we support multiple ISAs, we cant just: 3612935Sksewell@umich.edu // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is 3622935Sksewell@umich.edu // a possible delay slot inst for different architectures 3632935Sksewell@umich.edu // insts[tid].clear(); 3643093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3652935Sksewell@umich.edu DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " 3662935Sksewell@umich.edu "[sn:%i].\n",tid, squash_seq_num); 3672935Sksewell@umich.edu ListIt ilist_it = insts[tid].begin(); 3682935Sksewell@umich.edu while (ilist_it != insts[tid].end()) { 3692935Sksewell@umich.edu if ((*ilist_it)->seqNum > squash_seq_num) { 3702935Sksewell@umich.edu (*ilist_it)->setSquashed(); 3712935Sksewell@umich.edu DPRINTF(Rename, "Squashing incoming decode instruction, " 3722935Sksewell@umich.edu "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC); 3732935Sksewell@umich.edu } 3742935Sksewell@umich.edu ilist_it++; 3752935Sksewell@umich.edu } 3763093Sksewell@umich.edu#else 3773093Sksewell@umich.edu insts[tid].clear(); 3782935Sksewell@umich.edu#endif 3792292SN/A 3802292SN/A // Clear the skid buffer in case it has any data in it. 3812935Sksewell@umich.edu // See comments above. 3822935Sksewell@umich.edu // skidBuffer[tid].clear(); 3833093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3842935Sksewell@umich.edu DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " 3852935Sksewell@umich.edu "until [sn:%i].\n", tid, squash_seq_num); 3862935Sksewell@umich.edu ListIt slist_it = skidBuffer[tid].begin(); 3872935Sksewell@umich.edu while (slist_it != skidBuffer[tid].end()) { 3882935Sksewell@umich.edu if ((*slist_it)->seqNum > squash_seq_num) { 3892935Sksewell@umich.edu (*slist_it)->setSquashed(); 3902935Sksewell@umich.edu DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]" 3912935Sksewell@umich.edu "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC); 3922935Sksewell@umich.edu } 3932935Sksewell@umich.edu slist_it++; 3942935Sksewell@umich.edu } 3953093Sksewell@umich.edu#else 3963093Sksewell@umich.edu skidBuffer[tid].clear(); 3972935Sksewell@umich.edu#endif 3982935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3992292SN/A} 4002292SN/A 4012292SN/Atemplate <class Impl> 4022292SN/Avoid 4032292SN/ADefaultRename<Impl>::tick() 4042292SN/A{ 4052292SN/A wroteToTimeBuffer = false; 4062292SN/A 4072292SN/A blockThisCycle = false; 4082292SN/A 4092292SN/A bool status_change = false; 4102292SN/A 4112292SN/A toIEWIndex = 0; 4122292SN/A 4132292SN/A sortInsts(); 4142292SN/A 4153867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4163867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4172292SN/A 4182292SN/A // Check stall and squash signals. 4193867Sbinkertn@umich.edu while (threads != end) { 4202292SN/A unsigned tid = *threads++; 4212292SN/A 4222292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4232292SN/A 4242292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4252292SN/A 4262292SN/A rename(status_change, tid); 4272292SN/A } 4282292SN/A 4292292SN/A if (status_change) { 4302292SN/A updateStatus(); 4312292SN/A } 4322292SN/A 4332292SN/A if (wroteToTimeBuffer) { 4342292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4352292SN/A cpu->activityThisCycle(); 4362292SN/A } 4372292SN/A 4383867Sbinkertn@umich.edu threads = activeThreads->begin(); 4392292SN/A 4403867Sbinkertn@umich.edu while (threads != end) { 4412292SN/A unsigned tid = *threads++; 4422292SN/A 4432292SN/A // If we committed this cycle then doneSeqNum will be > 0 4442292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4452292SN/A !fromCommit->commitInfo[tid].squash && 4462292SN/A renameStatus[tid] != Squashing) { 4472292SN/A 4482292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4492292SN/A tid); 4502292SN/A } 4512292SN/A } 4522292SN/A 4532292SN/A // @todo: make into updateProgress function 4542292SN/A for (int tid=0; tid < numThreads; tid++) { 4552292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4562292SN/A 4572292SN/A assert(instsInProgress[tid] >=0); 4582292SN/A } 4592292SN/A 4602292SN/A} 4612292SN/A 4622292SN/Atemplate<class Impl> 4632292SN/Avoid 4642292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4652292SN/A{ 4662292SN/A // If status is Running or idle, 4672292SN/A // call renameInsts() 4682292SN/A // If status is Unblocking, 4692292SN/A // buffer any instructions coming from decode 4702292SN/A // continue trying to empty skid buffer 4712292SN/A // check if stall conditions have passed 4722292SN/A 4732292SN/A if (renameStatus[tid] == Blocked) { 4742292SN/A ++renameBlockCycles; 4752292SN/A } else if (renameStatus[tid] == Squashing) { 4762292SN/A ++renameSquashCycles; 4772301SN/A } else if (renameStatus[tid] == SerializeStall) { 4782301SN/A ++renameSerializeStallCycles; 4792292SN/A } 4802292SN/A 4812292SN/A if (renameStatus[tid] == Running || 4822292SN/A renameStatus[tid] == Idle) { 4832292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4842292SN/A "stage.\n", tid); 4852292SN/A 4862292SN/A renameInsts(tid); 4872292SN/A } else if (renameStatus[tid] == Unblocking) { 4882292SN/A renameInsts(tid); 4892292SN/A 4902292SN/A if (validInsts()) { 4912292SN/A // Add the current inputs to the skid buffer so they can be 4922292SN/A // reprocessed when this stage unblocks. 4932292SN/A skidInsert(tid); 4942292SN/A } 4952292SN/A 4962292SN/A // If we switched over to blocking, then there's a potential for 4972292SN/A // an overall status change. 4982292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4991858SN/A } 5001858SN/A} 5011858SN/A 5021858SN/Atemplate <class Impl> 5031858SN/Avoid 5042292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 5051858SN/A{ 5062292SN/A // Instructions can be either in the skid buffer or the queue of 5072292SN/A // instructions coming from decode, depending on the status. 5082292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5092292SN/A skidBuffer[tid].size() : insts[tid].size(); 5101858SN/A 5112292SN/A // Check the decode queue to see if instructions are available. 5122292SN/A // If there are no available instructions to rename, then do nothing. 5132292SN/A if (insts_available == 0) { 5142292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5152292SN/A tid); 5162292SN/A // Should I change status to idle? 5172292SN/A ++renameIdleCycles; 5182292SN/A return; 5192292SN/A } else if (renameStatus[tid] == Unblocking) { 5202292SN/A ++renameUnblockCycles; 5212292SN/A } else if (renameStatus[tid] == Running) { 5222292SN/A ++renameRunCycles; 5232292SN/A } 5241858SN/A 5252292SN/A DynInstPtr inst; 5262292SN/A 5272292SN/A // Will have to do a different calculation for the number of free 5282292SN/A // entries. 5292292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5302292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5312292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5322292SN/A int min_free_entries = free_rob_entries; 5332292SN/A 5342292SN/A FullSource source = ROB; 5352292SN/A 5362292SN/A if (free_iq_entries < min_free_entries) { 5372292SN/A min_free_entries = free_iq_entries; 5382292SN/A source = IQ; 5392292SN/A } 5402292SN/A 5412292SN/A if (free_lsq_entries < min_free_entries) { 5422292SN/A min_free_entries = free_lsq_entries; 5432292SN/A source = LSQ; 5442292SN/A } 5452292SN/A 5462292SN/A // Check if there's any space left. 5472292SN/A if (min_free_entries <= 0) { 5482292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5492292SN/A "entries.\n" 5502292SN/A "ROB has %i free entries.\n" 5512292SN/A "IQ has %i free entries.\n" 5522292SN/A "LSQ has %i free entries.\n", 5532292SN/A tid, 5542292SN/A free_rob_entries, 5552292SN/A free_iq_entries, 5562292SN/A free_lsq_entries); 5572292SN/A 5582292SN/A blockThisCycle = true; 5592292SN/A 5602292SN/A block(tid); 5612292SN/A 5622292SN/A incrFullStat(source); 5632292SN/A 5642292SN/A return; 5652292SN/A } else if (min_free_entries < insts_available) { 5662292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5672292SN/A "%i insts available, but only %i insts can be " 5682292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5692292SN/A tid, insts_available, min_free_entries); 5702292SN/A 5712292SN/A insts_available = min_free_entries; 5722292SN/A 5732292SN/A blockThisCycle = true; 5742292SN/A 5752292SN/A incrFullStat(source); 5762292SN/A } 5772292SN/A 5782292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5792292SN/A skidBuffer[tid] : insts[tid]; 5802292SN/A 5812292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5822292SN/A "send iew.\n", tid, insts_available); 5832292SN/A 5842292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5852292SN/A "dispatched to IQ last cycle.\n", 5862292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5872292SN/A 5882292SN/A // Handle serializing the next instruction if necessary. 5892292SN/A if (serializeOnNextInst[tid]) { 5902292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5912292SN/A // ROB already empty; no need to serialize. 5922292SN/A serializeOnNextInst[tid] = false; 5932292SN/A } else if (!insts_to_rename.empty()) { 5942292SN/A insts_to_rename.front()->setSerializeBefore(); 5952292SN/A } 5962292SN/A } 5972292SN/A 5982292SN/A int renamed_insts = 0; 5992292SN/A 6002292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6012292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6022292SN/A 6032292SN/A assert(!insts_to_rename.empty()); 6042292SN/A 6052292SN/A inst = insts_to_rename.front(); 6062292SN/A 6072292SN/A insts_to_rename.pop_front(); 6082292SN/A 6092292SN/A if (renameStatus[tid] == Unblocking) { 6102292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 6112292SN/A "skidBuffer\n", 6122292SN/A tid, inst->seqNum, inst->readPC()); 6132292SN/A } 6142292SN/A 6152292SN/A if (inst->isSquashed()) { 6162292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 6172292SN/A "squashed, skipping.\n", 6182935Sksewell@umich.edu tid, inst->seqNum, inst->readPC()); 6192292SN/A 6202292SN/A ++renameSquashedInsts; 6212292SN/A 6222292SN/A // Decrement how many instructions are available. 6232292SN/A --insts_available; 6242292SN/A 6252292SN/A continue; 6262292SN/A } 6272292SN/A 6282292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6292292SN/A "PC %#x.\n", 6302292SN/A tid, inst->seqNum, inst->readPC()); 6312292SN/A 6322292SN/A // Handle serializeAfter/serializeBefore instructions. 6332292SN/A // serializeAfter marks the next instruction as serializeBefore. 6342292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6352292SN/A // is empty. 6362336SN/A 6372336SN/A // In this model, IPR accesses are serialize before 6382336SN/A // instructions, and store conditionals are serialize after 6392336SN/A // instructions. This is mainly due to lack of support for 6402336SN/A // out-of-order operations of either of those classes of 6412336SN/A // instructions. 6422336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6432336SN/A !inst->isSerializeHandled()) { 6442292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6452292SN/A 6462301SN/A if (!inst->isTempSerializeBefore()) { 6472301SN/A renamedSerializing++; 6482292SN/A inst->setSerializeHandled(); 6492301SN/A } else { 6502301SN/A renamedTempSerializing++; 6512301SN/A } 6522292SN/A 6532301SN/A // Change status over to SerializeStall so that other stages know 6542292SN/A // what this is blocked on. 6552301SN/A renameStatus[tid] = SerializeStall; 6562292SN/A 6572301SN/A serializeInst[tid] = inst; 6582292SN/A 6592292SN/A blockThisCycle = true; 6602292SN/A 6612292SN/A break; 6622336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6632336SN/A !inst->isSerializeHandled()) { 6642292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6652292SN/A 6662307SN/A renamedSerializing++; 6672307SN/A 6682292SN/A inst->setSerializeHandled(); 6692292SN/A 6702292SN/A serializeAfter(insts_to_rename, tid); 6712292SN/A } 6722292SN/A 6732292SN/A // Check here to make sure there are enough destination registers 6742292SN/A // to rename to. Otherwise block. 6752292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6762292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6772292SN/A "physical registers to rename to.\n"); 6782292SN/A blockThisCycle = true; 6792292SN/A 6802292SN/A ++renameFullRegistersEvents; 6812292SN/A 6822292SN/A break; 6832292SN/A } 6842292SN/A 6852292SN/A renameSrcRegs(inst, inst->threadNumber); 6862292SN/A 6872292SN/A renameDestRegs(inst, inst->threadNumber); 6882292SN/A 6892292SN/A ++renamed_insts; 6902292SN/A 6912292SN/A // Put instruction in rename queue. 6922292SN/A toIEW->insts[toIEWIndex] = inst; 6932292SN/A ++(toIEW->size); 6942292SN/A 6952292SN/A // Increment which instruction we're on. 6962292SN/A ++toIEWIndex; 6972292SN/A 6982292SN/A // Decrement how many instructions are available. 6992292SN/A --insts_available; 7002292SN/A } 7012292SN/A 7022292SN/A instsInProgress[tid] += renamed_insts; 7032307SN/A renameRenamedInsts += renamed_insts; 7042292SN/A 7052292SN/A // If we wrote to the time buffer, record this. 7062292SN/A if (toIEWIndex) { 7072292SN/A wroteToTimeBuffer = true; 7082292SN/A } 7092292SN/A 7102292SN/A // Check if there's any instructions left that haven't yet been renamed. 7112292SN/A // If so then block. 7122292SN/A if (insts_available) { 7132292SN/A blockThisCycle = true; 7142292SN/A } 7152292SN/A 7162292SN/A if (blockThisCycle) { 7172292SN/A block(tid); 7182292SN/A toDecode->renameUnblock[tid] = false; 7192292SN/A } 7202292SN/A} 7212292SN/A 7222292SN/Atemplate<class Impl> 7232292SN/Avoid 7242292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 7252292SN/A{ 7262292SN/A DynInstPtr inst = NULL; 7272292SN/A 7282292SN/A while (!insts[tid].empty()) { 7292292SN/A inst = insts[tid].front(); 7302292SN/A 7312292SN/A insts[tid].pop_front(); 7322292SN/A 7332292SN/A assert(tid == inst->threadNumber); 7342292SN/A 7352292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 7362292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 7372292SN/A 7382307SN/A ++renameSkidInsts; 7392307SN/A 7402292SN/A skidBuffer[tid].push_back(inst); 7412292SN/A } 7422292SN/A 7432292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7442292SN/A panic("Skidbuffer Exceeded Max Size"); 7452292SN/A} 7462292SN/A 7472292SN/Atemplate <class Impl> 7482292SN/Avoid 7492292SN/ADefaultRename<Impl>::sortInsts() 7502292SN/A{ 7512292SN/A int insts_from_decode = fromDecode->size; 7522329SN/A#ifdef DEBUG 7533093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT 7542292SN/A for (int i=0; i < numThreads; i++) 7552292SN/A assert(insts[i].empty()); 7562329SN/A#endif 7572935Sksewell@umich.edu#endif 7582292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7592292SN/A DynInstPtr inst = fromDecode->insts[i]; 7602292SN/A insts[inst->threadNumber].push_back(inst); 7612292SN/A } 7622292SN/A} 7632292SN/A 7642292SN/Atemplate<class Impl> 7652292SN/Abool 7662292SN/ADefaultRename<Impl>::skidsEmpty() 7672292SN/A{ 7683867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7693867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7702292SN/A 7713867Sbinkertn@umich.edu while (threads != end) { 7723867Sbinkertn@umich.edu unsigned tid = *threads++; 7733867Sbinkertn@umich.edu 7743867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7752292SN/A return false; 7762292SN/A } 7772292SN/A 7782292SN/A return true; 7792292SN/A} 7802292SN/A 7812292SN/Atemplate<class Impl> 7822292SN/Avoid 7832292SN/ADefaultRename<Impl>::updateStatus() 7842292SN/A{ 7852292SN/A bool any_unblocking = false; 7862292SN/A 7873867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7883867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7892292SN/A 7903867Sbinkertn@umich.edu while (threads != end) { 7912292SN/A unsigned tid = *threads++; 7922292SN/A 7932292SN/A if (renameStatus[tid] == Unblocking) { 7942292SN/A any_unblocking = true; 7952292SN/A break; 7962292SN/A } 7972292SN/A } 7982292SN/A 7992292SN/A // Rename will have activity if it's unblocking. 8002292SN/A if (any_unblocking) { 8012292SN/A if (_status == Inactive) { 8022292SN/A _status = Active; 8032292SN/A 8042292SN/A DPRINTF(Activity, "Activating stage.\n"); 8052292SN/A 8062733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8072292SN/A } 8082292SN/A } else { 8092292SN/A // If it's not unblocking, then rename will not have any internal 8102292SN/A // activity. Switch it to inactive. 8112292SN/A if (_status == Active) { 8122292SN/A _status = Inactive; 8132292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8142292SN/A 8152733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8162292SN/A } 8172292SN/A } 8182292SN/A} 8192292SN/A 8202292SN/Atemplate <class Impl> 8212292SN/Abool 8222292SN/ADefaultRename<Impl>::block(unsigned tid) 8232292SN/A{ 8242292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8252292SN/A 8262292SN/A // Add the current inputs onto the skid buffer, so they can be 8272292SN/A // reprocessed when this stage unblocks. 8282292SN/A skidInsert(tid); 8292292SN/A 8302292SN/A // Only signal backwards to block if the previous stages do not think 8312292SN/A // rename is already blocked. 8322292SN/A if (renameStatus[tid] != Blocked) { 8332292SN/A if (renameStatus[tid] != Unblocking) { 8342292SN/A toDecode->renameBlock[tid] = true; 8352292SN/A toDecode->renameUnblock[tid] = false; 8362292SN/A wroteToTimeBuffer = true; 8372292SN/A } 8382292SN/A 8392329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8402329SN/A // it would not know to complete the serialize stall. 8412301SN/A if (renameStatus[tid] != SerializeStall) { 8422292SN/A // Set status to Blocked. 8432292SN/A renameStatus[tid] = Blocked; 8442292SN/A return true; 8452292SN/A } 8462292SN/A } 8472292SN/A 8482292SN/A return false; 8492292SN/A} 8502292SN/A 8512292SN/Atemplate <class Impl> 8522292SN/Abool 8532292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8542292SN/A{ 8552292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8562292SN/A 8572292SN/A // Rename is done unblocking if the skid buffer is empty. 8582301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8592292SN/A 8602292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8612292SN/A 8622292SN/A toDecode->renameUnblock[tid] = true; 8632292SN/A wroteToTimeBuffer = true; 8642292SN/A 8652292SN/A renameStatus[tid] = Running; 8662292SN/A return true; 8672292SN/A } 8682292SN/A 8692292SN/A return false; 8702292SN/A} 8712292SN/A 8722292SN/Atemplate <class Impl> 8732292SN/Avoid 8742935Sksewell@umich.eduDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 8752292SN/A{ 8762980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8772980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8782292SN/A 8791060SN/A // After a syscall squashes everything, the history buffer may be empty 8801060SN/A // but the ROB may still be squashing instructions. 8812292SN/A if (historyBuffer[tid].empty()) { 8821060SN/A return; 8831060SN/A } 8841060SN/A 8851060SN/A // Go through the most recent instructions, undoing the mappings 8861060SN/A // they did and freeing up the registers. 8872292SN/A while (!historyBuffer[tid].empty() && 8882292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8892292SN/A assert(hb_it != historyBuffer[tid].end()); 8901062SN/A 8912292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8922292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8931060SN/A 8942292SN/A // Tell the rename map to set the architected register to the 8952292SN/A // previous physical register that it was renamed to. 8962292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8971060SN/A 8982292SN/A // Put the renamed physical register back on the free list. 8992292SN/A freeList->addReg(hb_it->newPhysReg); 9001062SN/A 9012367SN/A // Be sure to mark its register as ready if it's a misc register. 9022367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9032367SN/A scoreboard->setReg(hb_it->newPhysReg); 9042367SN/A } 9052367SN/A 9062292SN/A historyBuffer[tid].erase(hb_it++); 9071061SN/A 9081062SN/A ++renameUndoneMaps; 9091060SN/A } 9101060SN/A} 9111060SN/A 9121060SN/Atemplate<class Impl> 9131060SN/Avoid 9142292SN/ADefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 9151060SN/A{ 9162292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9172292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9182292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9192292SN/A 9202980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9212980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9221060SN/A 9231061SN/A --hb_it; 9241060SN/A 9252292SN/A if (historyBuffer[tid].empty()) { 9262292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9272292SN/A return; 9282292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9292292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9302292SN/A "that a syscall happened recently.\n", tid); 9311060SN/A return; 9321060SN/A } 9331060SN/A 9342292SN/A // Commit all the renames up until (and including) the committed sequence 9352292SN/A // number. Some or even all of the committed instructions may not have 9362292SN/A // rename histories if they did not have destination registers that were 9372292SN/A // renamed. 9382292SN/A while (!historyBuffer[tid].empty() && 9392292SN/A hb_it != historyBuffer[tid].end() && 9402292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9411060SN/A 9422329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9432329SN/A "[sn:%lli].\n", 9442292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9451061SN/A 9462292SN/A freeList->addReg((*hb_it).prevPhysReg); 9472292SN/A ++renameCommittedMaps; 9481061SN/A 9492292SN/A historyBuffer[tid].erase(hb_it--); 9501060SN/A } 9511060SN/A} 9521060SN/A 9531061SN/Atemplate <class Impl> 9541061SN/Ainline void 9552292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9561061SN/A{ 9572292SN/A assert(renameMap[tid] != 0); 9582292SN/A 9591061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9601061SN/A 9611061SN/A // Get the architectual register numbers from the source and 9621061SN/A // destination operands, and redirect them to the right register. 9631061SN/A // Will need to mark dependencies though. 9642292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9651061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9661061SN/A 9671061SN/A // Look up the source registers to get the phys. register they've 9681061SN/A // been renamed to, and set the sources to those registers. 9692292SN/A PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 9701061SN/A 9712292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9722292SN/A "physical reg %i.\n", tid, (int)src_reg, 9732292SN/A (int)renamed_reg); 9741061SN/A 9751061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9761061SN/A 9772292SN/A // See if the register is ready or not. 9782292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9792292SN/A DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 9801061SN/A 9811061SN/A inst->markSrcRegReady(src_idx); 9821061SN/A } 9831062SN/A 9841062SN/A ++renameRenameLookups; 9851061SN/A } 9861061SN/A} 9871061SN/A 9881061SN/Atemplate <class Impl> 9891061SN/Ainline void 9902292SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 9911061SN/A{ 9922292SN/A typename RenameMap::RenameInfo rename_result; 9931061SN/A 9941061SN/A unsigned num_dest_regs = inst->numDestRegs(); 9951061SN/A 9962292SN/A // Rename the destination registers. 9972292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 9982292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 9991061SN/A 10002292SN/A // Get the physical register that the destination will be 10012292SN/A // renamed to. 10022292SN/A rename_result = renameMap[tid]->rename(dest_reg); 10031061SN/A 10042292SN/A //Mark Scoreboard entry as not ready 10052292SN/A scoreboard->unsetReg(rename_result.first); 10061062SN/A 10072292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10082292SN/A "reg %i.\n", tid, (int)dest_reg, 10092292SN/A (int)rename_result.first); 10101062SN/A 10112292SN/A // Record the rename information so that a history can be kept. 10122292SN/A RenameHistory hb_entry(inst->seqNum, dest_reg, 10132292SN/A rename_result.first, 10142292SN/A rename_result.second); 10151062SN/A 10162292SN/A historyBuffer[tid].push_front(hb_entry); 10171062SN/A 10182935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10192935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10202935Sksewell@umich.edu historyBuffer[tid].size(), 10212292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10221062SN/A 10232292SN/A // Tell the instruction to rename the appropriate destination 10242292SN/A // register (dest_idx) to the new physical register 10252292SN/A // (rename_result.first), and record the previous physical 10262292SN/A // register that the same logical register was renamed to 10272292SN/A // (rename_result.second). 10282292SN/A inst->renameDestReg(dest_idx, 10292292SN/A rename_result.first, 10302292SN/A rename_result.second); 10311062SN/A 10322292SN/A ++renameRenamedOperands; 10331061SN/A } 10341061SN/A} 10351061SN/A 10361061SN/Atemplate <class Impl> 10371061SN/Ainline int 10382292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 10391061SN/A{ 10402292SN/A int num_free = freeEntries[tid].robEntries - 10412292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10422292SN/A 10432292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10442292SN/A 10452292SN/A return num_free; 10461061SN/A} 10471061SN/A 10481061SN/Atemplate <class Impl> 10491061SN/Ainline int 10502292SN/ADefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 10511061SN/A{ 10522292SN/A int num_free = freeEntries[tid].iqEntries - 10532292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10542292SN/A 10552292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10562292SN/A 10572292SN/A return num_free; 10582292SN/A} 10592292SN/A 10602292SN/Atemplate <class Impl> 10612292SN/Ainline int 10622292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 10632292SN/A{ 10642292SN/A int num_free = freeEntries[tid].lsqEntries - 10652292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10662292SN/A 10672292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 10682292SN/A 10692292SN/A return num_free; 10702292SN/A} 10712292SN/A 10722292SN/Atemplate <class Impl> 10732292SN/Aunsigned 10742292SN/ADefaultRename<Impl>::validInsts() 10752292SN/A{ 10762292SN/A unsigned inst_count = 0; 10772292SN/A 10782292SN/A for (int i=0; i<fromDecode->size; i++) { 10792731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 10802292SN/A inst_count++; 10812292SN/A } 10822292SN/A 10832292SN/A return inst_count; 10842292SN/A} 10852292SN/A 10862292SN/Atemplate <class Impl> 10872292SN/Avoid 10882292SN/ADefaultRename<Impl>::readStallSignals(unsigned tid) 10892292SN/A{ 10902292SN/A if (fromIEW->iewBlock[tid]) { 10912292SN/A stalls[tid].iew = true; 10922292SN/A } 10932292SN/A 10942292SN/A if (fromIEW->iewUnblock[tid]) { 10952292SN/A assert(stalls[tid].iew); 10962292SN/A stalls[tid].iew = false; 10972292SN/A } 10982292SN/A 10992292SN/A if (fromCommit->commitBlock[tid]) { 11002292SN/A stalls[tid].commit = true; 11012292SN/A } 11022292SN/A 11032292SN/A if (fromCommit->commitUnblock[tid]) { 11042292SN/A assert(stalls[tid].commit); 11052292SN/A stalls[tid].commit = false; 11062292SN/A } 11072292SN/A} 11082292SN/A 11092292SN/Atemplate <class Impl> 11102292SN/Abool 11112292SN/ADefaultRename<Impl>::checkStall(unsigned tid) 11122292SN/A{ 11132292SN/A bool ret_val = false; 11142292SN/A 11152292SN/A if (stalls[tid].iew) { 11162292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11172292SN/A ret_val = true; 11182292SN/A } else if (stalls[tid].commit) { 11192292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11202292SN/A ret_val = true; 11212292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11222292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11232292SN/A ret_val = true; 11242292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11252292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11262292SN/A ret_val = true; 11272292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11282292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11292292SN/A ret_val = true; 11302292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11312292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11322292SN/A ret_val = true; 11332301SN/A } else if (renameStatus[tid] == SerializeStall && 11342292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11352301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11362292SN/A "empty.\n", 11372292SN/A tid); 11382292SN/A ret_val = true; 11392292SN/A } 11402292SN/A 11412292SN/A return ret_val; 11422292SN/A} 11432292SN/A 11442292SN/Atemplate <class Impl> 11452292SN/Avoid 11462292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 11472292SN/A{ 11482292SN/A bool updated = false; 11492292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 11502292SN/A freeEntries[tid].iqEntries = 11512292SN/A fromIEW->iewInfo[tid].freeIQEntries; 11522292SN/A updated = true; 11532292SN/A } 11542292SN/A 11552292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11562292SN/A freeEntries[tid].lsqEntries = 11572292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 11582292SN/A updated = true; 11592292SN/A } 11602292SN/A 11612292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11622292SN/A freeEntries[tid].robEntries = 11632292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11642292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11652292SN/A updated = true; 11662292SN/A } 11672292SN/A 11682292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11692292SN/A tid, 11702292SN/A freeEntries[tid].iqEntries, 11712292SN/A freeEntries[tid].robEntries, 11722292SN/A freeEntries[tid].lsqEntries); 11732292SN/A 11742292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 11752292SN/A tid, instsInProgress[tid]); 11762292SN/A} 11772292SN/A 11782292SN/Atemplate <class Impl> 11792292SN/Abool 11802292SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 11812292SN/A{ 11822292SN/A // Check if there's a squash signal, squash if there is 11832292SN/A // Check stall signals, block if necessary. 11842292SN/A // If status was blocked 11852292SN/A // check if stall conditions have passed 11862292SN/A // if so then go to unblocking 11872292SN/A // If status was Squashing 11882292SN/A // check if squashing is not high. Switch to running this cycle. 11892301SN/A // If status was serialize stall 11902292SN/A // check if ROB is empty and no insts are in flight to the ROB 11912292SN/A 11922292SN/A readFreeEntries(tid); 11932292SN/A readStallSignals(tid); 11942292SN/A 11952292SN/A if (fromCommit->commitInfo[tid].squash) { 11962292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 11972292SN/A "commit.\n", tid); 11982292SN/A 11993093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 12003093Sksewell@umich.edu InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 12013093Sksewell@umich.edu#else 12022935Sksewell@umich.edu InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 12032935Sksewell@umich.edu#endif 12042935Sksewell@umich.edu 12052935Sksewell@umich.edu squash(squashed_seq_num, tid); 12062292SN/A 12072292SN/A return true; 12082292SN/A } 12092292SN/A 12102292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12112292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12122292SN/A 12132292SN/A renameStatus[tid] = Squashing; 12142292SN/A 12152292SN/A return true; 12162292SN/A } 12172292SN/A 12182292SN/A if (checkStall(tid)) { 12192292SN/A return block(tid); 12202292SN/A } 12212292SN/A 12222292SN/A if (renameStatus[tid] == Blocked) { 12232292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12242292SN/A tid); 12252292SN/A 12262292SN/A renameStatus[tid] = Unblocking; 12272292SN/A 12282292SN/A unblock(tid); 12292292SN/A 12302292SN/A return true; 12312292SN/A } 12322292SN/A 12332292SN/A if (renameStatus[tid] == Squashing) { 12342292SN/A // Switch status to running if rename isn't being told to block or 12352292SN/A // squash this cycle. 12362292SN/A DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12372292SN/A tid); 12382292SN/A 12392292SN/A renameStatus[tid] = Running; 12402292SN/A 12412292SN/A return false; 12422292SN/A } 12432292SN/A 12442301SN/A if (renameStatus[tid] == SerializeStall) { 12452292SN/A // Stall ends once the ROB is free. 12462301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 12472292SN/A "unblocking.\n", tid); 12482292SN/A 12492301SN/A DynInstPtr serial_inst = serializeInst[tid]; 12502292SN/A 12512292SN/A renameStatus[tid] = Unblocking; 12522292SN/A 12532292SN/A unblock(tid); 12542292SN/A 12552292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 12562292SN/A "PC %#x.\n", 12572301SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 12582292SN/A 12592292SN/A // Put instruction into queue here. 12602301SN/A serial_inst->clearSerializeBefore(); 12612292SN/A 12622292SN/A if (!skidBuffer[tid].empty()) { 12632301SN/A skidBuffer[tid].push_front(serial_inst); 12642292SN/A } else { 12652301SN/A insts[tid].push_front(serial_inst); 12662292SN/A } 12672292SN/A 12682292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 12692703Sktlim@umich.edu " Adding to front of list.\n", tid); 12702292SN/A 12712301SN/A serializeInst[tid] = NULL; 12722292SN/A 12732292SN/A return true; 12742292SN/A } 12752292SN/A 12762292SN/A // If we've reached this point, we have not gotten any signals that 12772292SN/A // cause rename to change its status. Rename remains the same as before. 12782292SN/A return false; 12791061SN/A} 12801061SN/A 12811060SN/Atemplate<class Impl> 12821060SN/Avoid 12832292SN/ADefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 12842292SN/A unsigned tid) 12851060SN/A{ 12862292SN/A if (inst_list.empty()) { 12872292SN/A // Mark a bit to say that I must serialize on the next instruction. 12882292SN/A serializeOnNextInst[tid] = true; 12891060SN/A return; 12901060SN/A } 12911060SN/A 12922292SN/A // Set the next instruction as serializing. 12932292SN/A inst_list.front()->setSerializeBefore(); 12942292SN/A} 12952292SN/A 12962292SN/Atemplate <class Impl> 12972292SN/Ainline void 12982292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 12992292SN/A{ 13002292SN/A switch (source) { 13012292SN/A case ROB: 13022292SN/A ++renameROBFullEvents; 13032292SN/A break; 13042292SN/A case IQ: 13052292SN/A ++renameIQFullEvents; 13062292SN/A break; 13072292SN/A case LSQ: 13082292SN/A ++renameLSQFullEvents; 13092292SN/A break; 13102292SN/A default: 13112292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13122292SN/A break; 13131060SN/A } 13142292SN/A} 13151060SN/A 13162292SN/Atemplate <class Impl> 13172292SN/Avoid 13182292SN/ADefaultRename<Impl>::dumpHistory() 13192292SN/A{ 13202980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13211060SN/A 13222292SN/A for (int i = 0; i < numThreads; i++) { 13231060SN/A 13242292SN/A buf_it = historyBuffer[i].begin(); 13251060SN/A 13262292SN/A while (buf_it != historyBuffer[i].end()) { 13272292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13282292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13292292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13301060SN/A 13312292SN/A buf_it++; 13321062SN/A } 13331060SN/A } 13341060SN/A} 1335