rename_impl.hh revision 3773
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292935Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321060SN/A#include <list> 331060SN/A 343773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 353773Sgblack@eecs.umich.edu#include "arch/regfile.hh" 361858SN/A#include "config/full_system.hh" 371717SN/A#include "cpu/o3/rename.hh" 381060SN/A 391061SN/Atemplate <class Impl> 402292SN/ADefaultRename<Impl>::DefaultRename(Params *params) 412292SN/A : iewToRenameDelay(params->iewToRenameDelay), 422292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 432292SN/A commitToRenameDelay(params->commitToRenameDelay), 442292SN/A renameWidth(params->renameWidth), 452292SN/A commitWidth(params->commitWidth), 462361SN/A numThreads(params->numberOfThreads), 472361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 481060SN/A{ 492292SN/A _status = Inactive; 502292SN/A 512292SN/A for (int i=0; i< numThreads; i++) { 522292SN/A renameStatus[i] = Idle; 532292SN/A 542292SN/A freeEntries[i].iqEntries = 0; 552292SN/A freeEntries[i].lsqEntries = 0; 562292SN/A freeEntries[i].robEntries = 0; 572292SN/A 582292SN/A stalls[i].iew = false; 592292SN/A stalls[i].commit = false; 602301SN/A serializeInst[i] = NULL; 612292SN/A 622292SN/A instsInProgress[i] = 0; 632292SN/A 642292SN/A emptyROB[i] = true; 652292SN/A 662292SN/A serializeOnNextInst[i] = false; 672292SN/A } 682292SN/A 692292SN/A // @todo: Make into a parameter. 702292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 712292SN/A} 722292SN/A 732292SN/Atemplate <class Impl> 742292SN/Astd::string 752292SN/ADefaultRename<Impl>::name() const 762292SN/A{ 772292SN/A return cpu->name() + ".rename"; 781060SN/A} 791060SN/A 801061SN/Atemplate <class Impl> 811060SN/Avoid 822292SN/ADefaultRename<Impl>::regStats() 831062SN/A{ 841062SN/A renameSquashCycles 852301SN/A .name(name() + ".RENAME:SquashCycles") 861062SN/A .desc("Number of cycles rename is squashing") 871062SN/A .prereq(renameSquashCycles); 881062SN/A renameIdleCycles 892301SN/A .name(name() + ".RENAME:IdleCycles") 901062SN/A .desc("Number of cycles rename is idle") 911062SN/A .prereq(renameIdleCycles); 921062SN/A renameBlockCycles 932301SN/A .name(name() + ".RENAME:BlockCycles") 941062SN/A .desc("Number of cycles rename is blocking") 951062SN/A .prereq(renameBlockCycles); 962301SN/A renameSerializeStallCycles 972301SN/A .name(name() + ".RENAME:serializeStallCycles") 982301SN/A .desc("count of cycles rename stalled for serializing inst") 992301SN/A .flags(Stats::total); 1002292SN/A renameRunCycles 1012301SN/A .name(name() + ".RENAME:RunCycles") 1022292SN/A .desc("Number of cycles rename is running") 1032292SN/A .prereq(renameIdleCycles); 1041062SN/A renameUnblockCycles 1052301SN/A .name(name() + ".RENAME:UnblockCycles") 1061062SN/A .desc("Number of cycles rename is unblocking") 1071062SN/A .prereq(renameUnblockCycles); 1081062SN/A renameRenamedInsts 1092301SN/A .name(name() + ".RENAME:RenamedInsts") 1101062SN/A .desc("Number of instructions processed by rename") 1111062SN/A .prereq(renameRenamedInsts); 1121062SN/A renameSquashedInsts 1132301SN/A .name(name() + ".RENAME:SquashedInsts") 1141062SN/A .desc("Number of squashed instructions processed by rename") 1151062SN/A .prereq(renameSquashedInsts); 1161062SN/A renameROBFullEvents 1172301SN/A .name(name() + ".RENAME:ROBFullEvents") 1182292SN/A .desc("Number of times rename has blocked due to ROB full") 1191062SN/A .prereq(renameROBFullEvents); 1201062SN/A renameIQFullEvents 1212301SN/A .name(name() + ".RENAME:IQFullEvents") 1222292SN/A .desc("Number of times rename has blocked due to IQ full") 1231062SN/A .prereq(renameIQFullEvents); 1242292SN/A renameLSQFullEvents 1252301SN/A .name(name() + ".RENAME:LSQFullEvents") 1262292SN/A .desc("Number of times rename has blocked due to LSQ full") 1272292SN/A .prereq(renameLSQFullEvents); 1281062SN/A renameFullRegistersEvents 1292301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1301062SN/A .desc("Number of times there has been no free registers") 1311062SN/A .prereq(renameFullRegistersEvents); 1321062SN/A renameRenamedOperands 1332301SN/A .name(name() + ".RENAME:RenamedOperands") 1341062SN/A .desc("Number of destination operands rename has renamed") 1351062SN/A .prereq(renameRenamedOperands); 1361062SN/A renameRenameLookups 1372301SN/A .name(name() + ".RENAME:RenameLookups") 1381062SN/A .desc("Number of register rename lookups that rename has made") 1391062SN/A .prereq(renameRenameLookups); 1401062SN/A renameCommittedMaps 1412301SN/A .name(name() + ".RENAME:CommittedMaps") 1421062SN/A .desc("Number of HB maps that are committed") 1431062SN/A .prereq(renameCommittedMaps); 1441062SN/A renameUndoneMaps 1452301SN/A .name(name() + ".RENAME:UndoneMaps") 1461062SN/A .desc("Number of HB maps that are undone due to squashing") 1471062SN/A .prereq(renameUndoneMaps); 1482301SN/A renamedSerializing 1492301SN/A .name(name() + ".RENAME:serializingInsts") 1502301SN/A .desc("count of serializing insts renamed") 1512301SN/A .flags(Stats::total) 1522301SN/A ; 1532301SN/A renamedTempSerializing 1542301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1552301SN/A .desc("count of temporary serializing insts renamed") 1562301SN/A .flags(Stats::total) 1572301SN/A ; 1582307SN/A renameSkidInsts 1592307SN/A .name(name() + ".RENAME:skidInsts") 1602307SN/A .desc("count of insts added to the skid buffer") 1612307SN/A .flags(Stats::total) 1622307SN/A ; 1631062SN/A} 1641062SN/A 1651062SN/Atemplate <class Impl> 1661062SN/Avoid 1672733Sktlim@umich.eduDefaultRename<Impl>::setCPU(O3CPU *cpu_ptr) 1681060SN/A{ 1692292SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1701060SN/A cpu = cpu_ptr; 1711060SN/A} 1721060SN/A 1731061SN/Atemplate <class Impl> 1741060SN/Avoid 1752292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1761060SN/A{ 1772292SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1781060SN/A timeBuffer = tb_ptr; 1791060SN/A 1801060SN/A // Setup wire to read information from time buffer, from IEW stage. 1811060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1821060SN/A 1831060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1841060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1851060SN/A 1861060SN/A // Setup wire to write information to previous stages. 1871060SN/A toDecode = timeBuffer->getWire(0); 1881060SN/A} 1891060SN/A 1901061SN/Atemplate <class Impl> 1911060SN/Avoid 1922292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1931060SN/A{ 1942292SN/A DPRINTF(Rename, "Setting rename queue pointer.\n"); 1951060SN/A renameQueue = rq_ptr; 1961060SN/A 1971060SN/A // Setup wire to write information to future stages. 1981060SN/A toIEW = renameQueue->getWire(0); 1991060SN/A} 2001060SN/A 2011061SN/Atemplate <class Impl> 2021060SN/Avoid 2032292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2041060SN/A{ 2052292SN/A DPRINTF(Rename, "Setting decode queue pointer.\n"); 2061060SN/A decodeQueue = dq_ptr; 2071060SN/A 2081060SN/A // Setup wire to get information from decode. 2091060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2101060SN/A} 2111060SN/A 2121061SN/Atemplate <class Impl> 2131060SN/Avoid 2142292SN/ADefaultRename<Impl>::initStage() 2151060SN/A{ 2162329SN/A // Grab the number of free entries directly from the stages. 2172292SN/A for (int tid=0; tid < numThreads; tid++) { 2182292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2192292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2202292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2212292SN/A emptyROB[tid] = true; 2222292SN/A } 2231060SN/A} 2241060SN/A 2252292SN/Atemplate<class Impl> 2262292SN/Avoid 2272980Sgblack@eecs.umich.eduDefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2282292SN/A{ 2292292SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2302292SN/A activeThreads = at_ptr; 2312292SN/A} 2322292SN/A 2332292SN/A 2341061SN/Atemplate <class Impl> 2351060SN/Avoid 2362292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2371060SN/A{ 2382292SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2391060SN/A 2402292SN/A for (int i=0; i<numThreads; i++) { 2412292SN/A renameMap[i] = &rm_ptr[i]; 2421060SN/A } 2431060SN/A} 2441060SN/A 2451061SN/Atemplate <class Impl> 2461060SN/Avoid 2472292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2481060SN/A{ 2492292SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2502292SN/A freeList = fl_ptr; 2512292SN/A} 2521060SN/A 2532292SN/Atemplate<class Impl> 2542292SN/Avoid 2552292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2562292SN/A{ 2572292SN/A DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2582292SN/A scoreboard = _scoreboard; 2591060SN/A} 2601060SN/A 2611061SN/Atemplate <class Impl> 2622863Sktlim@umich.edubool 2632843Sktlim@umich.eduDefaultRename<Impl>::drain() 2641060SN/A{ 2652348SN/A // Rename is ready to switch out at any time. 2662843Sktlim@umich.edu cpu->signalDrained(); 2672863Sktlim@umich.edu return true; 2682316SN/A} 2691060SN/A 2702316SN/Atemplate <class Impl> 2712316SN/Avoid 2722843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2732316SN/A{ 2742348SN/A // Clear any state, fix up the rename map. 2752307SN/A for (int i = 0; i < numThreads; i++) { 2762980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2772980Sgblack@eecs.umich.edu historyBuffer[i].begin(); 2782307SN/A 2792307SN/A while (!historyBuffer[i].empty()) { 2802307SN/A assert(hb_it != historyBuffer[i].end()); 2812307SN/A 2822307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2832307SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2842307SN/A 2852307SN/A // Tell the rename map to set the architected register to the 2862307SN/A // previous physical register that it was renamed to. 2872307SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2882307SN/A 2892307SN/A // Put the renamed physical register back on the free list. 2902307SN/A freeList->addReg(hb_it->newPhysReg); 2912307SN/A 2922361SN/A // Be sure to mark its register as ready if it's a misc register. 2932361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2942361SN/A scoreboard->setReg(hb_it->newPhysReg); 2952361SN/A } 2962361SN/A 2972307SN/A historyBuffer[i].erase(hb_it++); 2982307SN/A } 2992307SN/A insts[i].clear(); 3002307SN/A skidBuffer[i].clear(); 3011060SN/A } 3021060SN/A} 3031060SN/A 3041061SN/Atemplate <class Impl> 3051060SN/Avoid 3062307SN/ADefaultRename<Impl>::takeOverFrom() 3071060SN/A{ 3082307SN/A _status = Inactive; 3092307SN/A initStage(); 3101060SN/A 3112329SN/A // Reset all state prior to taking over from the other CPU. 3122307SN/A for (int i=0; i< numThreads; i++) { 3132307SN/A renameStatus[i] = Idle; 3141060SN/A 3152307SN/A stalls[i].iew = false; 3162307SN/A stalls[i].commit = false; 3172307SN/A serializeInst[i] = NULL; 3182307SN/A 3192307SN/A instsInProgress[i] = 0; 3202307SN/A 3212307SN/A emptyROB[i] = true; 3222307SN/A 3232307SN/A serializeOnNextInst[i] = false; 3242307SN/A } 3252307SN/A} 3262307SN/A 3272307SN/Atemplate <class Impl> 3282307SN/Avoid 3292935Sksewell@umich.eduDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 3301858SN/A{ 3312292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3321858SN/A 3332292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3342292SN/A // If it still needs to block, the blocking should happen the next 3352292SN/A // cycle and there should be space to hold everything due to the squash. 3362292SN/A if (renameStatus[tid] == Blocked || 3372292SN/A renameStatus[tid] == Unblocking || 3382301SN/A renameStatus[tid] == SerializeStall) { 3392698Sktlim@umich.edu 3402292SN/A toDecode->renameUnblock[tid] = 1; 3412698Sktlim@umich.edu 3422301SN/A serializeInst[tid] = NULL; 3432292SN/A } 3442292SN/A 3452292SN/A // Set the status to Squashing. 3462292SN/A renameStatus[tid] = Squashing; 3472292SN/A 3482329SN/A // Squash any instructions from decode. 3492292SN/A unsigned squashCount = 0; 3502292SN/A 3512292SN/A for (int i=0; i<fromDecode->size; i++) { 3522935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3532935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3542731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3552292SN/A wroteToTimeBuffer = true; 3562292SN/A squashCount++; 3572292SN/A } 3582935Sksewell@umich.edu 3592292SN/A } 3602292SN/A 3612935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3622935Sksewell@umich.edu // insts in them. Since we support multiple ISAs, we cant just: 3632935Sksewell@umich.edu // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is 3642935Sksewell@umich.edu // a possible delay slot inst for different architectures 3652935Sksewell@umich.edu // insts[tid].clear(); 3663093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3672935Sksewell@umich.edu DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " 3682935Sksewell@umich.edu "[sn:%i].\n",tid, squash_seq_num); 3692935Sksewell@umich.edu ListIt ilist_it = insts[tid].begin(); 3702935Sksewell@umich.edu while (ilist_it != insts[tid].end()) { 3712935Sksewell@umich.edu if ((*ilist_it)->seqNum > squash_seq_num) { 3722935Sksewell@umich.edu (*ilist_it)->setSquashed(); 3732935Sksewell@umich.edu DPRINTF(Rename, "Squashing incoming decode instruction, " 3742935Sksewell@umich.edu "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC); 3752935Sksewell@umich.edu } 3762935Sksewell@umich.edu ilist_it++; 3772935Sksewell@umich.edu } 3783093Sksewell@umich.edu#else 3793093Sksewell@umich.edu insts[tid].clear(); 3802935Sksewell@umich.edu#endif 3812292SN/A 3822292SN/A // Clear the skid buffer in case it has any data in it. 3832935Sksewell@umich.edu // See comments above. 3842935Sksewell@umich.edu // skidBuffer[tid].clear(); 3853093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3862935Sksewell@umich.edu DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " 3872935Sksewell@umich.edu "until [sn:%i].\n", tid, squash_seq_num); 3882935Sksewell@umich.edu ListIt slist_it = skidBuffer[tid].begin(); 3892935Sksewell@umich.edu while (slist_it != skidBuffer[tid].end()) { 3902935Sksewell@umich.edu if ((*slist_it)->seqNum > squash_seq_num) { 3912935Sksewell@umich.edu (*slist_it)->setSquashed(); 3922935Sksewell@umich.edu DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]" 3932935Sksewell@umich.edu "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC); 3942935Sksewell@umich.edu } 3952935Sksewell@umich.edu slist_it++; 3962935Sksewell@umich.edu } 3973093Sksewell@umich.edu#else 3983093Sksewell@umich.edu skidBuffer[tid].clear(); 3992935Sksewell@umich.edu#endif 4002935Sksewell@umich.edu doSquash(squash_seq_num, tid); 4012292SN/A} 4022292SN/A 4032292SN/Atemplate <class Impl> 4042292SN/Avoid 4052292SN/ADefaultRename<Impl>::tick() 4062292SN/A{ 4072292SN/A wroteToTimeBuffer = false; 4082292SN/A 4092292SN/A blockThisCycle = false; 4102292SN/A 4112292SN/A bool status_change = false; 4122292SN/A 4132292SN/A toIEWIndex = 0; 4142292SN/A 4152292SN/A sortInsts(); 4162292SN/A 4172980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4182292SN/A 4192292SN/A // Check stall and squash signals. 4202292SN/A while (threads != (*activeThreads).end()) { 4212292SN/A unsigned tid = *threads++; 4222292SN/A 4232292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4242292SN/A 4252292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4262292SN/A 4272292SN/A rename(status_change, tid); 4282292SN/A } 4292292SN/A 4302292SN/A if (status_change) { 4312292SN/A updateStatus(); 4322292SN/A } 4332292SN/A 4342292SN/A if (wroteToTimeBuffer) { 4352292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4362292SN/A cpu->activityThisCycle(); 4372292SN/A } 4382292SN/A 4392292SN/A threads = (*activeThreads).begin(); 4402292SN/A 4412292SN/A while (threads != (*activeThreads).end()) { 4422292SN/A unsigned tid = *threads++; 4432292SN/A 4442292SN/A // If we committed this cycle then doneSeqNum will be > 0 4452292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4462292SN/A !fromCommit->commitInfo[tid].squash && 4472292SN/A renameStatus[tid] != Squashing) { 4482292SN/A 4492292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4502292SN/A tid); 4512292SN/A } 4522292SN/A } 4532292SN/A 4542292SN/A // @todo: make into updateProgress function 4552292SN/A for (int tid=0; tid < numThreads; tid++) { 4562292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4572292SN/A 4582292SN/A assert(instsInProgress[tid] >=0); 4592292SN/A } 4602292SN/A 4612292SN/A} 4622292SN/A 4632292SN/Atemplate<class Impl> 4642292SN/Avoid 4652292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4662292SN/A{ 4672292SN/A // If status is Running or idle, 4682292SN/A // call renameInsts() 4692292SN/A // If status is Unblocking, 4702292SN/A // buffer any instructions coming from decode 4712292SN/A // continue trying to empty skid buffer 4722292SN/A // check if stall conditions have passed 4732292SN/A 4742292SN/A if (renameStatus[tid] == Blocked) { 4752292SN/A ++renameBlockCycles; 4762292SN/A } else if (renameStatus[tid] == Squashing) { 4772292SN/A ++renameSquashCycles; 4782301SN/A } else if (renameStatus[tid] == SerializeStall) { 4792301SN/A ++renameSerializeStallCycles; 4802292SN/A } 4812292SN/A 4822292SN/A if (renameStatus[tid] == Running || 4832292SN/A renameStatus[tid] == Idle) { 4842292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4852292SN/A "stage.\n", tid); 4862292SN/A 4872292SN/A renameInsts(tid); 4882292SN/A } else if (renameStatus[tid] == Unblocking) { 4892292SN/A renameInsts(tid); 4902292SN/A 4912292SN/A if (validInsts()) { 4922292SN/A // Add the current inputs to the skid buffer so they can be 4932292SN/A // reprocessed when this stage unblocks. 4942292SN/A skidInsert(tid); 4952292SN/A } 4962292SN/A 4972292SN/A // If we switched over to blocking, then there's a potential for 4982292SN/A // an overall status change. 4992292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5001858SN/A } 5011858SN/A} 5021858SN/A 5031858SN/Atemplate <class Impl> 5041858SN/Avoid 5052292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 5061858SN/A{ 5072292SN/A // Instructions can be either in the skid buffer or the queue of 5082292SN/A // instructions coming from decode, depending on the status. 5092292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5102292SN/A skidBuffer[tid].size() : insts[tid].size(); 5111858SN/A 5122292SN/A // Check the decode queue to see if instructions are available. 5132292SN/A // If there are no available instructions to rename, then do nothing. 5142292SN/A if (insts_available == 0) { 5152292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5162292SN/A tid); 5172292SN/A // Should I change status to idle? 5182292SN/A ++renameIdleCycles; 5192292SN/A return; 5202292SN/A } else if (renameStatus[tid] == Unblocking) { 5212292SN/A ++renameUnblockCycles; 5222292SN/A } else if (renameStatus[tid] == Running) { 5232292SN/A ++renameRunCycles; 5242292SN/A } 5251858SN/A 5262292SN/A DynInstPtr inst; 5272292SN/A 5282292SN/A // Will have to do a different calculation for the number of free 5292292SN/A // entries. 5302292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5312292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5322292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5332292SN/A int min_free_entries = free_rob_entries; 5342292SN/A 5352292SN/A FullSource source = ROB; 5362292SN/A 5372292SN/A if (free_iq_entries < min_free_entries) { 5382292SN/A min_free_entries = free_iq_entries; 5392292SN/A source = IQ; 5402292SN/A } 5412292SN/A 5422292SN/A if (free_lsq_entries < min_free_entries) { 5432292SN/A min_free_entries = free_lsq_entries; 5442292SN/A source = LSQ; 5452292SN/A } 5462292SN/A 5472292SN/A // Check if there's any space left. 5482292SN/A if (min_free_entries <= 0) { 5492292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5502292SN/A "entries.\n" 5512292SN/A "ROB has %i free entries.\n" 5522292SN/A "IQ has %i free entries.\n" 5532292SN/A "LSQ has %i free entries.\n", 5542292SN/A tid, 5552292SN/A free_rob_entries, 5562292SN/A free_iq_entries, 5572292SN/A free_lsq_entries); 5582292SN/A 5592292SN/A blockThisCycle = true; 5602292SN/A 5612292SN/A block(tid); 5622292SN/A 5632292SN/A incrFullStat(source); 5642292SN/A 5652292SN/A return; 5662292SN/A } else if (min_free_entries < insts_available) { 5672292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5682292SN/A "%i insts available, but only %i insts can be " 5692292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5702292SN/A tid, insts_available, min_free_entries); 5712292SN/A 5722292SN/A insts_available = min_free_entries; 5732292SN/A 5742292SN/A blockThisCycle = true; 5752292SN/A 5762292SN/A incrFullStat(source); 5772292SN/A } 5782292SN/A 5792292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5802292SN/A skidBuffer[tid] : insts[tid]; 5812292SN/A 5822292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5832292SN/A "send iew.\n", tid, insts_available); 5842292SN/A 5852292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5862292SN/A "dispatched to IQ last cycle.\n", 5872292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5882292SN/A 5892292SN/A // Handle serializing the next instruction if necessary. 5902292SN/A if (serializeOnNextInst[tid]) { 5912292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5922292SN/A // ROB already empty; no need to serialize. 5932292SN/A serializeOnNextInst[tid] = false; 5942292SN/A } else if (!insts_to_rename.empty()) { 5952292SN/A insts_to_rename.front()->setSerializeBefore(); 5962292SN/A } 5972292SN/A } 5982292SN/A 5992292SN/A int renamed_insts = 0; 6002292SN/A 6012292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6022292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6032292SN/A 6042292SN/A assert(!insts_to_rename.empty()); 6052292SN/A 6062292SN/A inst = insts_to_rename.front(); 6072292SN/A 6082292SN/A insts_to_rename.pop_front(); 6092292SN/A 6102292SN/A if (renameStatus[tid] == Unblocking) { 6112292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 6122292SN/A "skidBuffer\n", 6132292SN/A tid, inst->seqNum, inst->readPC()); 6142292SN/A } 6152292SN/A 6162292SN/A if (inst->isSquashed()) { 6172292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 6182292SN/A "squashed, skipping.\n", 6192935Sksewell@umich.edu tid, inst->seqNum, inst->readPC()); 6202292SN/A 6212292SN/A ++renameSquashedInsts; 6222292SN/A 6232292SN/A // Decrement how many instructions are available. 6242292SN/A --insts_available; 6252292SN/A 6262292SN/A continue; 6272292SN/A } 6282292SN/A 6292292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6302292SN/A "PC %#x.\n", 6312292SN/A tid, inst->seqNum, inst->readPC()); 6322292SN/A 6332292SN/A // Handle serializeAfter/serializeBefore instructions. 6342292SN/A // serializeAfter marks the next instruction as serializeBefore. 6352292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6362292SN/A // is empty. 6372336SN/A 6382336SN/A // In this model, IPR accesses are serialize before 6392336SN/A // instructions, and store conditionals are serialize after 6402336SN/A // instructions. This is mainly due to lack of support for 6412336SN/A // out-of-order operations of either of those classes of 6422336SN/A // instructions. 6432336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6442336SN/A !inst->isSerializeHandled()) { 6452292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6462292SN/A 6472301SN/A if (!inst->isTempSerializeBefore()) { 6482301SN/A renamedSerializing++; 6492292SN/A inst->setSerializeHandled(); 6502301SN/A } else { 6512301SN/A renamedTempSerializing++; 6522301SN/A } 6532292SN/A 6542301SN/A // Change status over to SerializeStall so that other stages know 6552292SN/A // what this is blocked on. 6562301SN/A renameStatus[tid] = SerializeStall; 6572292SN/A 6582301SN/A serializeInst[tid] = inst; 6592292SN/A 6602292SN/A blockThisCycle = true; 6612292SN/A 6622292SN/A break; 6632336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6642336SN/A !inst->isSerializeHandled()) { 6652292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6662292SN/A 6672307SN/A renamedSerializing++; 6682307SN/A 6692292SN/A inst->setSerializeHandled(); 6702292SN/A 6712292SN/A serializeAfter(insts_to_rename, tid); 6722292SN/A } 6732292SN/A 6742292SN/A // Check here to make sure there are enough destination registers 6752292SN/A // to rename to. Otherwise block. 6762292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6772292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6782292SN/A "physical registers to rename to.\n"); 6792292SN/A blockThisCycle = true; 6802292SN/A 6812292SN/A ++renameFullRegistersEvents; 6822292SN/A 6832292SN/A break; 6842292SN/A } 6852292SN/A 6862292SN/A renameSrcRegs(inst, inst->threadNumber); 6872292SN/A 6882292SN/A renameDestRegs(inst, inst->threadNumber); 6892292SN/A 6902292SN/A ++renamed_insts; 6912292SN/A 6922292SN/A // Put instruction in rename queue. 6932292SN/A toIEW->insts[toIEWIndex] = inst; 6942292SN/A ++(toIEW->size); 6952292SN/A 6962292SN/A // Increment which instruction we're on. 6972292SN/A ++toIEWIndex; 6982292SN/A 6992292SN/A // Decrement how many instructions are available. 7002292SN/A --insts_available; 7012292SN/A } 7022292SN/A 7032292SN/A instsInProgress[tid] += renamed_insts; 7042307SN/A renameRenamedInsts += renamed_insts; 7052292SN/A 7062292SN/A // If we wrote to the time buffer, record this. 7072292SN/A if (toIEWIndex) { 7082292SN/A wroteToTimeBuffer = true; 7092292SN/A } 7102292SN/A 7112292SN/A // Check if there's any instructions left that haven't yet been renamed. 7122292SN/A // If so then block. 7132292SN/A if (insts_available) { 7142292SN/A blockThisCycle = true; 7152292SN/A } 7162292SN/A 7172292SN/A if (blockThisCycle) { 7182292SN/A block(tid); 7192292SN/A toDecode->renameUnblock[tid] = false; 7202292SN/A } 7212292SN/A} 7222292SN/A 7232292SN/Atemplate<class Impl> 7242292SN/Avoid 7252292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 7262292SN/A{ 7272292SN/A DynInstPtr inst = NULL; 7282292SN/A 7292292SN/A while (!insts[tid].empty()) { 7302292SN/A inst = insts[tid].front(); 7312292SN/A 7322292SN/A insts[tid].pop_front(); 7332292SN/A 7342292SN/A assert(tid == inst->threadNumber); 7352292SN/A 7362292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 7372292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 7382292SN/A 7392307SN/A ++renameSkidInsts; 7402307SN/A 7412292SN/A skidBuffer[tid].push_back(inst); 7422292SN/A } 7432292SN/A 7442292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7452292SN/A panic("Skidbuffer Exceeded Max Size"); 7462292SN/A} 7472292SN/A 7482292SN/Atemplate <class Impl> 7492292SN/Avoid 7502292SN/ADefaultRename<Impl>::sortInsts() 7512292SN/A{ 7522292SN/A int insts_from_decode = fromDecode->size; 7532329SN/A#ifdef DEBUG 7543093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT 7552292SN/A for (int i=0; i < numThreads; i++) 7562292SN/A assert(insts[i].empty()); 7572329SN/A#endif 7582935Sksewell@umich.edu#endif 7592292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7602292SN/A DynInstPtr inst = fromDecode->insts[i]; 7612292SN/A insts[inst->threadNumber].push_back(inst); 7622292SN/A } 7632292SN/A} 7642292SN/A 7652292SN/Atemplate<class Impl> 7662292SN/Abool 7672292SN/ADefaultRename<Impl>::skidsEmpty() 7682292SN/A{ 7692980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 7702292SN/A 7712292SN/A while (threads != (*activeThreads).end()) { 7722292SN/A if (!skidBuffer[*threads++].empty()) 7732292SN/A return false; 7742292SN/A } 7752292SN/A 7762292SN/A return true; 7772292SN/A} 7782292SN/A 7792292SN/Atemplate<class Impl> 7802292SN/Avoid 7812292SN/ADefaultRename<Impl>::updateStatus() 7822292SN/A{ 7832292SN/A bool any_unblocking = false; 7842292SN/A 7852980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 7862292SN/A 7872292SN/A threads = (*activeThreads).begin(); 7882292SN/A 7892292SN/A while (threads != (*activeThreads).end()) { 7902292SN/A unsigned tid = *threads++; 7912292SN/A 7922292SN/A if (renameStatus[tid] == Unblocking) { 7932292SN/A any_unblocking = true; 7942292SN/A break; 7952292SN/A } 7962292SN/A } 7972292SN/A 7982292SN/A // Rename will have activity if it's unblocking. 7992292SN/A if (any_unblocking) { 8002292SN/A if (_status == Inactive) { 8012292SN/A _status = Active; 8022292SN/A 8032292SN/A DPRINTF(Activity, "Activating stage.\n"); 8042292SN/A 8052733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8062292SN/A } 8072292SN/A } else { 8082292SN/A // If it's not unblocking, then rename will not have any internal 8092292SN/A // activity. Switch it to inactive. 8102292SN/A if (_status == Active) { 8112292SN/A _status = Inactive; 8122292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8132292SN/A 8142733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8152292SN/A } 8162292SN/A } 8172292SN/A} 8182292SN/A 8192292SN/Atemplate <class Impl> 8202292SN/Abool 8212292SN/ADefaultRename<Impl>::block(unsigned tid) 8222292SN/A{ 8232292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8242292SN/A 8252292SN/A // Add the current inputs onto the skid buffer, so they can be 8262292SN/A // reprocessed when this stage unblocks. 8272292SN/A skidInsert(tid); 8282292SN/A 8292292SN/A // Only signal backwards to block if the previous stages do not think 8302292SN/A // rename is already blocked. 8312292SN/A if (renameStatus[tid] != Blocked) { 8322292SN/A if (renameStatus[tid] != Unblocking) { 8332292SN/A toDecode->renameBlock[tid] = true; 8342292SN/A toDecode->renameUnblock[tid] = false; 8352292SN/A wroteToTimeBuffer = true; 8362292SN/A } 8372292SN/A 8382329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8392329SN/A // it would not know to complete the serialize stall. 8402301SN/A if (renameStatus[tid] != SerializeStall) { 8412292SN/A // Set status to Blocked. 8422292SN/A renameStatus[tid] = Blocked; 8432292SN/A return true; 8442292SN/A } 8452292SN/A } 8462292SN/A 8472292SN/A return false; 8482292SN/A} 8492292SN/A 8502292SN/Atemplate <class Impl> 8512292SN/Abool 8522292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8532292SN/A{ 8542292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8552292SN/A 8562292SN/A // Rename is done unblocking if the skid buffer is empty. 8572301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8582292SN/A 8592292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8602292SN/A 8612292SN/A toDecode->renameUnblock[tid] = true; 8622292SN/A wroteToTimeBuffer = true; 8632292SN/A 8642292SN/A renameStatus[tid] = Running; 8652292SN/A return true; 8662292SN/A } 8672292SN/A 8682292SN/A return false; 8692292SN/A} 8702292SN/A 8712292SN/Atemplate <class Impl> 8722292SN/Avoid 8732935Sksewell@umich.eduDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 8742292SN/A{ 8752980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8762980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8772292SN/A 8781060SN/A // After a syscall squashes everything, the history buffer may be empty 8791060SN/A // but the ROB may still be squashing instructions. 8802292SN/A if (historyBuffer[tid].empty()) { 8811060SN/A return; 8821060SN/A } 8831060SN/A 8841060SN/A // Go through the most recent instructions, undoing the mappings 8851060SN/A // they did and freeing up the registers. 8862292SN/A while (!historyBuffer[tid].empty() && 8872292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8882292SN/A assert(hb_it != historyBuffer[tid].end()); 8891062SN/A 8902292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8912292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8921060SN/A 8932292SN/A // Tell the rename map to set the architected register to the 8942292SN/A // previous physical register that it was renamed to. 8952292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8961060SN/A 8972292SN/A // Put the renamed physical register back on the free list. 8982292SN/A freeList->addReg(hb_it->newPhysReg); 8991062SN/A 9002367SN/A // Be sure to mark its register as ready if it's a misc register. 9012367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9022367SN/A scoreboard->setReg(hb_it->newPhysReg); 9032367SN/A } 9042367SN/A 9052292SN/A historyBuffer[tid].erase(hb_it++); 9061061SN/A 9071062SN/A ++renameUndoneMaps; 9081060SN/A } 9091060SN/A} 9101060SN/A 9111060SN/Atemplate<class Impl> 9121060SN/Avoid 9132292SN/ADefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 9141060SN/A{ 9152292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9162292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9172292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9182292SN/A 9192980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9202980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9211060SN/A 9221061SN/A --hb_it; 9231060SN/A 9242292SN/A if (historyBuffer[tid].empty()) { 9252292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9262292SN/A return; 9272292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9282292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9292292SN/A "that a syscall happened recently.\n", tid); 9301060SN/A return; 9311060SN/A } 9321060SN/A 9332292SN/A // Commit all the renames up until (and including) the committed sequence 9342292SN/A // number. Some or even all of the committed instructions may not have 9352292SN/A // rename histories if they did not have destination registers that were 9362292SN/A // renamed. 9372292SN/A while (!historyBuffer[tid].empty() && 9382292SN/A hb_it != historyBuffer[tid].end() && 9392292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9401060SN/A 9412329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9422329SN/A "[sn:%lli].\n", 9432292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9441061SN/A 9452292SN/A freeList->addReg((*hb_it).prevPhysReg); 9462292SN/A ++renameCommittedMaps; 9471061SN/A 9482292SN/A historyBuffer[tid].erase(hb_it--); 9491060SN/A } 9501060SN/A} 9511060SN/A 9521061SN/Atemplate <class Impl> 9531061SN/Ainline void 9542292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9551061SN/A{ 9562292SN/A assert(renameMap[tid] != 0); 9572292SN/A 9581061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9591061SN/A 9601061SN/A // Get the architectual register numbers from the source and 9611061SN/A // destination operands, and redirect them to the right register. 9621061SN/A // Will need to mark dependencies though. 9632292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9641061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9653773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9663773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9673773Sgblack@eecs.umich.edu flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 9683773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 9693773Sgblack@eecs.umich.edu } 9703773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 9711061SN/A 9721061SN/A // Look up the source registers to get the phys. register they've 9731061SN/A // been renamed to, and set the sources to those registers. 9743773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 9751061SN/A 9762292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9773773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 9782292SN/A (int)renamed_reg); 9791061SN/A 9801061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9811061SN/A 9822292SN/A // See if the register is ready or not. 9832292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9842292SN/A DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 9851061SN/A 9861061SN/A inst->markSrcRegReady(src_idx); 9871061SN/A } 9881062SN/A 9891062SN/A ++renameRenameLookups; 9901061SN/A } 9911061SN/A} 9921061SN/A 9931061SN/Atemplate <class Impl> 9941061SN/Ainline void 9952292SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 9961061SN/A{ 9972292SN/A typename RenameMap::RenameInfo rename_result; 9981061SN/A 9991061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10001061SN/A 10012292SN/A // Rename the destination registers. 10022292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10032292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10043773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10053773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10063773Sgblack@eecs.umich.edu flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 10073773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 10083773Sgblack@eecs.umich.edu } 10093773Sgblack@eecs.umich.edu 10103773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10111061SN/A 10122292SN/A // Get the physical register that the destination will be 10132292SN/A // renamed to. 10143773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10151061SN/A 10162292SN/A //Mark Scoreboard entry as not ready 10172292SN/A scoreboard->unsetReg(rename_result.first); 10181062SN/A 10192292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10203773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10212292SN/A (int)rename_result.first); 10221062SN/A 10232292SN/A // Record the rename information so that a history can be kept. 10243773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10252292SN/A rename_result.first, 10262292SN/A rename_result.second); 10271062SN/A 10282292SN/A historyBuffer[tid].push_front(hb_entry); 10291062SN/A 10302935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10312935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10322935Sksewell@umich.edu historyBuffer[tid].size(), 10332292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10341062SN/A 10352292SN/A // Tell the instruction to rename the appropriate destination 10362292SN/A // register (dest_idx) to the new physical register 10372292SN/A // (rename_result.first), and record the previous physical 10382292SN/A // register that the same logical register was renamed to 10392292SN/A // (rename_result.second). 10402292SN/A inst->renameDestReg(dest_idx, 10412292SN/A rename_result.first, 10422292SN/A rename_result.second); 10431062SN/A 10442292SN/A ++renameRenamedOperands; 10451061SN/A } 10461061SN/A} 10471061SN/A 10481061SN/Atemplate <class Impl> 10491061SN/Ainline int 10502292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 10511061SN/A{ 10522292SN/A int num_free = freeEntries[tid].robEntries - 10532292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10542292SN/A 10552292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10562292SN/A 10572292SN/A return num_free; 10581061SN/A} 10591061SN/A 10601061SN/Atemplate <class Impl> 10611061SN/Ainline int 10622292SN/ADefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 10631061SN/A{ 10642292SN/A int num_free = freeEntries[tid].iqEntries - 10652292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10662292SN/A 10672292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10682292SN/A 10692292SN/A return num_free; 10702292SN/A} 10712292SN/A 10722292SN/Atemplate <class Impl> 10732292SN/Ainline int 10742292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 10752292SN/A{ 10762292SN/A int num_free = freeEntries[tid].lsqEntries - 10772292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10782292SN/A 10792292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 10802292SN/A 10812292SN/A return num_free; 10822292SN/A} 10832292SN/A 10842292SN/Atemplate <class Impl> 10852292SN/Aunsigned 10862292SN/ADefaultRename<Impl>::validInsts() 10872292SN/A{ 10882292SN/A unsigned inst_count = 0; 10892292SN/A 10902292SN/A for (int i=0; i<fromDecode->size; i++) { 10912731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 10922292SN/A inst_count++; 10932292SN/A } 10942292SN/A 10952292SN/A return inst_count; 10962292SN/A} 10972292SN/A 10982292SN/Atemplate <class Impl> 10992292SN/Avoid 11002292SN/ADefaultRename<Impl>::readStallSignals(unsigned tid) 11012292SN/A{ 11022292SN/A if (fromIEW->iewBlock[tid]) { 11032292SN/A stalls[tid].iew = true; 11042292SN/A } 11052292SN/A 11062292SN/A if (fromIEW->iewUnblock[tid]) { 11072292SN/A assert(stalls[tid].iew); 11082292SN/A stalls[tid].iew = false; 11092292SN/A } 11102292SN/A 11112292SN/A if (fromCommit->commitBlock[tid]) { 11122292SN/A stalls[tid].commit = true; 11132292SN/A } 11142292SN/A 11152292SN/A if (fromCommit->commitUnblock[tid]) { 11162292SN/A assert(stalls[tid].commit); 11172292SN/A stalls[tid].commit = false; 11182292SN/A } 11192292SN/A} 11202292SN/A 11212292SN/Atemplate <class Impl> 11222292SN/Abool 11232292SN/ADefaultRename<Impl>::checkStall(unsigned tid) 11242292SN/A{ 11252292SN/A bool ret_val = false; 11262292SN/A 11272292SN/A if (stalls[tid].iew) { 11282292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11292292SN/A ret_val = true; 11302292SN/A } else if (stalls[tid].commit) { 11312292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11322292SN/A ret_val = true; 11332292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11342292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11352292SN/A ret_val = true; 11362292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11372292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11382292SN/A ret_val = true; 11392292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11402292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11412292SN/A ret_val = true; 11422292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11432292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11442292SN/A ret_val = true; 11452301SN/A } else if (renameStatus[tid] == SerializeStall && 11462292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11472301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11482292SN/A "empty.\n", 11492292SN/A tid); 11502292SN/A ret_val = true; 11512292SN/A } 11522292SN/A 11532292SN/A return ret_val; 11542292SN/A} 11552292SN/A 11562292SN/Atemplate <class Impl> 11572292SN/Avoid 11582292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 11592292SN/A{ 11602292SN/A bool updated = false; 11612292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 11622292SN/A freeEntries[tid].iqEntries = 11632292SN/A fromIEW->iewInfo[tid].freeIQEntries; 11642292SN/A updated = true; 11652292SN/A } 11662292SN/A 11672292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11682292SN/A freeEntries[tid].lsqEntries = 11692292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 11702292SN/A updated = true; 11712292SN/A } 11722292SN/A 11732292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11742292SN/A freeEntries[tid].robEntries = 11752292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11762292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11772292SN/A updated = true; 11782292SN/A } 11792292SN/A 11802292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11812292SN/A tid, 11822292SN/A freeEntries[tid].iqEntries, 11832292SN/A freeEntries[tid].robEntries, 11842292SN/A freeEntries[tid].lsqEntries); 11852292SN/A 11862292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 11872292SN/A tid, instsInProgress[tid]); 11882292SN/A} 11892292SN/A 11902292SN/Atemplate <class Impl> 11912292SN/Abool 11922292SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 11932292SN/A{ 11942292SN/A // Check if there's a squash signal, squash if there is 11952292SN/A // Check stall signals, block if necessary. 11962292SN/A // If status was blocked 11972292SN/A // check if stall conditions have passed 11982292SN/A // if so then go to unblocking 11992292SN/A // If status was Squashing 12002292SN/A // check if squashing is not high. Switch to running this cycle. 12012301SN/A // If status was serialize stall 12022292SN/A // check if ROB is empty and no insts are in flight to the ROB 12032292SN/A 12042292SN/A readFreeEntries(tid); 12052292SN/A readStallSignals(tid); 12062292SN/A 12072292SN/A if (fromCommit->commitInfo[tid].squash) { 12082292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12092292SN/A "commit.\n", tid); 12102292SN/A 12113093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 12123093Sksewell@umich.edu InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 12133093Sksewell@umich.edu#else 12142935Sksewell@umich.edu InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 12152935Sksewell@umich.edu#endif 12162935Sksewell@umich.edu 12172935Sksewell@umich.edu squash(squashed_seq_num, tid); 12182292SN/A 12192292SN/A return true; 12202292SN/A } 12212292SN/A 12222292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12232292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12242292SN/A 12252292SN/A renameStatus[tid] = Squashing; 12262292SN/A 12272292SN/A return true; 12282292SN/A } 12292292SN/A 12302292SN/A if (checkStall(tid)) { 12312292SN/A return block(tid); 12322292SN/A } 12332292SN/A 12342292SN/A if (renameStatus[tid] == Blocked) { 12352292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12362292SN/A tid); 12372292SN/A 12382292SN/A renameStatus[tid] = Unblocking; 12392292SN/A 12402292SN/A unblock(tid); 12412292SN/A 12422292SN/A return true; 12432292SN/A } 12442292SN/A 12452292SN/A if (renameStatus[tid] == Squashing) { 12462292SN/A // Switch status to running if rename isn't being told to block or 12472292SN/A // squash this cycle. 12482292SN/A DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12492292SN/A tid); 12502292SN/A 12512292SN/A renameStatus[tid] = Running; 12522292SN/A 12532292SN/A return false; 12542292SN/A } 12552292SN/A 12562301SN/A if (renameStatus[tid] == SerializeStall) { 12572292SN/A // Stall ends once the ROB is free. 12582301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 12592292SN/A "unblocking.\n", tid); 12602292SN/A 12612301SN/A DynInstPtr serial_inst = serializeInst[tid]; 12622292SN/A 12632292SN/A renameStatus[tid] = Unblocking; 12642292SN/A 12652292SN/A unblock(tid); 12662292SN/A 12672292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 12682292SN/A "PC %#x.\n", 12692301SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 12702292SN/A 12712292SN/A // Put instruction into queue here. 12722301SN/A serial_inst->clearSerializeBefore(); 12732292SN/A 12742292SN/A if (!skidBuffer[tid].empty()) { 12752301SN/A skidBuffer[tid].push_front(serial_inst); 12762292SN/A } else { 12772301SN/A insts[tid].push_front(serial_inst); 12782292SN/A } 12792292SN/A 12802292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 12812703Sktlim@umich.edu " Adding to front of list.\n", tid); 12822292SN/A 12832301SN/A serializeInst[tid] = NULL; 12842292SN/A 12852292SN/A return true; 12862292SN/A } 12872292SN/A 12882292SN/A // If we've reached this point, we have not gotten any signals that 12892292SN/A // cause rename to change its status. Rename remains the same as before. 12902292SN/A return false; 12911061SN/A} 12921061SN/A 12931060SN/Atemplate<class Impl> 12941060SN/Avoid 12952292SN/ADefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 12962292SN/A unsigned tid) 12971060SN/A{ 12982292SN/A if (inst_list.empty()) { 12992292SN/A // Mark a bit to say that I must serialize on the next instruction. 13002292SN/A serializeOnNextInst[tid] = true; 13011060SN/A return; 13021060SN/A } 13031060SN/A 13042292SN/A // Set the next instruction as serializing. 13052292SN/A inst_list.front()->setSerializeBefore(); 13062292SN/A} 13072292SN/A 13082292SN/Atemplate <class Impl> 13092292SN/Ainline void 13102292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13112292SN/A{ 13122292SN/A switch (source) { 13132292SN/A case ROB: 13142292SN/A ++renameROBFullEvents; 13152292SN/A break; 13162292SN/A case IQ: 13172292SN/A ++renameIQFullEvents; 13182292SN/A break; 13192292SN/A case LSQ: 13202292SN/A ++renameLSQFullEvents; 13212292SN/A break; 13222292SN/A default: 13232292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13242292SN/A break; 13251060SN/A } 13262292SN/A} 13271060SN/A 13282292SN/Atemplate <class Impl> 13292292SN/Avoid 13302292SN/ADefaultRename<Impl>::dumpHistory() 13312292SN/A{ 13322980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13331060SN/A 13342292SN/A for (int i = 0; i < numThreads; i++) { 13351060SN/A 13362292SN/A buf_it = historyBuffer[i].begin(); 13371060SN/A 13382292SN/A while (buf_it != historyBuffer[i].end()) { 13392292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13402292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13412292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13421060SN/A 13432292SN/A buf_it++; 13441062SN/A } 13451060SN/A } 13461060SN/A} 1347